DETAILED ACTION
1. Claims 1-20 are pending in the application.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
3. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
4. Claims 6-10 is rejected under 35 U.S.C. 112(b) as being directed to unclear subject matter.
Claim 6 recites the limitation "the CTRL element" in line 4. There is insufficient antecedent basis for this limitation in the claim. It appears the intent is to recite control element not CTRL element.
Claims 7-10 are rejected for the same reasons as claim 6 as they do not overcome the deficiencies found in the claim from which they depend (claim 6).
Claim Rejections - 35 USC § 102
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
6. Claim(s) 1-5 and 14-17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pillai et al (hereafter Pillail)(US Pub. 20200026745).
7. As to claim 1, Pillai discloses a matrix operation accelerator (abstract accelerator), wherein the accelerator comprising:
comprises a control element, a memory, and a process element (PE) ([0121] and [0122] controller and memory, fig. 21 processing elements), wherein the control element is configured to receive a matrix operation instruction ([0079]-[0082] matrix operations);
the memory is configured to store subsets of a first matrix in a first storage space, store subsets of a second matrix in a second storage space, and store a third matrix in a third storage space, wherein the third matrix is a matrix comprising subsets of the third matrix obtained by multiplying the subsets of the first matrix by the subsets of the second matrix ([0221] subsets stored including matrix multiply, accumulate); and
the PE is configured to perform matrix operations on the subsets of the first matrix in the first storage space and the subsets of the second matrix in the second storage space based on the matrix operation instruction, to obtain matrix operation results ([0221] and [0230]).
8. As to claim 2, Pillai discloses the accelerator comprises a plurality of PEs, the plurality including the process element (fig. 24 processing elements).
9. As to claims 3 and 15, Pillai discloses the plurality of PEs are separately configured to perform parallel matrix operations on the subsets of the first matrix in the first storage space and the subsets of the second matrix in the second storage space based on the matrix operation instruction, to obtain the matrix operation results ([fig 24 and [0188] simultaneous operation of matrix operations).
10. As to claims 4 and 16, Pillai discloses wherein the PE is further configured to update subsets of the third matrix in the third storage space based on the matrix operation results, wherein the subsets of the third matrix are obtained after matrix operations are performed on the subsets of the first matrix and the subsets of the second matrix ([0209]-[0211]).
11. As to claims 5 and 17, Pillai discloses wherein the control element is further configured to partition the first matrix and the second matrix based on the matrix operation instruction, to obtain the subsets of the first matrix and the subsets of the second matrix ([0221] and [0230]).
12. As to claim 14, the claim is rejected for similar reasons as claim 1 above.
Allowable Subject Matter
13. Claims 6-10 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claims 11-13 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
14. The following is a statement of reasons for the indication of allowable subject matter:
The claims recite at least wherein the accelerator further comprises a direct memory access DMA, wherein the DMA is configured to: obtain N first subsets of the first matrix and N second subsets of the second matrix from a shared storage space based on a partitioning result of the CTRL element, and respectively store the N first subsets and the N second subsets in the first storage space and the second storage space of the memory, wherein N is greater than or equal to a quantity of PEs comprised in the accelerator, N is a positive integer, and the shared storage space is shared by a processor and the accelerator, as in claim 6;
and wherein the PE comprises: a multiplier and an adder, wherein a first input end and a second input end of the multiplier are respectively connected to the first storage space and the second storage space and an output end of the adder is connected to the third storage space; the multiplier is configured to multiply elements in the subset of the first matrix by elements in the subset of the second matrix; and the adder is configured to: add computing results of a plurality of multipliers to elements in current subsets of the third matrix in the third storage space, and update the elements in the subsets of the third matrix in the third storage space by using addition operation results, as in claim 11.
The closest prior art of record US Pub. 20200026745 teaches the matrix operation accelerator as in the claims. However, the prior art of record does not teach or suggest at least wherein the accelerator further comprises a direct memory access DMA, wherein the DMA is configured to: obtain N first subsets of the first matrix and N second subsets of the second matrix from a shared storage space based on a partitioning result of the CTRL element, and respectively store the N first subsets and the N second subsets in the first storage space and the second storage space of the memory, wherein N is greater than or equal to a quantity of PEs comprised in the accelerator, N is a positive integer, and the shared storage space is shared by a processor and the accelerator, as in claim 6;
and wherein the PE comprises: a multiplier and an adder, wherein a first input end and a second input end of the multiplier are respectively connected to the first storage space and the second storage space and an output end of the adder is connected to the third storage space; the multiplier is configured to multiply elements in the subset of the first matrix by elements in the subset of the second matrix; and the adder is configured to: add computing results of a plurality of multipliers to elements in current subsets of the third matrix in the third storage space, and update the elements in the subsets of the third matrix in the third storage space by using addition operation results, as in claim 11.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US Pub. 20200210517 – related to accelerating multiplication of sparse matrices. In one example, a processor is to fetch and decode an instruction having fields to specify locations of first, second, and third matrices, and an opcode indicating the processor is to multiply and accumulate matching non-zero (NZ) elements of the first and second matrices with corresponding elements of the third matrix, and executing the decoded instruction as per the opcode to generate NZ bitmasks for the first and second matrices, broadcast up to two NZ elements at a time from each row of the first matrix and each column of the second matrix to a processing engine (PE) grid, each PE to multiply and accumulate matching NZ elements of the first and second matrices with corresponding elements of the third matrix. Each PE further to store an NZ element for use in a subsequent multiplications.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL D YAARY whose telephone number is (571)270-1249. The examiner can normally be reached Mon-Fri 9-5:30.
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/MICHAEL D. YAARY/Primary Examiner, Art Unit 2151
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