Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 12/03/2025 have been fully considered but they are not persuasive.
The applicant contends that since the decoding scheme in Jiang is based on the teachings of Chari et al., that it is not obvious to combine or to move the CRC encoder so that it encodes source data prior to RS encoding.
The Examiner disagrees and asserts that Chari et al. moves away from the industry standard of including a CRC encoder only at the source so that the CRC bits as taught in Chari can participate in the iterative decoding at the decoder to improve the operation of the iterative decoder as well as the check for the integrity of received data whereas, in the industry standard whereby the CRC encoder is used to encode source data prior to error correction coding, the CRC bits at the destination are primarily used to check for integrity the receive data. The Examiner includes two new teaching arts: Figure 6 in Yoshii (US 20060195756 A1, hereafter referred to as Yoshii) teaches a CRC Adding 30 that provides CRC prior to outer and inner error correction encoding. Figures 8A & 8B in Park (US 6397367 B1) teach CRC generators 801 and 811 that provides CRC prior to channel coding.
The Applicant also contends that the prior art does not teach that the RS coder segments incoming data and the parity bits to create RS blocks.
The Examiner disagrees and asserts that Figure 4 in Jiang teaches that the RS encoder forms RS codeword blocks along the columns in Figure 4 to form RS codeword blocks comprising K data bytes and R parity bytes.
The Applicant also argues that such an arrangement would significantly modify the operations of the systems in Jiang because the size of data from one device to the next would be altered.
The Examiner would like to point out that RS encoder, interleaver and turbo encoder are not “black boxes” with random sizes there mathematically rigid the output of one must be input to the next. Calculating the buffer sizes, clock cycle and a parity bit overhead to ensure these blocks “fit” together is a standard engineering calculation (like calculating gear ratios in a transmission”, not a novel invention. Calculating the size of these blocks and determining the amount of redundancy in each of these blocks is a routine rate matching calculation required for any system.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-17 and 20-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jiang et al. (US 20120054585 A1, hereafter referred to as Jiang), Eidson et al. (US 20010025358 A1, hereafter referred to as Eidson), Howell et al. (US 4151510 A, hereafter referred to as Howell), Yoshii (US 20060195756 A1, hereafter referred to as Yoshii) and Park (US 6397367 B1, hereafter referred to as Park).
Rejection of claim 1:
The Examiner would like to point out that Chari et al., as described in the Applicant's remarks filed 12/03/2025, moves away from the industry standard of including a CRC encoder only at the source so that the CRC bits as taught in Chari can participate in the iterative decoding at the decoder to improve the operation of the iterative decoder as well as the check for the integrity of received data whereas, in the industry standard whereby the CRC encoder is used to encode source data prior to error correction coding, the CRC bits at the destination are primarily used to check for integrity the receive data. The Examiner includes two new teaching arts: Figure 6 in Yoshii (US 20060195756 A1, hereafter referred to as Yoshii) teaches a CRC Adding 30 that provides CRC prior to outer and inner error correction encoding. Figures 8A & 8B in Park (US 6397367 B1) teach CRC generators 801 and 811 that provides CRC prior to channel coding.
Jiang teaches A transmitter circuit providing forward error correction (Figure 3 in Jiang), comprising: a parity bit generator that generates parity bits based on a generator polynomial and appends the parity bits to incoming data (Paragraphs [0066]-[0069] in Jiang teaches CRC verification check for use in an iterative decoding procedure to verify conversions of an iterative decoding algorithm to a correct answer, which clearly suggests that the CRC encoder is used for encoding; note: it is well known in the art that CRC can be generated using a polynomial generator and that a polynomial generator inherently exists for CRC codes); a Reed-Solomon (RS) coder that creates RS blocks from the incoming data and the parity bits (Figure 3 in Jiang teaches Reed-Solomon encoder 320); an interleaver that interleaves symbols in the RS blocks to create turbo coder input blocks (Figure 3 in Jiang teaches interleaver 330); and a turbo encoder that uses the turbo coder input blocks to create a signal to be sent to a receiver (Figure 3 in Jiang teaches Turbo Encoder 340).
The Examiner would like to point out that Figure 4 in Jiang teaches that the RS encoder forms RS codeword blocks along the columns in Figure 4 to form RS codeword blocks comprising K data bytes and R parity bytes.
Jiang does not disclose when the CRC encoder applies the CRC code.
Eidson et al. (US 20010025358 A1, hereafter referred to as Eidson), in an analogous art, teaches the use of an external CRC encoder that applies a CRC code prior to outer encoding and inner encoding for use in an iterative turbo decoding algorithm. The abstract in Eidson teaches that a external CRC coder can enhance iterative decoding by identifying correctly decoded CRC blocks with a high degree of certainty.
The Examiner would like to point out that MPEP 2144.04(VI)(C) states that rearrangement of parts is held to be an obvious matter of design choice whenever such modification does not modify the operation of the device. In Jiang and Eidson, CRC bits are only used to verify whether the decoder has corrected data after decoding. Since CRC bits are parity bits attached to other data bits and used to verify whether the data bits are correct, the position of the CRC encoder does not change the operation of the error correction decoder in Jiang and Eidson.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Jiang with the teachings of Eidson by including use of an external CRC encoder. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, because one of ordinary skill in the art would have recognized that use of an external CRC encoder would have enhanced iterative decoding by identifying correctly decoded CRC blocks with a high degree of certainty (The abstract in Eidson).
Howell et al. (US 4151510 A, hereafter referred to as Howell) teaches the use of a generator polynomial for generating a CRC code (see abstract in Howell). Since it is well known in the art that CRC codes inherently have both a generator matrix and equivalent generator polynomial, choosing to use the generator polynomial is an obvious design choice.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Jiang and Eidson with the teachings of Howell by including use of a generator polynomial for generating a CRC code. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, because one of ordinary skill in the art would have recognized that use of a generator polynomial for generating a CRC code would have been an obvious design choice since CRC codes inherently have both a generator matrix and equivalent generator polynomial.
In regard claim 2, Jiang teaches:
The transmitter circuit of claim 1, further comprising: a Digital Signal Processor (DSP) that provides hardware for the turbo encoder and the parity bit generator
(Figure 2 in Jiang)
In regard to claim 3, Jiang teaches:
The transmitter circuit of claim 2, further comprising: software instructions running on the DSP to provide the RS coder and the interleaver.
(Figure 2 in Jiang)
In regard to claim 4, Jiang teaches:
The transmitter circuit of claim 1, wherein the size of the RS blocks is selected to match the input block size of the turbo coder so that an integer number of RS blocks are interleaved to create the turbo coder input blocks.
(Sections [0066]-[0067] in Jiang)
In regard to claim 5, Jiang teaches:
The transmitter circuit of claim 1, wherein the interleaver sequential fills the turbo input blocks with symbols from successive RS blocks.
(Sections [0066]-[0067] in Jiang)
In regard to claim 6, Jiang teaches:
The transmitter circuit of claim 1, wherein the CRC parity bit generator and the turbo encoder operate using parameters defined in a Long Term Evolution (LTE) standard.
(Sections [0043] and [0061] in Jiang)
Claims 7-12 are rejected for the same reasons as per claims 1-6.
In regard to claim 13, Jiang teaches:
A receiver circuit decoding forward error corrected signals, comprising:
(Figure 3 in Jiang)
a turbo decoder that decodes received signals to create turbo output blocks;
(Figure 3, ref. (370) in Jiang)
a de-interleaver that de-interleaves the turbo output blocks to create Reed-Solomon (RS) input blocks;
(Figure 3, ref. (380) in Jiang)
a Reed-Solomon decoder that receives the RS input blocks and generates decoded output data; and
(Figure 3, ref. (390) in Jiang)
a Cyclic Redundancy Check (CRC) parity bit check circuit that evaluates CRC bits in the decoded data.
(Section [0117] in Jiang)
Eidson et al. (US 20010025358 A1, hereafter referred to as Eidson), in an analogous art, teaches the use of an external CRC encoder that applies a CRC code prior to outer encoding and inner encoding for use in an iterative turbo decoding algorithm. The abstract in Eidson teaches that a external CRC coder can enhance iterative decoding by identifying correctly decoded CRC blocks with a high degree of certainty.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Jiang with the teachings of Eidson by including use of an external CRC encoder. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, because one of ordinary skill in the art would have recognized that use of an external CRC encoder would have enhanced iterative decoding by identifying correctly decoded CRC blocks with a high degree of certainty (The abstract in Eidson).
Howell et al. (US 4151510 A, hereafter referred to as Howell) teaches the use of a generator polynomial for generating a CRC code (see abstract in Howell). Since it is well known in the art that CRC codes inherently have both a generator matrix and equivalent generator polynomial, choosing to use the generator polynomial is an obvious design choice.
. In regard to claim 14, Jiang teaches:
The receiver circuit of claim 13, further comprising:
a Digital Signal Processor (DSP) that provides hardware for the turbo decoder and CRC parity bit check circuit.
(Figure 2 in Jiang)
In regard to claim 15, Jiang teaches:
The receiver circuit of claim 14, further comprising:
software instructions running on the DSP to provide the RS decoder and the de- interleaver.
(Figure 2 in Jiang)
In regard to claim 16, Jiang teaches:
The receiver circuit of claim 1, wherein the size of the RS blocks is selected to match the output block size of the turbo decoder so that an integer number of RS blocks are de-interleaved from the turbo decoder output blocks.
(Sections [0066]-[0067] in Jiang)
Claims 17-20 are rejected for the same reasons as per claims 13-15.
Rejection of claim 21:
The Examiner would like to point out that RS encoder, interleaver and turbo encoder are not “black boxes” with random sizes there mathematically rigid the output of one must be input to the next. Calculating the buffer sizes, clock cycle and a parity bit overhead to ensure these blocks “fit” together is a standard engineering calculation (like calculating gear ratios in a transmission”, not a novel invention. Calculating the size of these blocks and determining the amount of redundancy in each of these blocks is a routine rate matching calculation required for any system.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH D TORRES whose telephone number is (571)272-3829. The examiner can normally be reached on M-F, 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Albert Decady can be reached on 571-272-3819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOSEPH D TORRES/Primary Examiner, Art Unit 2112