Prosecution Insights
Last updated: May 29, 2026
Application No. 18/094,775

CHIP CARRIER

Non-Final OA §102§103
Filed
Jan 09, 2023
Priority
Jan 11, 2022 — FR 2200190
Examiner
KIM, PAUL D
Art Unit
3729
Tech Center
3700 — Mechanical Engineering & Manufacturing
Assignee
STMicroelectronics
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
1357 granted / 1548 resolved
+17.7% vs TC avg
Moderate +7% lift
Without
With
+6.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
48 currently pending
Career history
1598
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
52.7%
+12.7% vs TC avg
§102
18.1%
-21.9% vs TC avg
§112
26.4%
-13.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1548 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This office action is a response to the election of species filed on 3/2/2026. Election/Restrictions Applicant’s election without traverse of Species A, Sub-Species C, claims 1-8, 11 and 14, in the reply filed on 3/2/2026 is acknowledged. Claims 9-13 and 15 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 3/2/2026. Claim Objections Claims 2-10 are objected to because of the following informalities: Re. claim 2: The phrase “The method according to claim 1, comprising” as recited in line 1 appears to be --The method according to claim 1, further comprising--. The phrase “in front of the location of the cavity” as recited in lines 4-5 appears to be --in front of a location of the cavity--. Appropriate correction is required. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-4 and 6-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kajihara et al. (PGPub 2018/0116057 A1). Kajihara et al. teach a process of making an integrated circuit chip carrier, comprising steps of: forming a wall (25, paragraph [0044]) surrounding a cavity (an empty space between the wall, Fig. 3L), wherein the wall comprises one or more first levels (25a, 25b, paragraph [0044]), by: at each first level, forming a layer of a first resin (4, a liquid polyimide resin, paragraphs [0045]-[0046]) around a block (7, Fig. 3N, paragraph [0045]), wherein the block (a peelable resin material, paragraph [0045]) is made of a material different from the first resin; and removing each block to open the cavity as shown in Fig. 3P (paragraph [0048]). Re. claim 2: A base (10, Fig. 1) of the integrated circuit chip carrier having the wall resting thereon; wherein forming the base comprises forming one or more second levels by: at each second level, forming a layer of the first resin extending in front of the location of the cavity (paragraph [0012]). Re. claim 3: The base further comprises forming metal vias (13a, 13b, 13c, Fig. 1, (paragraph [0019]) crossing the base in front of the cavity. Re. claim 4: Each first level comprises growing metal tracks (12a, 12b, 12c, 12d, paragraphs [0015]-[0017]) and metal vias (13a, 13b, 13c, Fig. 1, (paragraph [0019]). Re. claim 6: The one or more first levels are formed on a plate (51, paragraph [0031]) as shown in Figs. 3A and 3H. Re. claim 7: The one or more second levels are formed on the plate before the at least two first levels as shown in Figs. 3A-3L. Re. claim 8: The plate forms the base of the carrier as shown in Figs. 3A and 3H. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kajihara et al. as applied to claim 1 above, and further in view of Yu et al. (PGPub 2020/0305289 A1). Kajihara et al. teach all limitations as set forth above, bur fail to teach the block, which is made of a same material as the metal tracks and metal vias. Yu et al. teach a process of making an integrated circuit chip carrier comprising a process of forming a wall surrounding a cavity, wherein the wall comprises one or more first levels (55, Fig. 5D, paragraph [0072]) and forming a layer of a first resin (53, 54) around a block (59a, 59b, paragraph [0072]) follow by removing each block to open the cavity as shown in Fig. 5F (paragraph [0076]). Wherein the block is made of a metallic material as the metal tracks and metal vias (paragraph [0073]). Therefore, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the claimed invention was made, to a person having ordinary skill in the art to modify a process of fabricating an integrated circuit chip carrier of Kajihara et al. by a metallic material for the block, the metal tracks and metal vias as taught by Yu et al. in order to obtain the invention as specified in claim 1. It is noted that one of ordinary skill in the art could easily select materials from the recited lists to result in the required same compositions. Therefore, since such a modification would have been an obvious design consideration that is within the purview of one having ordinary skill in the art to provide the well-known benefit of obtaining desirable integrated circuit chip carrier. Allowable Subject Matter Claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The Prior Art The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Furutani et al. (PGPub 2019/0200462 A1), Verhaverbeke et al. (US PAT. 11,521,937), and SAKAI et al. (PGPub 2016/0316566 A1) are cited to further show the state of the art with respect to a process of making an integrated circuit chip carrier. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL D KIM whose telephone number is (571)272-4565. The examiner can normally be reached Monday-Friday: 6:00 AM-2:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas Hong can be reached at 571-272-0993. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PAUL D KIM/Primary Examiner, Art Unit 3729
Read full office action

Prosecution Timeline

Jan 09, 2023
Application Filed
Mar 27, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
94%
With Interview (+6.6%)
2y 9m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1548 resolved cases by this examiner. Grant probability derived from career allowance rate.

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