Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in KR on 01/20/2022. It is noted, however, that applicant has not filed a certified copy of the KR 10-20220008499 application as required by 37 CFR 1.55.
The Examiner notes that the applicant has filed a request for USPTO to retrieve Electronic Priority Application(s) on 01/10/2023, but no certified copies are present in the application contents. The Examiner further notes that if retrieval fails, applicants remain responsible for the submission of the certified copy of the foreign application, see uspto.gov/patents/basics/international-protection/electronic-priority-document-exchange-pdx#Retrieval for more information.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/10/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements mentioned above are being considered by the examiner.
Specification
The abstract of the disclosure is objected for failing to conform to 37 C.F.R. 1.72, by exceeding 150 words in length, MPEP 608.01(b). A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The disclosure is objected to because of the following informalities:
The applicant’s specification, [00108] seems to contain a typographical error and should be changed to: “in accordance with an embodiment of
Appropriate correction is required.
Claim Objections
Claims 5 and 19 are objected to because of the following informalities:
Claim 5 appears to contain grammatical errors and should be changed to: “wherein each of the elements constituting the offset vector is a binary number composed of a plurality of bits; further comprising an offset vector”.
Claim 19 appears to contain a typographical error and should be changed to: “partial negative computation values as results of multiplying the partial offset vectors and the negative matrix”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With regards to claim 1, claim 1 recites the limitations of: “split, when negative elements are included in a matrix received”, “a vector conversion circuit configured to: generate, when negative elements are included in a vector received from the host device”. It is unclear if the matrix splitting circuit, and the vector conversion circuit is only operable to perform any functions when a negative element is present within the matrix and vector, and not operable otherwise. Claim 1 further recites: “a vector conversion circuit configured to: generate, when negative elements are included in a vector received from the host device, an offset vector by adding, to elements within the vector, an offset for converting a negative element, which has a largest absolute value among the elements within the vector, into a zero element or a positive element, and apply the offset vector to the row lines of the first sub array and the second sub array”. It is unclear if the offset vector is only applied to the row lines of the first and second sub array when a negative value is present in the vector.
Furthermore, claim 1 recites the limitations of: “apply the offset vector to the row lines of the first sub array and the second sub array”. It is unclear as to what “apply” means for the application of the offset vector to the row lines of the first and second sub arrays. It is unclear if this means that the vector is used as input to the first and second sub arrays with every element being input into each of the row lines of both the first and second sub array, or if it is meant as the vector is used as input to the first and second sub arrays with each row line receiving one element of the vector, it’s unclear if by “apply” it is meant as the vector is applied as a set of voltages, or currents, or as a binary signal, to the row lines.
Furthermore, claim 1 recites the limitations of: “an offset correction circuit configured to: generate an offset correction value by subtracting a result of multiplying the offset and the negative matrix from a result of multiplying the offset and the positive matrix”. It is unclear if the limitation is meant to be understood as the offset correction circuit also multiplies the offset and the negative matrix and multiplies the offset and the positive matrix, or if the offset correction circuit is merely receiving the result of each of those multiplication operations from some other known or unknown circuitries, for use in the operation of subtracting the results of the offset multiplied by the negative matrix from the offset multiplied by the positive matrix.
Furthermore, claim 1 recites the limitations of: “a computation memory comprising one or more sub arrays”. Claim 1 also recites the limitations of “store the positive matrix and the negative matrix in a first sub array and a second sub array within the computation memory respectively”. The limitation of storing the positive matrix and negative matrix in a first sub array and a second sub array respectively means that the computation memory must comprise of at least two or more sub arrays, not one or more. It is unclear how the limitation of the storing the positive matrix and negative matrix in a first sub array and a second sub array respectively coincides with the limitation reciting that the computation memory may comprise of one sub array. For purposes of examination, the Examiner interprets the “a computation memory comprising one or more sub arrays” to mean that the computation memory comprises of two or more sub arrays.
Furthermore, claim 1 recites the limitations of: “generate an offset correction value by subtracting a result of multiplying the offset and the negative matrix from a result of multiplying the offset and the positive matrix”. Multiplying a singular value with a matrix results in a matrix of values. Subtracting a matrix from another matrix results in a new matrix. The limitation of, “an offset correction value” is described as a singular value while the mathematical steps of generating the offset correction value result in a matrix of values. It is unclear if the offset correction value is meant to be understood as a singular value as the claim language suggests, or if it is meant to be understood as a matrix of values as the mathematical steps suggest. For purposes of examination, the Examiner interprets the limitation to be understood as the offset correction value is a matrix of values.
Furthermore, claim 1 recites the limitations of: “subtract the offset correction value from a computation value”. As referenced above, the Examiner interprets the offset correction value to be a matrix of values. This limitation describes the computation value as a singular value, “a computation value”. It is unclear if the computation value is meant to be understood as a singular value or a matrix of values because of the limitation “subtract the offset correction value from a computation value”. Directly subtracting a matrix from a singular value is not a mathematical operation. It is unclear if the limitation is meant to be understood as a value from the matrix of offset correction values is subtracted from a computation value, or if the computation value is meant to be understood as a matrix of values as well (of the same size as the offset correction value matrix). For purposes of examination, the Examiner interprets the computation value to be a matrix of values the same size as the offset correction value matrix (thus allowing a mathematical subtraction operation to take place).
Claims 2-6 inherit the same deficiencies as claim 1 based on dependence.
With regards to claim 2, claim 2 recites the limitations of: “a negative computation value, which is outputted from the second sub array as a result of multiplying the negative matrix and the offset vector”. The “negative computation value” in the claim the negative computation value is recited as a singular value, “a negative computation value”, however, the process of calculating the “negative computation value” would result in a vector of values not a singular value. The claim recites that the negative computation value is a result of multiplying the negative matrix and the offset vector. Multiplying a matrix by a vector would result in a vector not a singular value as suggested by the limitation of the claim. It is unclear if the negative computation value is meant to be understood as a vector of negative computation values as the mathematical steps would suggest, or if the negative computation value is meant to be understood as a singular value as the claim language suggests.
Furthermore, claim 2 recites the limitations of: “a positive computation value, which is outputted from the first sub array as a result of multiplying the positive matrix and the offset vector”. The “positive computation value” in the claim the positive computation value is recited as a singular value, “a positive computation value”, however, the process of calculating the “positive computation value” would result in a vector of values not a singular value. The claim recites that the positive computation value is a result of multiplying the positive matrix and the offset vector. Multiplying a matrix by a vector would result in a vector not a singular value as suggested by the limitation of the claim. It is unclear if the positive computation value is meant to be understood as a vector of positive computation values as the mathematical steps would suggest, or if the positive computation value is meant to be understood as a singular value as the claim language suggests.
Furthermore, claim 2 recites the limitations of: “wherein the computation memory is configured to generate the computation value by subtracting a negative computation value, which is outputted from the second sub array as a result of multiplying the negative matrix and the offset vector, from a positive computation value, which is outputted from the first sub array as a result of multiplying the positive matrix and the offset vector.” The “computation value” in claim 2, as well as in claim 1 which claim 2 is dependent upon, is recited as a singular value, “subtract the offset correction value from a computation value”, as seen in claim 1, however, the process of calculating the “computation value” would not result in a singular value, but instead with a vector of values through the acts of a matrix (positive matrix) multiplied by a vector (offset vector) which would result in a vector, and subtract from that vector the result of another matrix (negative matrix) multiplied by a vector (offset vector) which would result in another vector. It is unclear if the “computation value” is meant to be understood as a vector of values as the mathematical steps would suggest, or if the “computation value” is meant to be understood as a singular value as the claim language suggests. Furthermore, as referenced above in regards to claim 1, the mathematical steps of claim 1 suggest the computation value to be a matrix of values, which the Examiner interpreted the computation value to be. Therefore, it is unclear if the computation value is meant to be understood as a singular value as the claim language suggests, a vector of values as the mathematical steps of claim 2 suggests, or a matrix of values as the mathematical steps of claim 1 suggests.
Furthermore, claim 2 recites the limitations of: “wherein the computation memory is configured to generate the computation value by subtracting a negative computation value, which is outputted from the second sub array as a result of multiplying the negative matrix and the offset vector, from a positive computation value, which is outputted from the first sub array as a result of multiplying the positive matrix and the offset vector”. It is unclear if the limitation is meant to be understood as the computation memory is what multiplies the offset vector and the negative matrix and multiplies the offset vector and the positive matrix, or if the computation memory is merely receiving the result of each of those multiplication operations from some other known or unknown circuitries, for use in the operation of subtracting the results of the offset vector multiplied by the negative matrix from the offset vector multiplied by the positive matrix.
Claims 3-4 inherit the same deficiencies as claim 2 based on dependence.
With regards to claim 3, claim 3 recites the limitations of: “a digital subtractor configured to subtract the digitalized negative computation value from the digitalized positive computation value to generate the computation value”. Claim 3 is dependent on claim 2, wherein claim 2 recites the limitations of: “wherein the computation memory is configured to generate the computation value by subtracting a negative computation value, which is outputted from the second sub array as a result of multiplying the negative matrix and the offset vector, from a positive computation value, which is outputted from the first sub array as a result of multiplying the positive matrix and the offset vector”. Claim 2 recites that the generation of the computation value is done through subtracting the output of the second sub array (the result being a multiplication between the negative matrix and the offset vector), from the output of the first sub array (the result being a multiplication between the positive matrix and the offset vector). Claim 3, however, recites that the generation of the computation value is through subtracting a digitized negative computation value from a digitized positive computation value. Claim 2’s limitation specifies that the negative computation value is output from the second sub array and that this negative computation value is the result of multiplying the negative matrix by the offset matrix. Similarly, claim 2’s limitations specifies that the positive computation value is output from the first sub array and that this positive computation value is the result of multiplying the positive matrix by the offset matrix. Though it may be related, digitizing a value changes that value. Claim 2 recites that the generation of the computation value is through subtracting the negative computation value from the positive computation value. Claim 3 recites that the generation of the computation value is through subtracting a digitized negative computation value (which is related but different than the negative computation value) from a digitized positive computation value (which is related but different than the positive computation value). It is unclear if the limitations of claim 3 are meant to replace the limitations of claim 2, or if the limitations of claim 3 are meant to be calculating a related, but different, computation value, a digitalized computation value.
Furthermore, claim 3 recites the limitations of: “the positive computation value and the negative computation value”. Claim 3 is dependent on claim 2, claim 2 recites the limitations of, “a negative computation value, which is outputted from the second sub array as a result of multiplying the negative matrix and the offset vector”, and “a positive computation value, which is outputted from the first sub array as a result of multiplying the positive matrix and the offset vector”. Claim 3 recites the positive computation value as a singular value, and the negative computation value as a singular value, however, the process of calculating the positive computation value and negative computation value would result in a vector of values, not a singular value for each (as referenced in claim 2 112(b) rejection). It is unclear if the positive computation value, and the negative computation value is meant to be understood as a vector of positive computation values and negative computation values, respectively, as the mathematical steps would suggest, or if the positive computation value, and the negative computation value is meant to be understood as a singular value, respectively, as the claim language suggests. Similarly, claim 3 recites the limitations of: “a digitalized positive computation value and a digitalized negative computation value”. Claim 3 generates the digitalized positive computation value and digitalized negative computation value through converting the positive computation value and negative computation value. It is unclear if the act of digitizing the positive computation value and negative computation value converts each to be a singular value as the claim language implies, “a digitalized positive computation value and a digitalized negative computation value”, or if the digitalized versions of the positive computation value and the negative computation value would actually each be a vector of values as the mathematical steps would suggest the pre-digitalized versions of the positive and negative computations values to be (as referenced above).
With regards to claim 4, claim 4 recites the limitations of: “an analog-digital converter configured to convert an output of the analog subtractor to generate the computation value”. Claim 4 is dependent on claim 2, claim 2 recites the limitations of: “generate the computation value by subtracting a negative computation value, which is outputted from the second sub array as a result of multiplying the negative matrix and the offset vector, from a positive computation value, which is outputted from the first sub array as a result of multiplying the positive matrix and the offset vector”. Claim 4 recites that the computation value is generated through conversion of an output of the analog subtractor (which subtracts the negative computation value from the positive computation value). Claim 2, however, recites that the computation value is generated simply by subtracting the negative computation value from the positive computation value, “generate the computation value by subtracting a negative computation value… from a positive computation value”. It is unclear if the limitations of claim 4 are meant to replace the limitations of claim 2, or if the calculation set forth in claim 4 is meant to be calculating a related (but different) computation value, a digitalized computation value.
Furthermore, claim 4 recites the limitations of: “subtract the negative computation value from the positive computation value”. Claim 4 is dependent on claim 2, claim 2 recites the limitations of, “a negative computation value, which is outputted from the second sub array as a result of multiplying the negative matrix and the offset vector”, and “a positive computation value, which is outputted from the first sub array as a result of multiplying the positive matrix and the offset vector”. Claim 4 recites the positive computation value as a singular value, and the negative computation value as a singular value, however, the process of calculating the positive computation value and negative computation value would result in a vector of values, not a singular value for each (as referenced in the claim 2 112(b) rejection). It is unclear if the positive computation value, and the negative computation value is meant to be understood as a vector of positive computation values and negative computation values, respectively, as the mathematical steps would suggest, or if the positive computation value, and the negative computation value is meant to be understood as a singular value, respectively, as the claim language suggests.
With regards to claim 5, claim 5 recites the limitations of: “the vector conversion circuit is configured to sequentially apply the partial offset vectors to the row lines of the first and second sub arrays”. It is unclear as to what “apply” means for the application of the partial offset vectors to the row lines of the first and second sub arrays. It is unclear if this means that the partial offset vectors are used as input to the first and second sub arrays with every element being input into each of the row lines of both the first and second sub array, or if it is meant as the vector is used as input to the first and second sub arrays with each row line receiving one element of the vector, it’s unclear if by “apply” it is meant as the vector is applied as a set of voltages, or currents, or as a binary signal, to the row lines.
Furthermore, claim 5 recites the limitations of: “further comprising an offset vector splitting circuit configured to: generate a sequential vector including one or more partial offset vectors by splitting the offset vector on a bitwise basis according to place values, and the vector conversion circuit is configured to sequentially apply the partial offset vectors to the row lines of the first and second sub arrays”. Claim 5 recites that the vector conversion circuit is configured to sequentially apply the partial offset vectors to the row lines of the first and second sub arrays. Claim 5 also recites that a sequential vector is generated including one or more partial offset vectors. It is unclear if the conversion circuit sequentially applying the partial offset vectors is done through applying the sequential vector (which is made up of one or more partial offset vectors), or instead through separately sequentially applying all of the separated partial offset vectors.
Claim 6 inherits the same deficiencies as claim 5 based on dependence.
With regards to claim 6, claim 6 recites the limitations of: “a place value sorting circuit configured to sort, according to the place values of the partial offset vectors, partial positive computation values as results of multiplying the partial offset vectors and the positive matrix, sort, according to the place values of the partial offset vectors, partial negative computation values as results of multiplying the partial offset vectors and the negative matrix”. It is unclear if the limitation is meant to be understood as the sorting circuit also multiplies the partial offset vectors and the negative matrix and multiplies the partial offset vectors and the positive matrix, or if the sorting circuit is merely receiving the result of each of those multiplication operations from some other known or unknown circuitries.
Furthermore, claim 6 recites the limitations of: “partial positive computation values as results of multiplying the partial offset vectors and the positive matrix”. It is unclear if the limitation describing the multiplying the partial offset vectors and the positive matrix is meant to be understood as the partial offset vectors are grouped in some fashion into a matrix and multiplied with the positive matrix, or if it is meant to be understood as each partial offset vector is individually multiplied with the positive matrix. For purposes of examination, the Examiner interprets the limitation to mean that each of the partial offset vectors is individually multiplied with the positive matrix (separately).
Furthermore claim 6 recites the limitations of: “derive a positive computation value by adding up all sorted partial positive computation values”, and “partial positive computation values as results of multiplying the partial offset vectors and the positive matrix”. Multiplying a vector with a matrix results in another vector. As interpreted by the Examiner above, the Examiner interprets the limitation of multiplying the partial offset vectors and the positive matrix as meaning that each of the partial offset vectors is individually multiplied with the positive matrix (separately). This would result in a plurality of vectors as the partial positive computation values. In the limitation, “derive a positive computation value by adding up all sorted partial positive computation values”, the positive computation value is described as a singular value, “a positive computation value”. Therefore, it is unclear if the act of adding up all sorted partial positive computation values (which are vectors) is meant to be understood as not only all of the partial positive computation values (vectors) added together creating a summed vector, but also each element within the vector is added in order to result in a singular “positive computation value”, or if the “positive computation value” is meant to be understood as a vector of values. For purposes of examination, the Examiner interprets the positive computation value to be a vector of values.
Furthermore, claim 6 recites the limitations of: “partial negative computation values as results of multiplying the partial offset vectors and the negative matrix”. It is unclear if the limitation describing the multiplying the partial offset vectors and the negative matrix is meant to be understood as the vectors are grouped in some fashion into a matrix and multiplied with the negative matrix, or if it is meant to be understood as each partial offset vector is individually multiplied with the negative matrix. For purposes of examination, the Examiner interprets the limitation to mean that each of the partial offset vectors is individually multiplied with the negative matrix (separately).
Furthermore claim 6 recites the limitations of: “derive a negative computation value by adding up all sorted partial negative computation values”, and “partial negative computation values as results of multiplying the partial offset vectors and the negative matrix”. Multiplying a vector with a matrix results in another vector. As interpreted by the Examiner above, the Examiner interprets the limitation of multiplying the partial offset vectors and the negative matrix as meaning that each of the partial offset vectors is individually multiplied with the negative matrix (separately). This would result in a plurality of vectors as the partial negative computation values. In the limitation, “derive a negative computation value by adding up all sorted partial negative computation values”, the negative computation value is described as a singular value, “a negative computation value”. Therefore, it is unclear if the act of adding up all sorted partial negative computation values (which are vectors) is meant to be understood as not only all of the partial negative computation values (vectors) added together creating a summed vector, but also each element within the vector is added in order to result in a singular “negative computation value”, or if the “negative computation value” is meant to be understood as a vector of values. For purposes of examination, the Examiner interprets the negative computation value to be a vector of values.
With regards to claim 7, claim 7 recites the limitations of: “splitting, by a negative number computation control circuit, when negative elements are included in a matrix received from a host device”, “generating, by the negative number computation control circuit, when negative elements are included in a vector received from the host device”. It is unclear if the negative number computation control circuit is only operable to perform any functions when a negative element is present within the matrix and vector, and not operable otherwise. Claim 7 further recites: “generating, by the negative number computation control circuit, when negative elements are included in a vector received from the host device, an offset vector by adding, to elements within the vector, an offset for converting a negative element, which has a largest absolute value among the elements within the vector, into a zero element or a positive element; applying, by the negative number computation control circuit, the offset vector to the row lines of the first sub array and the second sub array”. It is unclear if the offset vector is only applied to the row lines of the first and second sub array when a negative value is present in the vector.
Furthermore, claim 7 recites the limitations of: “applying, by the negative number computation control circuit, the offset vector to the row lines of the first sub array and the second sub array”. It is unclear as to what “applying” means for the application of the offset vector to the row lines of the first and second sub arrays. It is unclear if this means that the offset vector is used as input to the first and second sub arrays with every element being input into each of the row lines of both the first and second sub array, or if it is meant as the offset vector is used as input to the first and second sub arrays with each row line receiving one element of the offset vector, it’s unclear if by “applying” it is meant as the offset vector is applied as a set of voltages, or currents, or as a binary signal, to the row lines.
Furthermore, claim 7 recites the limitations of: “generating, by the negative number computation control circuit, an offset correction value by subtracting a result of multiplying the offset and the negative matrix from a result of multiplying the offset and the positive matrix”. It is unclear if the limitation is meant to be understood as the negative number computation control circuit also multiplies the offset and the negative matrix and multiplies the offset and the positive matrix, or if the offset correction circuit is merely receiving the result of each of those multiplication operations from some other known or unknown circuitries, for use in the operation of subtracting the results of the offset multiplied by the negative matrix from the offset multiplied by the positive matrix.
Furthermore, claim 7 recites the limitations of: “a computation memory comprising one or more sub arrays”. Claim 7 also recites the limitations of “storing the positive matrix and the negative matrix in a first sub array and a second sub array within the computation memory, respectively”. The limitation of storing the positive matrix and negative matrix in a first sub array and a second sub array respectively means that the computation memory must comprise of at least two or more sub arrays, not one or more. It is unclear how the limitation of the storing the positive matrix and negative matrix in a first sub array and a second sub array respectively coincides with the limitation reciting that the computation memory may comprise of one sub array. For purposes of examination, the Examiner interprets the “a computation memory comprising one or more sub arrays” to mean that the computation memory comprises of two or more sub arrays.
Furthermore, claim 7 recites the limitations of: “generating, by the negative number computation control circuit, an offset correction value by subtracting a result of multiplying the offset and the negative matrix from a result of multiplying the offset and the positive matrix”. Multiplying a singular value with a matrix results in a new matrix of values. Subtracting a matrix from another matrix results in a new matrix. The limitation of, “an offset correction value” is described as a singular value while the mathematical steps of generating the offset correction value result in a matrix of values. It is unclear if the offset correction value is meant to be understood as a singular value as the claim language suggests, or if it is meant to be understood as a matrix of values as the mathematical steps suggest. For purposes of examination, the Examiner interprets the limitation to be understood as the offset correction value is a matrix of values.
Furthermore, claim 7 recites the limitations of: “subtracting, by the negative number computation control circuit, the offset correction value from a computation value”. As referenced above, the Examiner interprets the offset correction value to be a matrix of values. This limitation describes the computation value as a singular value, “a computation value”. It is unclear if the computation value is meant to be understood as a singular value or a matrix of values because of the limitation “subtracting, by the negative number computation control circuit, the offset correction value from a computation value”. Directly subtracting a matrix from a singular value is not a known mathematical operation. It is unclear if the limitation is meant to be understood as a value from the matrix of offset correction values is subtracted from a computation value, or if the computation value is meant to be understood as a matrix of values as well (of the same size as the offset correction value matrix). For purposes of examination, the Examiner interprets the computation value to be a matrix of values the same size as the offset correction value matrix (thus allowing a mathematical subtraction operation to take place).
Claims 8-12 inherit the same deficiencies as claim 7 based on dependence.
With regards to claim 8, claim 8 recites the limitations of: “a negative computation value, which is outputted from the second sub array as a result of multiplying the negative matrix and the offset vector”. The “negative computation value” in the claim is recited as a singular value, “a negative computation value”, however, the process of calculating the “negative computation value” would result in a vector of values not a singular value. The claim recites that the negative computation value is a result of multiplying the negative matrix and the offset vector. Multiplying a matrix by a vector would result in a vector, not a singular value as suggested by the limitation of the claim. It is unclear if the negative computation value is meant to be understood as a vector of negative computation values as the mathematical steps would suggest, or if the negative computation value is meant to be understood as a singular value as the claim language suggests.
Furthermore, claim 8 recites the limitations of: “a positive computation value, which is outputted from the first sub array as a result of multiplying the positive matrix and the offset vector”. The “positive computation value” in the claim is recited as a singular value, “a positive computation value”, however, the process of calculating the “positive computation value” would result in a vector of values not a singular value. The claim recites that the positive computation value is a result of multiplying the positive matrix and the offset vector. Multiplying a matrix by a vector would result in a vector not a singular value as suggested by the limitation of the claim. It is unclear if the positive computation value is meant to be understood as a vector of positive computation values as the mathematical steps would suggest, or if the positive computation value is meant to be understood as a singular value as the claim language suggests.
Furthermore, claim 8 recites the limitations of: “generating the computation value by subtracting a negative computation value, which is outputted from the second sub array as a result of multiplying the negative matrix and the offset vector, from a positive computation value, which is outputted from the first sub array as a result of multiplying the positive matrix and the offset vector.” The “computation value” in claim 8, as well as in claim 7 which claim 8 is dependent upon, is recited as a singular value, “subtracting, by the negative number computation control circuit, the offset correction value from a computation value”, as seen in claim 7, however, the process of calculating the “computation value” would not result in a singular value, but instead with a vector of values through the acts of a matrix (positive matrix) multiplied by a vector (offset vector) which would result in vector, and subtract from that vector the result of another matrix (negative matrix) multiplied by a vector (offset vector) which would result in another vector. It is unclear if the “computation value” is meant to be understood as a vector of values as the mathematical steps would suggest, or if the “computation value” is meant to be understood as a singular value as the claim language suggests. Furthermore, as referenced above in regards to claim 7, the mathematical steps of claim 7 suggest the computation value to be a matrix of values, which the Examiner interpreted the computation value to be. Therefore, it is unclear if the computation value is meant to be understood as a singular value as the claim language suggests, a vector of values as the mathematical steps of claim 8 suggests, or a matrix of values as the mathematical steps of claim 7 suggests.
Furthermore, claim 8 recites the limitations of: “generating the computation value by subtracting a negative computation value, which is outputted from the second sub array as a result of multiplying the negative matrix and the offset vector, from a positive computation value, which is outputted from the first sub array as a result of multiplying the positive matrix and the offset vector”. It is unclear if the act of multiplying the negative matrix and the offset vector, and the act multiplying of the positive matrix and the offset vector is positively recited, it is unclear if the claim is reciting that the claimed method includes the act of multiplying the negative matrix and the offset vector, and the act of multiplying the positive matrix and the offset vector, or if the claimed method is reciting merely the subtraction of the negative computation value from the positive computation value, with the multiplication steps being from some other method.
Claims 9-10 inherit the same deficiencies as claim 8 based on dependence.
With regards to claim 9, claim 9 recites the limitations of: “generating of the computation value includes: converting, by the computation memory, the positive computation value and the negative computation value respectively into a digitalized positive computation value and a digitalized negative computation value; and generating, by the computation memory, the computation value by subtracting the digitalized negative computation value from the digitalized positive computation value”. Claim 9 is dependent on claim 8, wherein claim 8 recites the limitations of: “generating the computation value by subtracting a negative computation value, which is outputted from the second sub array as a result of multiplying the negative matrix and the offset vector, from a positive computation value, which is outputted from the first sub array as a result of multiplying the positive matrix and the offset vector”. Claim 8 recites that the generation of the computation value is done through subtracting the output of the second sub array (the result being a multiplication between the negative matrix and the offset vector), from the output of the first sub array (the result being a multiplication between the positive matrix and the offset vector). Claim 9, however, recites that the generation of the computation value is through subtracting a digitized negative computation value from a digitized positive computation value. Claim 8’s limitation specifies that the negative computation value is output from the second sub array and that this negative computation value is the result of multiplying the negative matrix by the offset matrix. Similarly, claim 8’s limitations specifies that the positive computation value is output from the first sub array and that this positive computation value is the result of multiplying the positive matrix by the offset matrix. Though it may be related, digitizing a value changes that value. Claim 8 recites that the generation of the computation value is through subtracting the negative computation value from the positive computation value. Claim 9 recites that the generation of the computation value is through subtracting a digitized negative computation value (which is related but different than the negative computation value) from a digitized positive computation value (which is related but different than the positive computation value). It is unclear if the limitations of claim 9 are meant to replace the limitations of claim 8, or if the limitations of claim 9 are meant to be calculating a related, but different, computation value, a digitalized computation value.
Furthermore, claim 9 recites the limitations of: “the positive computation value and the negative computation value”. Claim 9 is dependent on claim 8, claim 8 recites the limitations of, “a negative computation value, which is outputted from the second sub array as a result of multiplying the negative matrix and the offset vector”, and “a positive computation value, which is outputted from the first sub array as a result of multiplying the positive matrix and the offset vector”. Claim 9 recites the positive computation value as a singular value, and the negative computation value as a singular value, however, the process of calculating the positive computation value and negative computation value would result in a vector of values, not a singular value for each (as referenced in claim 8 112(b) rejection). It is unclear if the positive computation value, and the negative computation value is meant to be understood as a vector of positive computation values and negative computation values, respectively, as the mathematical steps would suggest, or if the positive computation value, and the negative computation value is meant to be understood as a singular value, respectively, as the claim language suggests. Similarly, claim 9 recites the limitations of: “a digitalized positive computation value and a digitalized negative computation value”. Claim 9 generates the digitalized positive computation value and digitalized negative computation value through converting the positive computation value and negative computation value. It is unclear if the act of digitizing the positive computation value and negative computation value converts each to be a singular value as the claim language implies, “a digitalized positive computation value and a digitalized negative computation value”, or if the digitalized versions of the positive computation value and the negative computation value would actually each be a vector of values as the mathematical steps would suggest the pre-digitalized versions of the positive and negative computations values to be (as referenced above).
With regards to claim 10, claim 10 recites the limitations of: “generating of the computation value includes: subtracting the negative computation value from the positive computation value; and generating the computation value by converting an output of an analog subtractor into a digital value”. Claim 10 is dependent on claim 8, claim 8 recites the limitations of: “generate the computation value by subtracting a negative computation value, which is outputted from the second sub array as a result of multiplying the negative matrix and the offset vector, from a positive computation value, which is outputted from the first sub array as a result of multiplying the positive matrix and the offset vector”. Claim 10 recites that the computation value is generated through conversion of an output of the analog subtractor (which subtracts the negative computation value from the positive computation value). Claim 8, however, recites that the computation value is generated simply by subtracting the negative computation value from the positive computation value, “generating the computation value by subtracting a negative computation value… from a positive computation value”. It is unclear if the limitations of claim 10 are meant to replace the limitations of claim 8, or if the calculation set forth in claim 10 is meant to be calculating a related (but different) computation value, a digitalized computation value.
Furthermore, claim 10 recites the limitations of: “ subtracting the negative computation value from the positive computation value”. Claim 10 is dependent on claim 8, claim 8 recites the limitations of, “a negative computation value, which is outputted from the second sub array as a result of multiplying the negative matrix and the offset vector”, and “a positive computation value, which is outputted from the first sub array as a result of multiplying the positive matrix and the offset vector”. Claim 10 recites the positive computation value as a singular value, and the negative computation value as a singular value, however, the process of calculating the positive computation value and negative computation value would result in a vector of values, not a singular value for each (as referenced in the claim 8 112(b) rejection). It is unclear if the positive computation value, and the negative computation value is meant to be understood as a vector of positive computation values and negative computation values, respectively, as the mathematical steps would suggest, or if the positive computation value, and the negative computation value is meant to be understood as a singular value, respectively, as the claim language suggests.
With regards to claim 11, claim 11 recites the limitations of: “sequentially applying the partial offset vectors to the row lines of the first and second sub arrays”. It is unclear as to what “applying” means for the application of the partial offset vectors to the row lines of the first and second sub arrays. It is unclear if this means that the partial offset vectors are used as input to the first and second sub arrays with every element being input into each of the row lines of both the first and second sub array, or if it is meant as the vector is used as input to the first and second sub arrays with each row line receiving one element of the vector, it’s unclear if by “applying” it is meant as the partial offset vector is applied as a set of voltages, or currents, or as a binary signal, to the row lines.
Furthermore, claim 11 recites the limitations of: “each element constituting the offset vector is a binary number composed of a plurality of bits, wherein the applying the offset vector includes: generating a sequential vector including one or more partial offset vectors by splitting the offset vector on a bitwise basis according to place values; and sequentially applying the partial offset vectors to the row lines of the first and second sub arrays”. Claim 11 recites sequentially applying the partial offset vectors to the row lines of the first and second sub arrays. Claim 11 also recites that a sequential vector is generated including one or more partial offset vectors. It is unclear if sequentially applying the partial offset vectors is done through applying the sequential vector (which is made up of one or more partial offset vectors), or instead through separately sequentially applying all of the separated partial offset vectors.
Claim 12 inherits the same deficiencies as claim 11 based on dependence.
With regards to claim 12, claim 12 recites the limitations of: “sorting, according to the place values of the partial offset vectors, partial positive computation values as results of multiplying the partial offset vectors and the positive matrix; sorting, according to the place values of the partial offset vectors, partial negative computation values as results of multiplying the partial offset vectors and the negative matrix”. It is unclear if the act of multiplying the negative matrix and the partial offset vectors, and the act multiplying of the positive matrix and the partial offset vectors is positively recited, it is unclear if the claim is reciting that the claimed method includes the act of multiplying the negative matrix and the partial offset vectors, and the act of multiplying the positive matrix and the partial offset vectors, or if the claimed method is reciting merely the sorting of the partial positive computation values, and partial negative computation values, with the multiplication steps being from some other method.
Furthermore, claim 12 recites the limitations of: “partial positive computation values as results of multiplying the partial offset vectors and the positive matrix”. It is unclear if the limitation describing the multiplying the partial offset vectors and the positive matrix is meant to be understood as the partial offset vectors are grouped in some fashion into a matrix and multiplied with the positive matrix, or if it is meant to be understood as each partial offset vector is individually multiplied with the positive matrix. For purposes of examination, the Examiner interprets the limitation to mean that each of the partial offset vectors is individually multiplied with the positive matrix (separately).
Furthermore claim 12 recites the limitations of: “deriving a positive computation value by adding all the sorted partial positive computation values”, and “partial positive computation values as results of multiplying the partial offset vectors and the positive matrix”. Multiplying a vector with a matrix results in another vector. As interpreted by the Examiner above, the Examiner interprets the limitation of multiplying the partial offset vectors and the positive matrix as meaning that each of the partial offset vectors is individually multiplied with the positive matrix (separately). This would result in a plurality of vectors as the partial positive computation values. In the limitation, “deriving a positive computation value by adding all the sorted partial positive computation values”, the positive computation value is described as a singular value, “a positive computation value”. Therefore, it is unclear if the act of adding up all sorted partial positive computation values (which are vectors) is meant to be understood as not only all of the partial positive computation values (vectors) added together creating a summed vector, but also each element within the vector is added in order to result in a singular “positive computation value”, or if the “positive computation value” is meant to be understood as a vector of values. For purposes of examination, the Examiner interprets the positive computation value to be a vector of values.
Furthermore, claim 12 recites the limitations of: “partial negative computation values as results of multiplying the partial offset vectors and the negative matrix”. It is unclear if the limitation describing the multiplying the partial offset vectors and the negative matrix is meant to be understood as the vectors are grouped in some fashion into a matrix and multiplied with the negative matrix, or if it is meant to be understood as each partial offset vector is individually multiplied with the negative matrix. For purposes of examination, the Examiner interprets the limitation to mean that each of the partial offset vectors is individually multiplied with the negative matrix (separately).
Furthermore, claim 12 recites the limitations of: “deriving a negative computation value by adding all the sorted partial negative computation values”, and “partial negative computation values as results of multiplying the partial offset vectors and the negative matrix”. Multiplying a vector with a matrix results in another vector. As interpreted by the Examiner above, the Examiner interprets the limitation of multiplying the partial offset vectors and the negative matrix as meaning that each of the partial offset vectors is individually multiplied with the negative matrix (separately). This would result in a plurality of vectors as the partial negative computation values. In the limitation, “deriving a negative computation value by adding all the sorted partial negative computation values”, the negative computation value is described as a singular value, “a negative computation value”. Therefore, it is unclear if the act of adding up all sorted partial negative computation values (which are vectors) is meant to be understood as not only all of the partial negative computation values (vectors) added together creating a summed vector, but also each element within the vector is added in order to result in a singular “negative computation value”, or if the “negative computation value” is meant to be understood as a vector of values. For purposes of examination, the Examiner interprets the negative computation value to be a vector of values.
With regards to claim 13, claim 13 recites the limitations of: “split, when negative elements are included in a matrix received”, “generate, when negative elements are included in a vector received from the host device”. It is unclear if the data processing system is only operable to perform any functions when a negative element is present within the matrix and vector, and not operable otherwise.
Furthermore, claim 13 recites the limitations of: “a negative number computation control circuit configured to split, when negative elements are included in a matrix received from the host device, the matrix into a positive matrix and a negative matrix, generate, when negative elements are included in a vector received from the host device, an offset vector by adding an offset to the vector, and correct a computation value, outputted as a result of multiplying each of the positive and negative matrices with the offset vector, from the computation memory according to an offset correction value generated on the basis of the offset.” It is unclear if the negative number computation control circuit is the circuitry that is configured to split the matrix, generate an offset vector, and correct a computation value, or if the negative number computation control circuit is only meant to split the matrix. For purposes of examination, the Examiner interprets the limitations as: “a negative number computation control circuit configured to: split, when negative elements are included in a matrix received from the host device, the matrix into a positive matrix and a negative matrix, generate, when negative elements are included in a vector received from the host device, an offset vector by adding an offset to the vector, and correct a computation value, outputted as a result of multiplying each of the positive and negative matrices with the offset vector, from the computation memory according to an offset correction value generated on the basis of the offset” such that the negative number computation control circuit is configured to split the matrix, generate an offset vector, and correct a computation value. It remains unclear, however, if the computation value from the limitation, “correct a computation value, outputted as a result of multiplying each of the positive and negative matrices with the offset vector, from the computation memory according to an offset correction value generated on the basis of the offset” is meant to be calculated as part of the functions of the negative number computation control circuit (as referenced above), with the computation memory being a part of the negative number computation control circuit, or the negative number computation control circuit as part of the computation memory, or if the negative number computation control circuit is a separate circuit than the computation memory, with the limitation meaning that the negative number computation control circuit merely corrects the computation value which is received from the computation memory. For purposes of examination the Examiner interprets the limitations regarding the computation control circuit, and the limitations regarding the negative number computation control circuit as: “and comprising: to: split, when negative elements are included in a matrix received from the host device, the matrix into a positive matrix and a negative matrix, generate, when negative elements are included in a vector received from the host device, an offset vector by adding an offset to the vector, and correct a computation[[.]]; and a computation memory including one or more sub arrays each including a plurality of memory cells coupled between a plurality of row lines and a plurality of column lines[[;]], wherein the computation memory outputs a computation value as a result of multiplying each of the positive and negative matrices with the offset vector”.
Furthermore, claim 13 recites the limitations of: “a computation value, outputted as a result of multiplying each of the positive and negative matrices with the offset vector”. Claim 13 recites the computation value as a singular value, “a computation value”, however, the mathematical steps that the claim recites for generating the computation value would result in two vectors. Multiplying a vector with a matrix results in a matrix, and the claim recites “multiplying each of the positive and negative matrices with the offset vector”. It is unclear if the computation value is meant to be understood as a singular value as the claim language suggests, or if it is meant to be understood as a plurality of vectors of values, or if it is meant to be understood as a single vector of values through some combination of the multiplication of the offset vector with the positive and negative matrices. For purposes of examination, the Examiner interprets the computation value to be a vector of values as a result of a combination of the multiplication results from the offset vector with the positive and negative matrices.
Claims 14-19 inherit the same deficiencies as claim 13 based on dependence.
With regards to claim 15, claim 15 recites the limitations of: “wherein the negative number computation control circuit is further configured to generate the offset correction value by subtracting a result of multiplying the offset and the negative matrix from a result of multiplying the offset and the positive matrix”. It is unclear if the limitation is meant to be positively reciting the multiplication of the offset with the positive matrix and the offset with the negative matrix. The limitations regarding the multiplications are recited as merely results of the multiplication having happened, rather than positively reciting that the negative number computation control circuit, or some other known or unknown circuitry is configured to multiply the offset with the positive and negative matrices.
With regards to claim 16, claim 16 recites the limitations of: “wherein the computation memory is configured to generate the computation value by subtracting a negative computation value, which is outputted from a second sub array as a result of multiplying the negative matrix and the offset vector, from a positive computation value, which is outputted from a first sub array as a result of multiplying the positive matrix and the offset vector”. It is unclear if the limitation is meant to be positively reciting the multiplication of the offset vector with the positive matrix and the offset vector with the negative matrix. The limitations regarding the multiplications are recited as merely results of the multiplication having happened, rather than positively reciting that the computation memory, or some other known or unknown circuitry is configured to multiply the offset with the positive and negative matrices. Furthermore, the limitations regarding the multiplication of the offset vector with the positive and negative matrices describe that the results of the multiplication is output from the first and second sub arrays, respectively. It is unclear if the first and second sub array from which these results are output, are a part of the computation memory, as part of the “one or more sub arrays” recited in claim 13, or if they are sub arrays from another circuit, with results of the multiplication operations merely received by the computation memory. For purposes of examination, the Examiner interprets the limitations to mean that the computation memory comprises a first and second sub array, each sub array configured to multiply their respective matrix (positive/negative), with the result of the multiplication of the negative matrix with the offset vector being the negative computation value, and the result of the multiplication of the positive matrix with the offset vector being the positive computation value, and the computation memory further configured to generate the computation value by subtracting the negative computation value from the positive computation value.
Furthermore, claim 16 recites the limitations of: “wherein the computation memory is configured to generate the computation value by subtracting a negative computation value, which is outputted from a second sub array as a result of multiplying the negative matrix and the offset vector, from a positive computation value, which is outputted from a first sub array as a result of multiplying the positive matrix and the offset vector”. The claim describes the negative computation value as a singular value, “a negative computation value”, as well as the positive computation value as a singular value, “a positive computation value”. The mathematical steps, however, of computing the positive and negative computation values would result in vectors, due to multiplication of a matrix with a vector, not singular values. Furthermore, as referenced above in claim 13 which claim 16 is dependent upon, the Examiner interprets the computation value as a vector of values, and subtracting a singular value from another singular value would not result in a vector of values, but a vector of values subtracted from another vector of values would result in another vector of values. Therefore, for the purposes of examination, as interpreted by the Examiner interprets the negative and positive computation values as each being respective vectors of values.
With regards to claim 17, claim 17 recites the limitations of: “the negative number computation control circuit is further configured to subtract the offset correction value from the computation value”. As referenced above with claim 13, which claim 17 is dependent upon, the Examiner interprets the computation value as a vector of values. It is unclear if the offset correction value is meant to be understood as a singular value, or a vector of values. For purposes of examination, the Examiner interprets the offset correction value to be a vector of values.
With regards to claim 18, claim 18 recites the limitations of: “apply the partial offset vectors”. There is insufficient antecedent basis for this limitation in the claim.
Furthermore, claim 18 recites the limitations of: “the row lines of sub arrays in which the positive matrix and the negative matrix are respectively stored”. There is insufficient antecedent basis for the positive matrix and the negative matrix stored on row lines of sub arrays.
Furthermore, claim 18 recites the limitations of: “sequentially apply the partial offset vectors to the row lines of sub arrays in which the positive matrix and the negative matrix are respectively stored”. It is unclear if the limitation is meant to be understood as there is a plurality of sub arrays which store the positive matrix and the negative matrix, with either, each sub array of the plurality storing the entirety of the positive matrix, and another plurality of sub arrays storing the entirety of the negative matrix, or each sub array of the plurality of sub arrays storing portions of the positive matrix and each sub array of another plurality of sub arrays storing portions of the negative matrix, or if it is meant to be understood as a single sub array is storing the positive matrix, and another single sub array is storing the negative matrix. For purposes of examination, the Examiner interprets the limitation to mean that there is a first sub array storing the positive matrix, and a second sub array storing the negative matrix.
Furthermore, claim 18 recites the limitations of: “sequentially apply the partial offset vectors to the row lines of sub arrays”. It is unclear as to what “apply” means for the application of the partial offset vectors to the row lines of the sub arrays. It is unclear if this means that the partial offset vectors are used as input to the sub arrays with every element being input into each of the row lines of both the sub arrays, or if it is meant as the vector is used as input to the first and second sub arrays with each row line receiving one element of the vector, it’s unclear if by “apply” it is meant as the vector is applied as a set of voltages, or currents, or as a binary signal, to the row lines.
Furthermore, claim 18 recites the limitations of: “the negative number computation control circuit is further configured to: generate a sequential vector including one or more offset vectors by splitting the offset vector on a bitwise basis according to place values, and sequentially apply the partial offset vectors to the row lines of sub arrays in which the positive matrix and the negative matrix are respectively stored”. Claim 18 describes that the negative number computation control circuit is configured to sequentially apply the partial offset vectors to the row lines of the sub arrays. Claim 18 also recites that a sequential vector is generated including one or more partial offset vectors. It is unclear if the negative number computation control circuit sequentially applying the partial offset vectors is done through applying the sequential vector (which is made up of one or more partial offset vectors), or instead through separately sequentially applying all of the separated partial offset vectors.
Claim 19 inherits the same deficiencies as claim 18 based on dependence.
With regards to claim 19, claim 19 recites the limitations of: “the computation memory is further configured to: sort, according to the place values of the partial offset vectors, partial positive computation values as results of multiplying the partial offset vectors and the positive matrix, sort, according to the place values of the partial offset vectors, partial negative computation values as results of multiplying the part offset vectors and the negative matrix, and subtract the sorted partial negative computation values from the sorted partial positive computation values”. It is unclear if the limitation is meant to be understood as the computation memory also multiplies the partial offset vectors and the negative matrix and multiplies the partial offset vectors and the positive matrix, or if the computation memory is merely receiving the result of each of those multiplication operations from some other known or unknown circuitries.
Furthermore, claim 19 recites the limitations of: “partial positive computation values as results of multiplying the partial offset vectors and the positive matrix”. It is unclear if the limitation describing the multiplying the partial offset vectors and the positive matrix is meant to be understood as the partial offset vectors are grouped in some fashion into a matrix and multiplied with the positive matrix, or if it is meant to be understood as each partial offset vector is individually multiplied with the positive matrix. For purposes of examination, the Examiner interprets the limitation to mean that each of the partial offset vectors is individually multiplied with the positive matrix (separately).
Furthermore, claim 6 recites the limitations of: “partial negative computation values as results of multiplying the part offset vectors and the negative matrix”. It is unclear if the limitation describing the multiplying the partial offset vectors and the negative matrix is meant to be understood as the vectors are grouped in some fashion into a matrix and multiplied with the negative matrix, or if it is meant to be understood as each partial offset vector is individually multiplied with the negative matrix. For purposes of examination, the Examiner interprets the limitation to mean that each of the partial offset vectors is individually multiplied with the negative matrix (separately).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 13, 14, and 16-17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hua et al. (Patent application publication 2022/0236909 A1), hereinafter, “Hua”.
With regards to claim 13, Hua teaches:
A computing system (Fig. 1);
comprising: a host device; (Fig. 1 Item 110 (Host));
a data processing system configured to process a computation of an application according to a request of the host device, (Fit. 1 Item 120 (Neural network circuit)(as a data processing system), 110 (Host), 130 (PCIe bus); [0056] regarding data sent from the host (110) input into the neural network circuit (120));
and comprising a computation memory including one or more sub arrays each including a plurality of memory cells coupled between a plurality of row lines and a plurality of column lines; (Fig. 1 item 120 (Neural network circuit), 1201 (neural network chip); [0062] regarding the neural network chips (1201) as memory devices; Fig. 3 regarding the crossbar array structure within a neural network chip);
and a negative number computation control circuit configured to split, when negative elements are included in a matrix received from the host device, the matrix into a positive matrix and a negative matrix, (Fig. 3 regarding the crossbar array structure within a neural network chip; [0067] regarding splitting an input matrix into a positive matrix and a negative matrix; [0156]-[0159] regarding the neural network computing chip, matrix 1301 containing negative numbers, matrix 1302 being the positive matrix, and 1303 being the negative matrix);
generate, when negative elements are included in a vector received from the host device, an offset vector by adding an offset to the vector, (Fig. 14 and [0155] - [0161] regarding vector [-4, 1, 2] containing a negative number, adding translation data (4) to the vector elements to change it to vector [0, 5, 6] (as an offset vector); [0155] regarding a value (as an offset) added to an input data vector with a negative number to generate a new vector (as an offset vector));
and correct computation values, outputted as a result of multiplying each of the positive and negative matrices with the offset vector, from the computation memory according to an offset correction value generated on the basis of the offset. (Fig. 14 regarding multiplying the positive matrix (1302) and the negative matrix (1303) by the offset vector [0, 5, 6], the vector [-16, 15, -4] as a computation value, and adding (correcting) to the computation value the vector [9, -7, 10]; Fig 8 and [0093] regarding vector [9, -7, 10] being calculated on the basis of the offset (translation data 4)).
With regards to claim 14, Hua teaches the computing system according to claim 13, as referenced above.
Hua further teaches:
wherein the sub arrays comprise: a first sub array configured to store the positive matrix therein and receive the offset vector through the row lines thereof; ([0067] regarding one crossbar array (as a sub array) used to map the positive matrix and another crossbar array (as a sub array) used to map the second matrix; Fig. 3 regarding input data (offset vector) applied to the row lines of the crossbar array; [0155] regarding vector (as the offset vector) [0, 5, 6] being input data);
and a second sub array configured to store the negative matrix therein and receive the offset vector through the row lines thereof. ([0067] regarding one crossbar array (as a sub array) used to map the positive matrix and another crossbar array (as a sub array) used to map the second matrix; Fig. 3 regarding input data (offset vector) applied to the row lines of the crossbar array; [0155] regarding vector (as the offset vector) [0, 5, 6] being input data).
With regards to claim 16, Hua teaches the computing system according to claim 13, as referenced above.
Hua further teaches:
wherein the computation memory is configured to generate the computation value by subtracting a negative computation value, which is outputted from a second sub array as a result of multiplying the negative matrix and the offset vector, from a positive computation value, which is outputted from a first sub array as a result of multiplying the positive matrix and the offset vector. (Fig. 14 regarding multiplying the positive matrix (1302) and the negative matrix (1303) by the offset vector [0, 5, 6], the vector [-16, 15, -4] as a computation value).
With regards to claim 17, Hua teaches the computing system according to claim 13, as referenced above.
Hua further teaches:
wherein the negative number computation control circuit is further configured to subtract the offset correction value from the computation value. (Fig. 14 regarding multiplying the positive matrix (1302) and the negative matrix (1303) by the offset vector [0, 5, 6], the vector [-16, 15, -4] as a computation value, and adding (correcting) to the computation value the vector [9, -7, 10]; Fig 8 and [0093] regarding vector [9, -7, 10] being calculated on the basis of the offset (translation data 4)).
Indication of Allowable Subject Matter
Claims 1-12 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Claims 15, and 18-19 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter regarding claims 1-6:
With regards to claim 1, the applicant claims a data processing system comprising:
a computation memory comprising one or more sub arrays each including a plurality of memory cells coupled between a plurality of row lines and a plurality of column lines; a matrix splitting circuit configured to: split, when negative elements are included in a matrix received from a host device, the matrix into a positive matrix composed of positive elements from the matrix and a negative matrix composed of absolute values of the negative elements from the matrix, and store the positive matrix and the negative matrix in a first sub array and a second sub array within the computation memory, respectively; a vector conversion circuit configured to: generate, when negative elements are included in a vector received from the host device, an offset vector by adding, to elements within the vector, an offset for converting a negative element, which has a largest absolute value among the elements within the vector, into a zero element or a positive element, and apply the offset vector to the row lines of the first sub array and the second sub array; and an offset correction circuit configured to: generate an offset correction value by subtracting a result of multiplying the offset and the negative matrix from a result of multiplying the offset and the positive matrix, and subtract the offset correction value from a computation value outputted from the first sub array and the second sub array.
The primary reason for indication of allowable subject matter is the above italicized claim limitations in combination with the remaining claim limitations including intervening claims.
The following is a statement of reasons for the indication of allowable subject matter regarding claims 7-12:
With regards to claim 7, the applicant claims an operating method of a data processing system, comprising:
providing a computation memory comprising one or more sub arrays each including a plurality of memory cells coupled between a plurality of row lines and a plurality of column lines; splitting, by a negative number computation control circuit, when negative elements are included in a matrix received from a host device, the matrix into a positive matrix composed of positive elements from the matrix and a negative matrix composed of absolute values of the negative elements from the matrix; storing the positive matrix and the negative matrix in a first sub array and a second sub array within the computation memory, respectively; generating, by the negative number computation control circuit, when negative elements are included in a vector received from the host device, an offset vector by adding, to elements within the vector, an offset for converting a negative element, which has a largest absolute value among the elements within the vector, into a zero element or a positive element; applying, by the negative number computation control circuit, the offset vector to the row lines of the first sub array and the second sub array; generating, by the negative number computation control circuit, an offset correction value by subtracting a result of multiplying the offset and the negative matrix from a result of multiplying the offset and the positive matrix; and subtracting, by the negative number computation control circuit, the offset correction value from a computation value outputted from the first and second sub arrays.
The primary reason for indication of allowable subject matter is the above italicized claim limitations in combination with the remaining claim limitations including intervening claims.
The following is a statement of reasons for the indication of allowable subject matter regarding claim 15:
With regards to claim 13, the applicant claims a computing system comprising:
a host device; a data processing system configured to process a computation of an application according to a request of the host device, and comprising a computation memory including one or more sub arrays each including a plurality of memory cells coupled between a plurality of row lines and a plurality of column lines; and a negative number computation control circuit configured to split, when negative elements are included in a matrix received from the host device, the matrix into a positive matrix and a negative matrix, generate, when negative elements are included in a vector received from the host device, an offset vector by adding an offset to the vector, and correct a computation value, outputted as a result of multiplying each of the positive and negative matrices with the offset vector, from the computation memory according to an offset correction value generated on the basis of the offset.
Furthermore, wherein the computing system according to claim 15 comprises:
The computing system according to claim 13, wherein the negative number computation control circuit is further configured to generate the offset correction value by subtracting a result of multiplying the offset and the negative matrix from a result of multiplying the offset and the positive matrix.
The primary reason for indication of allowable subject matter is the above italicized claim limitations in combination with the remaining claim limitations including intervening claims.
The following is a statement of reasons for the indication of allowable subject matter regarding claims 18-19:
With regards to claim 13, the applicant claims a computing system comprising:
a host device; a data processing system configured to process a computation of an application according to a request of the host device, and comprising a computation memory including one or more sub arrays each including a plurality of memory cells coupled between a plurality of row lines and a plurality of column lines; and a negative number computation control circuit configured to split, when negative elements are included in a matrix received from the host device, the matrix into a positive matrix and a negative matrix, generate, when negative elements are included in a vector received from the host device, an offset vector by adding an offset to the vector, and correct a computation value, outputted as a result of multiplying each of the positive and negative matrices with the offset vector, from the computation memory according to an offset correction value generated on the basis of the offset.
Furthermore, wherein the computing system according to claim 18 comprises:
The computing system according to claim 13, wherein each element constituting the offset vector is a binary number composed of a plurality of bits, wherein the negative number computation control circuit is further configured to: generate a sequential vector including one or more offset vectors by splitting the offset vector on a bitwise basis according to place values, and sequentially apply the partial offset vectors to the row lines of sub arrays in which the positive matrix and the negative matrix are respectively stored.
The primary reason for indication of allowable subject matter is the above italicized claim limitations in combination with the remaining claim limitations including intervening claims.
Luo, (U.S. Patent Application Publication 2021/0149984 A1), hereinafter, “Luo”, discloses matrix operations within a memory array, separating an input matrix into a positive and negative matrix (Fig. 4 regarding the matrix split into positive and negative matrices; Fig. 5A, 5B). Luo further discloses multiplying the positive and negative matrices by a same vector of values (Fig. 4 regarding vector [a0, a1] multiplied with each the positive and negative matrices). However, Luo fails to teach or suggest the italicized claim limitations in combination with the remaining claim limitations as referenced above. Luo fails to teach or suggest creating an offset vector by applying an offset value to a vector with negative values, and then multiplying each, the positive and negative matrices with the same offset value used in calculating the offset vector, and then subtracting the result of the offset multiplied by the negative matrix from the result of the offset multiplied by the positive matrix to create an offset correction value, nor does Luo teach or suggest taking this offset correction value and subtract it from a computation value output from a first and second sub array.
Muralimanohar et al. (U.S. Patent Application Publication 2018/0004708 A1), hereinafter, “Muralimanohar”, discloses separating a matrix into a positive matrix and a negative matrix, and storing them in different crossbar arrays (Fig. 1 regarding 110 (input), 122 (first memory crossbar array), 124 (second memory crossbar array); [0016] regarding segregating an input vector into positive and negative vectors, and storing them on different crossbar arrays; Fig. 3 regarding splitting input matrix 320 into a positive matrix (322) and a negative matrix (324)). Muralimanohar further discloses, multiplying both the positive and negative matrices with a vector that has been modified to remove negative values (Fig. 3 regarding the vector 310 separated into positive and negative matrices; [0046] regarding the positive vector (312) multiplied with both the positive and negative matrices). However, Muralimanohar fails to teach or suggest the italicized claim limitations in combination with the remaining claim limitations as referenced above. Muralimanohar fails to teach or suggest creating an offset vector by applying an offset value to a vector with negative values, and then multiplying each, the positive and negative matrices with the same offset value used in calculating the offset vector, and then subtracting the result of the offset multiplied by the negative matrix from the result of the offset multiplied by the positive matrix to create an offset correction value, nor does Muralimanohar teach or suggest taking this offset correction value and subtract it from a computation value output from a first and second sub array.
Hua discloses a computation memory comprising one or more sub arrays each including a plurality of memory cells coupled between a plurality of row lines and a plurality of column lines (Fig. 1 item 120 (Neural network circuit), 1201 (neural network chip); [0062] regarding the neural network chips (1201) as memory devices; Fig. 3 regarding the crossbar array structure within a neural network chip). Hua further discloses an input matrix containing negative values split into a positive matrix and a negative matrix (Fig. 3 regarding the crossbar array structure within a neural network chip; [0067] regarding splitting an input matrix into a positive matrix and a negative matrix; [0156]-[0159] regarding the neural network computing chip, matrix 1301 containing negative numbers, matrix 1302 being the positive matrix, and 1303 being the negative matrix). Hua further discloses modifying an input vector which contains negative values into an offset vector by adding an offset value to the elements of the vector (Fig. 14 and [0155] - [0161] regarding vector [-4, 1, 2] containing a negative number, adding translation data (4) to the vector elements to change it to vector [0, 5, 6] (as an offset vector); [0155] regarding a value (as an offset) added to an input data vector with a negative number to generate a new vector (as an offset vector)). Hua further discloses multiplying the positive and negative matrices each with the offset vector, subtracting the results, and correcting the result of the subtraction using a vector based on the offset value used (Fig. 14 regarding multiplying the positive matrix (1302) and the negative matrix (1303) by the offset vector [0, 5, 6], the vector [-16, 15, -4] as a computation value, and adding (correcting) to the computation value the vector [9, -7, 10]; Fig 8 and [0093] regarding vector [9, -7, 10] being calculated on the basis of the offset (translation data 4)). However, Hua fails to teach or suggest the italicized claim limitations in combination with the remaining claim limitations as referenced above. Hua fails to teach or suggest creating an offset vector by applying an offset value to a vector with negative values, and then multiplying each the positive and negative matrices with the same offset value used in calculating the offset vector, and then subtracting the result of the offset multiplied by the negative matrix from the result of the offset multiplied by the positive matrix to create an offset correction value, nor does Hua teach or suggest taking this offset correction value and subtract it from a computation value output from a first and second sub array. Furthermore, Hua fails to teach or suggest separating the offset vector in a bitwise fashion according to place values, and sorting the results.
Conclusion
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/J.A.K./ Examiner, Art Unit 2182 /EMILY E LAROCQUE/ Primary Examiner, Art Unit 2182
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