The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are presented for examination
Allowable Subject Matter
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
((a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7, 10, and 12-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Persson (US Patent Application 20150089495).
As per claim 1, Persson teaches a machine-readable storage medium containing program code [processor-based program execution: 0149] that when processed by one or more processing cores [CPU core: 0250] causes a method to be performed, comprising:
determining from program code that is scheduled for execution [accelerator task scheduler: 0042] and/or is being scheduled for execution that an accelerator is expected to be invoked by the program code, the program code to implement one or more application software processes [0042, 0067, as pointed out the accelerator task scheduler is used to determine which task is to be executed by reading value from the register. Where each task as an expected identifier where expected identifier is used for the task that is expected to execute].
in response to the determining, causing the accelerator to wake up from a sleep state before the accelerator is first invoked from the program code's execution [0081, 0201, where the accelerator is configured to wake up and process the tasks based on the scheduling result].
As per claim 7, Persson teaches an apparatus [20, fig. 2], comprising:
a plurality of processing cores [CPU 101 with cores, fig. 9] and an accelerator [12, fig. 9].
a virtual machine monitor [10, fig .1] executing on the plurality of processing cores [0125, hypervisor executed program by the processor].
a virtual machine [4, fig. 1] executing on the virtual machine monitor [0003, figure 1 shows virtual machines 4 and 5 controlled by hypervisor 10].
an operating system [6, fig. 1] executing on the virtual machine, the operating system to support the concurrent execution of multiple software processes [0003, figure 1 shows operating system 6 and 7 running in the virtual machines].
an accelerator device driver [operating system driver for the accelerator: 0003] and/or hardware power manager to wake the accelerator from a sleep state, before the accelerator is invoked from the execution of program code for the software processes on one or more of the processing cores, in response to a determination made before the execution of the program code that the program code is expected to invoke the accelerator [0081, 0125 as pointed out the accelerator generate a wake when data is available from the interface. Thus, only when data is available the wake even is generated].
As per claim 2, Persson teaches the method is performed by any one of: a device driver of the accelerator [0002, 0003, as pointed out, operating system driver for the accelerator will then schedule the task].
As per claim 3, Person teaches the method is performed by the device driver of the accelerator and the method further comprises the device driver polling an instance of an operating system [0004, register slot initiates task for the accelerator from the operating system which is viewed as an instance for specific task].
As per claim 4, Person teaches the determining is performed within an operating system instance and the causing includes the operating system instance sending notification of the determining to a device driver of the accelerator and/or register space of the accelerator [0219, notification of the hypervisor virtual machine to the accelerator].
As per claim 5, Person teaches wherein the determining is based on an amount of the program code [0266, type of workload or job including small jobs or workloads or light workloads or jobs or heavy workload or jobs].
As per claim 6, Person teaches the determining is based on the program code being characterized as dependent on acceleration [0266, based on the demand reading from the register which makes the determination].
As per claim 10, Person teaches the accelerator is an encryption/decryption accelerator [0034, 0155, acceleratory is used to perform cryptographic operation such as encryption].
As per claim 12, Person teaches the determination is made by the accelerator device driver and/or hardware power manager [0002, operating system driver for the accelerator].
As per claim 13, Person teaches the accelerator device driver polls the operating system for a state of the operating system's scheduler [0004, register slot initiates task for the accelerator from the operating system which is viewed as an instance for specific task].
Claims 14-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Azizi (US Patent Application 20200359265).
As per claim 14, Azizi teaches a machine-readable storage medium [non-transitory computer readable medium: 0154] containing program code that when processed by one or more processing cores [multi-core processor: 0103] causes a method to be performed, comprising [0110, program to implement methods shown of figures 5, and 10-12]:
determining an expected arrival of a burst of ingress packets from collected networking statistics [0073, as pointed out the network traffic controller is used to receive prediction information from prediction controller to determine incoming packet or traffic as well as when to except a packet].
in response to the determining, causing an accelerator to wake up from a sleep state before the accelerator is invoked to process the ingress packets [0072, 0085, where the information is used to determine when to wakeup the GPU. For example, output of the prediction controller 306, the example latency value generator 310 is also generating times at which to interrupt (e.g., wake) the memory 204 and/or processor 206 from a C-state].
As per claim 15, Azizi teaches the accelerator performs decryption on the ingress packets [0104, perform frame encryption and decryption].
As pe claim 16, Azizi teaches a Network Data Analytics Functionality function determined from previously collected networking statistics a networking state that precedes a burst of ingress packets [0091, 0111, as pointed out, the network packet controller 302 analyzes the header of the data packets to determine matching tuples between the data packets. Analyzing previous data learning from the prediction model].
As per clam 17, Azizi teaches the collected networking statistics include statistics from a networking interface controller [0020, 0039, network traffic information related to specific workload].
As per claim 17, Azizi teaches the collected networking statistics include statistics from a networking interface controller [0196, network interface that enable the communication with the computing device and other devices].
As per claim 18, Azizi teaches the method is performed by a wireless base station [0016, wireless based station such as access point].
As per claim 19, Azizi teaches the determining is made from statistics performed on a network slice [0148, packet determine the state of the modem and network traffic].
As per claim 20, Azizi teaches determining an increase or decrease in expected workload of the accelerator from subsequently collected networking statistics and causing the accelerator's performance state to be correspondingly lowered or raised in response [0020-0021, as pointed out depending of the workload which is based on network traffic as well as packet information].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Persson (US Patent Application 20150089495) in the view of Azizi (US Patent Application 20200359265).
As per claim 9, Person does not teach the accelerator is an artificial intelligence accelerator.
However, Azizi teaches the accelerator is an artificial intelligence accelerator [0024-0027, where the GPU or processor can perform machine learning operation].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method of Person to use the design of Azizi in order to program the accelerator to perform machine learning operation or simply execute modules that perform machine learning operations in conjunction.
As per claim 11, Person does not teach the program code is to send a plurality of egress packets.
However, Azizi teaches the program code is to send a plurality of egress packets [0085, interarrival packet management where packet are waiting with specific time period].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method of Person to use the design of Azizi to program the packets so they can wait to be processed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Samson (US 10178619) teaches advanced graphics power state management.
Bachmutsky (US 20210026651) teaches wake-up and scheduling for functions with context hints.
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/VOLVICK DEROSE/Primary Examiner, Art Unit 2176