DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The present application is being examined under the claims filed 10/07/2025. Claims 1, 8, 10, 14, 16, 17. 19, and 20 have been amended. Claims 1, 3, and 14-20 are amended. Claim 2 is canceled. Claims 1 and 3-20 are pending. Claims 1 and 3-20 are rejected.
Response to Arguments
I. Applicant's arguments filed 10/07/2025 have been fully considered but they are not persuasive.
II. Regarding the Obviousness-Type Double Patenting, applicant argues “unlike the recited features of claim 1, the boot images in Kochar are not received from a ‘host system’, are not a ‘a request to switch to performing the boot-up procedure according to a second power mode,’ and are not transmitted ‘during performance of the boot-up procedure according to the first power mode.’ Thus, Kochar is insufficient to teach or suggest the above recited features of claim 1.” Examiner respectfully disagrees.
Despite different wordings, Palmer teaches the following limitations of claim 1 of the instant application: the structure, signaling to boot/power-on a memory system using a host system, determining which mode to boot the memory device in according to one of two power modes, requesting the boot, and performing the boot according to the determination. Notably, the structure of a ‘host system’ and the limitation of to ‘receive, from the host system, a command to perform the boot-up operation’ [of a memory device] are disclosed by Palmer. Kochar is relied upon for the teachings of the determination during the boot up procedure to switch from booting in a first mode to booting in a second mode (Kochar Col. 8 Lines 1-16, a first boot image [i.e., boot mode, see Kochar Col. 5 Lines 43-53, boot image is selected according to available power] may be used in a first stage, then a second boot image may be selected [i.e., switched to] based on indicated power available; and Col. 8 Lines 1-16, a set of configurable resources may be configured in both stages [i.e., the boot process is ongoing during both stages]). Therefore, claim 1 is obvious in view of the combination of Palmer and Kochar.
III. Applicant argues that “Nabhane does not teach or suggest a host system that ‘transmit[s], to the memory system during performance of the boot-up procedure by the memory system according to the first power mode, a request for the memory system to switch to performing the boot-up procedure according to the second power mode,’ as recited in claim 14” and that “Kochar does not cure the deficiencies of Nabhane [because] Kochar describes multi-stage initialization processes in which "different boot images are used in different stages.” Examiner respectfully disagrees.
Applicant states that the “PMU 100 in Nabhane is not a host system” and “the communicated operating parameters in Nabhane are neither a "request for the memory system to switch to performing the boot-up procedure according to the second power mode" because “the cited section of Nabhane merely discusses the communication of system parameters from a PMU 100 to a power processor 132.” However, the system parameters transmitted in Nabhane constitute switching the boot mode from a default boot mode (Nabhane par. 51, OTP map in PSU 100 may store initial voltage settings) to a secondary boot mode (Nabhane par. 51, additionally the PMU controller 101 may set voltage and/or current settings for one or more of the power rails 120-124 based on instructions from the host SOC 130). The host SOC 130 constitutes a host system of which power management unit (PMU) 100 is an element, as the system is responsible for the booting of the elements of the system (Nabhane par. 80, one or more operating parameters for one or more of the application processor 140, the modem 141, the graphics processor 142, one or more of the subsystems 170-173, or other elements of the system 10 [see FIG. 1, system memory 184 is an element of system 10]). Therefore, updating the operating parameters by the PMU is a "request for the memory system to switch to performing the boot-up procedure according to the second power mode."
Kochar discusses boot images, which are selected based on power consumption of an apparatus (Kochar Col. 5 Lines 43-53, boot image is selected according to available power; also see Kochar FIG. 5, each boot image is selected to be utilized within a certain power range), therefore each boot image is a boot mode based on power consumption. In Kochar, the booting mode switch is performed “during performance of the boot-up procedure” (Kochar Col. 8 Lines 1-16, a set of configurable resources may be configured in both stages [i.e., the boot process is ongoing during both stages]; and Kochar Col. 8 Lines 1-16, a first boot image [i.e., boot mode, see Kochar Col. 5 Lines 43-53, boot image is selected according to available power] may be used in a first stage, then a second boot image may be selected [i.e., switched to] based on indicated power available).
Therefore, the combination of Nabhane and Kochar fully teaches “transmit[ting], [by the host system] to the memory system during performance of the boot-up procedure by the memory system according to the first power mode, a request for the memory system to switch to performing the boot-up procedure according to the second power mode” as recited by claim 14.
IX. Applicant argues that “Nabhane does not teach or suggest a memory system that ‘receive[s], during performance of the boot-up procedure according to the first power mode and from a host system that provides power to the memory system, a request to switch to performing the boot-up procedure according to a second power mode associated with a second power consumption different than the first power consumption,’ as recited in claim 1. Examiner respectfully disagrees.
Applicant states “there is no indication in Nabhane the PMU 100-or any other component of the system 10-receives ‘a request to switch to performing the boot-up procedure according to a second power mode associated with a second power consumption different than the first power consumption.’” However, the system parameters transmitted in Nabhane constitute switching the boot mode from a default boot mode (Nabhane par. 51, OTP map in PSU 100 may store initial voltage settings) to a secondary boot mode (Nabhane par. 51, additionally the PMU controller 101 may set voltage and/or current settings for one or more of the power rails 120-124 based on instructions from the host SOC 130), and that the modes are associated with power consumption (Nabhane par. 52, OTP map 106 maps settings based on system state (ex. different battery chargers or charging ports which may be coupled to the system bus 180), which dictate modes distinct from the initial (first) mode). By updating these parameters, the PMU is transmitting a request to switch the boot mode of the system.
Kochar discusses boot images, which are selected based on power consumption of an apparatus (Kochar Col. 5 Lines 43-53, boot image is selected according to available power; also see Kochar FIG. 5, each boot image is selected to be utilized within a certain power range), therefore each boot image is a boot mode based on power consumption. In Kochar, the booting mode switch is performed “during performance of the boot-up procedure” (Kochar Col. 8 Lines 1-16, a set of configurable resources may be configured in both stages [i.e., the boot process is ongoing during both stages]; and Kochar Col. 8 Lines 1-16, a first boot image [i.e., boot mode, see Kochar Col. 5 Lines 43-53, boot image is selected according to available power] may be used in a first stage, then a second boot image may be selected [i.e., switched to] based on indicated power available). The process for indicating power available and then switching the mode would necessitate a request to a boot manager (Kochar FIG. 1, boot loader 142) to update the boot image. Kochar is replied upon for the teaching of switching the boot mode during the performance of the boot-up procedure.
Therefore, the combination of Nabhane and Kochar fully teaches “a memory system that ‘receive[s], during performance of the boot-up procedure according to the first power mode and from a host system that provides power to the memory system, a request to switch to performing the boot-up procedure according to a second power mode associated with a second power consumption different than the first power consumption.”
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 11, and 21 of Palmer et. al. (U.S. Patent No. 11868632 B2) in view of Kochar et. al. (US 9652252 B1). Although the claims at issue are not identical, they are not patentably distinct from each other, with the differences underlined below:
Instant Application
U.S. Patent No. 11868632B2
1. An apparatus, comprising:
a memory device; and
a controller coupled with the memory device and configured to cause the apparatus to:
initiate a boot-up procedure of a memory system according to a first power mode associated with a first power consumption;
receive, during performance of the boot-up procedure according to the first power mode and from a host system that provides power to the memory system, a request to switch to performing the boot-up procedure according to a second power mode associated with a second power consumption different than the first power consumption;
determine, during the boot-up procedure and based at least in part on the request, whether to switch from performing the boot-up procedure according to the first power mode to performing the boot-up procedure according to a second power mode associated with a second power consumption different than the first power consumption; and
switch, after performing a portion of the boot-up procedure, from performing the boot-up procedure according to the first power mode to performing the boot-up procedure according to the second power mode based at least in part on determining to switch to performing the boot-up procedure according to the second power mode.
1. An apparatus, comprising:
a controller associated with a memory device, wherein the controller is configured to cause the apparatus to:
receive, at a memory system, a signal from a host system to power-on the memory system;
determine whether to boot-up the memory system in a first power mode or a second power mode based at least in part on one or more characteristics of a previous boot-up operation of the memory system, the first power mode configured to use more current than the second power mode; and
perform a boot-up operation in the first power mode or in the second power mode based at least in part on determining whether to boot-up the memory system in the first power mode or the second power mode.
Independent Claim 1 of the instant application and Claim 1 of Palmer are both directed towards a method to initialize a memory system in one of two operational modes. Despite different wordings, Palmer teaches the following limitations of claim 1 of the instant application: the structure, signaling to boot/power-on a memory system using a host system, determining which mode to boot the memory device in according to one of two power modes, requesting the boot, and performing the boot according to the determination.
The claims of Palmer do not explicitly speak to beginning a boot procedure in the first mode, then performing the determination during the boot up procedure to switch from booting in a first mode to booting in a second mode (i.e. switching the power mode after a portion of the boot-up procedure took place).
In the analogous art of boot up procedures, Kochar teaches to:
initiate a boot-up procedure of a memory system according to a first power mode associated with a first power consumption (Kochar FIG. 5, boot image is set for each power level range [requesting to switch vs. continue using same boot mode would be based on power consumption]; and Kochar Col. 8 Lines 1-16, a first boot image [i.e., boot mode, see Kochar Col. 5 Lines 43-53, boot image is selected according to available power] may be used in a first stage; also see Kochar Col. 1 lines 64-67, an apparatus includes a memory and a processor disposed on an IC die [i.e., memory system]);
receive, during performance of the boot-up procedure according to the first power mode […], a request to switch to performing the boot-up procedure according to a second power mode associated with a second power consumption different than the first power consumption (Kochar Col. 8 Lines 1-16, a first boot image [i.e., boot mode, see Kochar Col. 5 Lines 43-53, boot image is selected according to available power] may be used in a first stage, then a second boot image may be selected [i.e., switched to] based on indicated power available; and Col. 8 Lines 1-16, a set of configurable resources may be configured in both stages [i.e., the boot process is ongoing during both stages]);
Therefore, it would have been obvious of one of ordinary skill in the art, having the teachings of Palmer and Kochar before them, before the effective filing date of the claimed invention, to combine Palmer’s architecture and method for determining a boot mode of a memory system with Kochar’s multi-stage initialization process, the motivation being to optimize the configuration of sets of resources based on the amount of available power (Kochar Col. 8 Lines 1-16).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3, 9, 11-15, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Nabhane et. al. (US 2014/0223217 A1) [previously cited] in view of Kochar et. al. (US 9652252 B1) [previously cited].
Regarding Claim 1, Nabhane discloses an apparatus (Nabhane Figure 1, system 10), comprising:
a memory device (Nabhane FIG. 1, system memory 184); and
a controller (Nabhane FIG. 1, power management unit (PMU) 100 and power processor 132, which interface to control power distributed to system [see par. 39 stating they may be combined as a single circuit]) coupled with the memory device (Nabhane par. 34, a power rail may connect PMU 100 to system memory 184) and configured to cause the apparatus to:
initiate a boot-up procedure of a memory system according to a first power mode associated with a first power consumption (Nabhane par. 51, OTP map in PSU 100 may store initial voltage settings [i.e., a first power mode, see par. 79 and FIG. 3, operating parameters are based on operating environment, including power consumption] for one or more of the power rail circuits that supply components of host SOC 120, including memory 184; and par. 61 and 79, application processor and other system elements [i.e., system memory] may be transitioned from a powered-off to a powered-on mode of operation [i.e., boot initiated] by power manager 206);
receive, […] from a host system that provides power to the memory system (Nabhane FIG. 1, Host SoC 130 [i.e., host system] provides power to system memory 184, see par. 58, the power manager provides coordinates a power up sequence to power up the elements of the system 10 [see FIG. 1, system memory is an element of Host SoC 130]), a request to switch to performing the boot-up procedure according to a second power mode associated with a second power consumption different than the first power consumption (Nabhane FIG. 2B step 216 and par. 80, set the operating parameters for elements of the system 10 [i.e., request boot mode to be switched via parameter update]; and par. 63, the operating parameter may indicate that the application processor 140 must boot according to a certain limitation of operating power or timing, to conserve power] [i.e., modes have different power consumptions]);
determine, […] based at least in part on the request, whether to switch from performing the boot-up procedure according to the first power mode to performing the boot-up procedure according to the second power mode associated with the second power consumption different than the first power consumption (Nabhane par. 62, operating parameter for application processor 140 is based on evaluation parameter of PMU 100, which determines the mode of startup; and par. 52, OTP map 106 maps settings based on system state (e.g., different battery chargers or charging ports which may be coupled to the system bus 180), which dictate modes distinct from the initial (first) mode; and par. 63, the operating parameter may indicate that the application processor 140 must boot according to a certain limitation of operating power or timing, to conserve power] [i.e., modes have different power consumptions]); and
switch, […], from performing the boot-up procedure according to the first power mode to performing the boot-up procedure according to the second power mode based at least in part on determining to switch to performing the boot-up procedure according to the second power mode (Nabhane FIG. 2B step 216 and par. 80, operating parameters for one or more of the application processor 140, the modem 141, the graphics processor 142, one or more of the subsystems 170-173, or other elements of the system 10 are set [i.e., it is determined the booting mode should be switched from the initial configuration, see par. 51, initial voltage and/or current settings for one or more of the power rails may be stored in OTP memory]; and FIG. 2B step 226, boot is completed based on operating parameters [i.e., boot mode is switched based on the determining to switch]).
Nabhane does not explicitly teach:
receive, during performance of the boot-up procedure according to the first power mode and from a host system that provides power to the memory system, a request to switch to performing the boot-up procedure according to a second power mode associated with a second power consumption different than the first power consumption;
determine, during the boot-up procedure and based at least in part on the request, whether to switch from performing the boot-up procedure according to the first power mode to performing the boot-up procedure according to the second power mode associated with the second power consumption different than the first power consumption; and
switch, after performing a portion of the boot-up procedure, from performing the boot-up procedure according to the first power mode to performing the boot-up procedure according to the second power mode based at least in part on determining to switch to performing the boot-up procedure according to the second power mode.
In the analogous art of boot up procedures, Kochar teaches an apparatus (Kochar FIG. 1, IC 120), comprising:
a controller coupled with the memory device (Kochar FIG. 1, boot loader circuit 142 [i.e., controller] coupled to non-volatile memory 144 [i.e., memory 144]) and configured to cause the apparatus to:
receive, during performance of the boot-up procedure according to the first power mode […] (Kochar Col. 1 lines 64-67, an apparatus includes a memory and a processor disposed on an IC die [i.e., memory system]), a request to switch to performing the boot-up procedure according to a second power mode associated with a second power consumption different than the first power consumption (Kochar Col. 8 Lines 1-16, a first boot image [i.e., boot mode, see Kochar Col. 5 Lines 43-53, boot image is selected according to available power] may be used in a first stage, then a second boot image may be selected [i.e., switched to] based on indicated power available; and Col. 8 Lines 1-16, a set of configurable resources may be configured in both stages [i.e., the boot process is ongoing during both stages]; and Kochar FIG. 5, boot image is set for each power level range [requesting to switch vs. continue using same boot mode would be based on power consumption]);
determine, during the boot-up procedure and based at least in part on the request, whether to switch from performing the boot-up procedure according to the first power mode to performing the boot-up procedure according to the second power mode associated with the second power consumption different than the first power consumption (Kochar Col. 8 Lines 1-16, a first boot image [i.e., boot mode, see Kochar Col. 5 Lines 43-53, boot image is selected according to available power] may be used in a first stage, then a second boot image may be selected [i.e., switched to] based on indicated power available; and Col. 8 Lines 1-16, a set of configurable resources may be configured in both stages [i.e., the boot process is ongoing during both stages]); and
switch, after performing a portion of the boot-up procedure, from performing the boot-up procedure according to the first power mode to performing the boot-up procedure according to the second power mode based at least in part on determining to switch to performing the boot-up procedure according to the second power mode (Kochar Col. 8 Lines 1-16, a first boot image [i.e., boot mode, see Kochar Col. 5 Lines 43-53, boot image is selected according to available power] may be used in a first stage, then after the first boot stage, a second boot image may be selected [i.e., switched to] based on indicated power available; and Col. 8 Lines 1-16, a set of configurable resources may be configured in both stages [i.e., the boot process is ongoing during both stages, therefore a portion is completed before the switch]).
Therefore, it would have been obvious of one of ordinary skill in the art, having the teachings of Nabhane and Kochar before them, before the effective filing date of the claimed invention, to combine Nabhane's architecture and method for determining a boot mode with Kochar’s multi-stage initialization process, the motivation being to optimize the configuration of sets of resources based on the amount of available power (Kochar Col. 8 Lines 1-16).
Regarding Claim 3, Nabhane in view of Kochar discloses the apparatus of claim 1, wherein to receive the request the controller is further configured to cause the apparatus to:
read a value of a register of the memory system (Nabhane par. 92, operating parameters for boot are read; and Nabhane par. 63, boot sequence of the application processor 140 may be impacted by the operating parameter which was set or stored in the register bank 150; also see par. 81, setting the operating parameters may be performed by the power processor 132 by storing data, flags, or logic levels, for example, in the register banks 150-152), the value indicating whether to perform the boot-up procedure according to the first power mode or the second power mode (Nabhane Figure 2B step 226, start is based on operating parameters, first mode is achieved by initial voltage settings, settings can be changed for second mode (e.g. in par. 84)).
Regarding Claim 9, Nabhane in view of Kochar teaches the apparatus of claim 1, wherein the controller is further configured to cause the apparatus to:
receive power at the memory system, wherein initiating the boot-up procedure is based at least in part on receiving the power (Nabhane par. 88, boot can occur if sufficient power is supplied to, for example, system memory 184).
Regarding Claim 11, Nabhane in view of Kochar teaches apparatus of claim 1, wherein initiating the boot-up procedure according to the first power mode is based at least in part on the first power mode being a preconfigured power mode for the boot-up procedure (Nabhane par. 51, OTP map 106 may be programmed with initial conditions [preconfigured power mode] for boot at time of manufacture).
Regarding Claim 12, Nabhane in view of Kochar teaches the apparatus of claim 1, wherein the controller is further configured to cause the apparatus to:
store, in a register, a value indicating the first power mode (Nabhane Figure 1, OTP map 103 holds initial values for initial voltage settings, for example, for one or more of the power rail circuits 120-124 (see par. 51); also see par. 81, setting the operating parameters may be performed by the power processor 132 by storing data, flags, or logic levels, for example, in the register banks 150-152); and
lock the register to store the value, wherein initiating the boot-up procedure according to the first power mode is based at least in part on the register being locked to store the value (Nabhane par. 34, OTP map is one time programmable and therefore locked; Nabhane par. 51 logical values stored in OTP map are used to direct operation of PMU controller which is used for system boot).
Regarding Claim 13, Nabhane in view of Kochar teaches the apparatus of claim 1, wherein the second power consumption is less than the first power consumption (Nabhane par. 63, boot-up is affected by stored operating parameter (e.g., operating parameter may indicate that the application processor 140 must boot at a certain operating frequency or speed for lower power operation because the battery voltage of the system battery 182 is marginal), second power mode would be lower operating frequency of processor, see par. 63, the operating parameter may indicate that the application processor 140 must boot according to a certain limitation of operating power or timing, to conserve power]).
Regarding Claim 14, Nabhane discloses a host system (Nabhane Figure 1, system 10), comprising:
a controller configured to couple with a memory system, wherein the controller is configured to cause the host system to:
a controller (Nabhane Figure 1, power management unit (PMU) 100 and power processor 132, which interface to control power distributed to system [see par. 39 stating they may be combined as a single circuit]) configured to couple with a memory system (Nabhane Figure 1, system memory 184; Nabhane par. 34, a power rail may connect PMU 100 to system memory 184), wherein the controller is configured to cause the host system to:
supply power to the memory system (Nabhane par. 34, a power rail may connect PMU 100 to system memory 184) make a determination based at least in part on supplying the power (Nabhane Figure 2A step 210 and par. 77, operating parameters are updated based on any system status parameters [ex. Figure 3, step 304 supply of power] that have recently changed, operating parameters are used to determine boot up mode)
transmit a request for the memory system to perform the boot-up procedure according to the second power mode (Nabhane par. 78, boot uses parameters stored in PMU register bank 103, which adjust boot settings [i.e. the second power mode]).
The remaining limitations of claim 14 are similar in scope to claim 1 as addressed above and is thus rejected under the same rationale.
Regarding Claim 15, Nabhane in view of Kochar discloses the host system of claim 14, wherein to transmit the request the controller is further configured to cause the host system to:
write a value indicating the second power mode to a register of the memory system (Nabhane par. 63, boot-up is affected by stored operating parameter in the PMU register bank 103 (ex. operating parameter may indicate that the application processor 140 must boot at a certain operating frequency or speed for lower power operation because the battery voltage of the system battery 182 is marginal), second power mode would be lower operating frequency of processor; and par. 81, setting the operating parameters may be performed by the power processor 132 [i.e., controller] by storing data, flags, or logic levels, for example, in the register banks 150-152);
Regarding Claim 17, Nabhane in view of Kochar disclose the host system of claim 14, wherein the controller is further configured to cause the host system to:
determine that the power supplied to the memory system is less than the first power consumption (Nabhane par. 63, operating parameter indicates power supplied is less than power expected by initial conditions because battery voltage of the system battery 182 is marginal), wherein determining to request the memory system to switch to performing the boot-up procedure according to the second power mode is based at least in part on the power supplied to the memory system being less than the first power consumption (Nabhane par. 63, boot-up is affected by stored operating parameter in the PMU register bank 103).
Regarding Claim 18, Nabhane in view of Kochar teaches the apparatus of claim 14, wherein the controller is further configured to cause the host system to:
initiate a second boot-up procedure of a host system (Nabhane Figure 2A step 210, operating parameters for boot are adjusted; or Kochar Col. 5 Lines 43-53, a second boot image may be selected [i.e., initiated]), wherein supplying the power to the memory system to initiate the boot-up procedure is based at least in part on initiating the second boot-up procedure of the host system (Nabhane par. 90, power rails are set to supply power to elements of the system 10 which are about to be released to start or boot).
Regarding Claim 19, Nabhane in view of Kochar teaches the host system of claim 14, wherein the controller is further configured to cause the host system to:
determine a power level provided to the memory system for the boot-up procedure, wherein determining whether to request the memory system to switch to performing the boot-up procedure according to the second power mode is based at least in part on determining the power level (Nabhane par. 83, current available to the system is determined and used to make decision about operations at step 222 (see par. 90); Kochar Col. 8 Lines 1-16, a second boot image may be selected after the first boot stage [i.e., switched to] based on indicated power available).
Regarding Claim 20, Nabhane teaches a non-transitory computer-readable medium storing code comprising instructions which, when executed by a processor of an electronic device (Nabhane par. 32, system memory 184 may store computer-readable instructions to be executed by processors 140-142).
The remaining clauses in claim 20 are similar in scope to claim 1 as addressed above, and thus rejected under the same rationale.
Claims 4-8, 10, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Nabhane in view of Kochar further in view Wang (US 2021/0373642 A1) [previously cited].
Regarding Claim 4, Nabhane in view of Kochar discloses the apparatus of claim 1, wherein the second power consumption is [different] than the first power consumption (Nabhane par. 63, operating parameter may specify a certain operating frequency or speed for lower power operation; and Nabhane par. 73 and par. 77, system parameters are stored in PMU register bank 103 and updated based on operating conditions; also see par. 63, charge stored in the system battery 182 may be sufficient only to support a low frequency—rather than a high frequency—boot [i.e., there are high and low power consumption boot options]).
Nabhane does not explicitly teach that the second power consumption is greater than the first power consumption.
In the analogous art of configuring operating parameters for a device before boot to meet power and user needs, Wang teaches an apparatus (Wang FIG. 1, information handling system 100) undergoing a booting operation (Wang par. 20, algorithm 200 for controlling an information handling system with a wide range power mechanism for over-speed memory design from a real time clock (RTC) boot):
wherein the second power consumption is greater than the first power consumption (Wang par. 22, overclock configuration setting for boot [running at a higher frequency requires more power], otherwise a boot setting is implemented for a standard configuration setting).
Therefore, it would have been obvious to one of ordinary skill in the art, having the teachings of Nabhane and Wang before them, before the effective filing date of the claimed invention, to combine the operating parameter update of Nabhane with Wang’s teaching to increase the operating frequency of the memory, the motivation being to increase data access speed and support higher performance data processing system solutions (Wang par. 10).
Regarding Claim 5, Nabhane in view of Kochar, further in view of Wang discloses the apparatus of claim 4, wherein:
to perform the boot-up procedure according to the first power mode the controller is further configured to cause the apparatus to operate the memory system according to a first clock rate (Nabhane par. 63, operating parameter specifies to adjust the operating frequency or speed [i.e., clock rate]; and par. 64, current draw for the system [which includes system memory 184] is used to determine conditions for power up); and
to perform the boot-up procedure according to the second power mode the controller is further configured to cause the apparatus to operate the memory system according to a second clock rate that is faster than the first clock rate (Nabhane Claim 13, stating value in register bank sets an operating frequency or speed of the application processor [i.e. the clock rate]; and Nabhane par. 62 stating register can store operating parameter that can be modified (see par. 63, boot operating frequency is adjusted); and Wang par. 22, overclock configuration setting for boot [running at a higher frequency requires more power], otherwise a boot setting is implemented for a standard configuration setting).
Regarding Claim 6, Nabhane in view of Kochar, further in view of Wang discloses the apparatus of claim 4, wherein:
to perform the boot-up procedure according to the first power mode the controller is further configured to cause the apparatus to supply power to a first quantity of components of the memory system (Nabhane FIG. 1 and par. 51, , the logical values retained in the OTP map 106 [i.e., first power mode] may be relied upon to store initial voltage settings, for example, for one or more of the power rail circuits 120-124 [which supply power to components; or Kochar Col. 8 Lines 1-16, a set of programmable resources [i.e., components] is configured [i.e., supplied power] during the first boot stage using the first boot image); and
to perform the boot-up procedure according to the second power mode the controller is further configured to cause the apparatus to supply power to a second quantity of components of the memory system that is [different] than the first quantity (Nabhane FIG. 1 and par. 51, PMU controller 101 may set voltage and/or current settings for one or more of the power rails 120-124 [i.e., which supply power to components] based on instructions from the host SOC 130; and par. 55, PMU may couple or decouple power from the power rails; also see par. ).
Nabhane does not explicitly teach:
to perform the boot-up procedure according to the second power mode the controller is further configured to cause the apparatus to supply power to a second quantity of components of the memory system that is greater than the first quantity.
Nabhane teaches individually controlling the power rails based on power mode (Nabhane par. 51, PMU controller 101 may set voltage and/or current settings for one or more of the power rails 120-124 based on instructions from the host SOC 130), to individually power elements that require a higher voltage (Nabhane par. 88, use of the strap switch 129 at reference numeral 218 may permit the system 10 to start or boot faster, because it is not necessary to wait for the system battery 182 to charge to a relatively higher voltage which may be required for operation of certain elements in the system 10), and releasing elements to boot in any suitable sequence or arrangement (Nabhane par. 91, elements of the system 10 may be released respectively in time, in combinations over time, together). Therefore, it would have been obvious of one of ordinary skill in the art, having the teachings of Nabhane, Kochar, and Wang before him, before the effective filing date of the claimed invention, that a first power mode or second power mode for the boot up procedure may involve supplying power to a different subset of components in the system, and a mode using more power may supply power to more components.
Regarding Claim 7, the scope is similar to claim 6 as addressed above, except that a quantity of “memory devices of the memory system” is cited instead of a quantity of “components of the memory system.” System 10 of Nabhane depicts multiple memory devices (Nabhane Figure 1, system memory 184, register banks 150-152, memory 133, PMU register bank 103), which are a subset of components of the SOC referenced in claim 6.
Therefore, it would be obvious to someone of ordinary skill in the art that a first power mode or second power mode for the boot up procedure may involve supplying power to a subset of the memory devices in the system.
Regarding Claim 8, Nabhane in view of Kochar, further in view of Wang discloses the apparatus of claim 4, wherein to perform the boot-up procedure according to the first power mode the controller is further configured to cause the apparatus to:
execute one or more first operations based at least in part on the one or more first operations being associated with power consumption below a threshold (Nabhane par. 74, operation to determine to start power manager 131 [i.e., first operation] carried out while minimum power threshold is not yet reached; or Nabhane par. 82-84, application processor 140 may be permitted to start or boot [i.e., first operations] earlier than would be possible otherwise due to current supplying the system being at a marginal VBat voltage level), and
refrain from executing one or more second operations based at least in part on the one or more second operations being associated with power consumption above the threshold (Nabhane Figure 2B, setting strap for power rails operation is skipped if system uses bus power instead of battery power; Nabhane par. 89 battery power is used when above a power threshold and therefore strap operation can be skipped); and
to perform the boot-up procedure according to the second power mode the controller is further configured to cause the apparatus to:
execute the one or more first operations, and execute the one or more second operations (Nabhane Figure 3, evaluating system parameters 302-310 are operations used to configure boot in either mode, operations must occur to update operational variables for second mode (see par. 92).
Regarding Claim 10, Nabhane in view of Kochar, further in view of Wang discloses the apparatus of claim 9, wherein the controller is further configured to cause the apparatus to:
determine that the received power is greater than the first power consumption associated with the first power mode (Wang par. 36, determination whether memory can support one or more overclock settings, may be based on power available (ex. voltage required for an overclock; and Nabhane par. 79 and FIG. 3, operating parameters are based on operating environment, including power consumption), wherein determining to switch to performing the boot-up procedure according to the second power mode is based at least in part on the received power being greater than the first power consumption (Kochar Col. 8 Lines 1-16, a first boot image may be used in a first stage, then after completing the first boot stage, a second boot image may be selected based on indicated power available [i.e., switch to a different boot image is based on received power changing]; also see Kochar FIG. 5, boot image is set for each power level range [requesting to switch vs. continue using same boot mode would be based on power consumption]).
Claim 16, is similar in scope to claim 10 as addressed above and is thus rejected under the same rationale.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLE JIAWEI WENTZEL whose telephone number is (703) 756-4762. The examiner can normally be reached 9:30am-5:30pm ET (Mon-Fri).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Jung can be reached on (571) 270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C.J.W./Examiner, Art Unit 2175
/ANDREW J JUNG/Supervisory Patent Examiner, Art Unit 2175