Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II (claims 5 – 10) in the reply filed on August 15, 2025 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 5 – 10 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida (US 2002/0079508) and Micovic et al. (US 2003/0218183).
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(Claim 5) Yoshida et al. teach a method for fabricating a high electron mobility transistor comprising:
sequentially forming a lattice matching layer (2, buffer, paragraph 26), a channel layer (3), and an AlGaN layer (4, paragraph 27) on a growth substrate (1),
wherein the AlGaN layer (4) comprises a first area (region left of 6), a second area (region occupied by 6), and a third area (region right of 6), and the second area is located between the first area and the third area;
forming an insulation block (6, paragraph 35) on the second area of the AlGaN layer (4);
respectively forming two GaN blocks (5, paragraph 37) on the first area and the third area of the AlGaN layer (4);
removing the insulation block (paragraph 39); and
forming a gate (G) to directly interface the second area of the AlGaN layer (4).
Yoshida et al. lack respectively forming two InAlGaN blocks on the two GaN blocks; and
respectively forming a source and a drain on the two InAlGaN blocks.
However, Micovic teaches respectively forming two InAlGaN blocks on the two GaN blocks as art recognized equivalents and
respectively forming a source and a drain on the two InAlGaN blocks (paragraph 26) as art recognized equivalents.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references as art recognized equivalents,
(Claim 6) Yoshida et al. teach wherein the step of forming the insulation block on the second area of the AlGaN layer comprises:
sequentially forming an insulation layer and a photoresist layer on the AlGaN layer;
removing the photoresist layer directly above the first area and the third area of the AlGaN layer and leaving the photoresist layer directly above the second area of the AlGaN layer;
removing the insulation layer directly above the first area and the third area of the AlGaN layer and leaving the insulation layer directly above the second area of the AlGaN layer; and
removing the photoresist layer directly above the second area of the AlGaN layer to form the insulation block on the second area of the AlGaN layer (paragraphs 37, 40, 45).
(Claim 7) Yoshida et al. teach wherein the two GaN blocks are formed using metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), or plasma enhanced chemical vapor deposition (PECVD).
Yoshida et al. lack wherein the two InAlGaN blocks are formed using metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), or plasma enhanced chemical vapor deposition (PECVD) (paragraphs 7, 8).
However, Micovic teaches the two InAlGaN blocks are formed using metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), or plasma enhanced chemical vapor deposition (PECVD) as art recognized equivalents (paragraph 67).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references as art recognized equivalents.
(Claim 8) Yoshida et al. teach wherein the growth substrate comprises Si, GaN, SiC, or sapphire (paragraph 8).
(Claim 9) Yoshida et al. teach wherein the lattice matching layer (2, buffer) comprises GaN (paragraph 8).
(Claim 10) Yoshida et al. teach wherein the channel layer (3) comprises GaN (3, paragraph 8).
Conclusion
Prior art made of record and not relied upon, considered pertinent to applicant's disclosure are listed in PTO – 892 Form.
Contact Information
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272- 1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/IGWE U ANYA/Primary Examiner, Art Unit 2891
April 4, 2026
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