DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is non-final and is in response to the claims filed January 17th, 2023. Claims 1-20 are pending, of which claims 1-20 are currently rejected.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in China on 01/17/2022. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: 11i4 mentioned in ¶ 0066.
New corrected drawings in compliance with 37 CFR 1.121(d) are required in this application because Figures 4B do not meet the requirements as set forth in 37 CFR 1.84. As stated in 37 CFR 1.84 (l) “All drawings must be made by a process which will give them satisfactory reproduction characteristics. Every line, number, and letter must be durable, clean, black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined.” The lines and reference numbers of Figures 4B are highly pixelated.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
In addition to Replacement Sheets containing the corrected drawing figure(s), applicant is required to submit a marked-up copy of each Replacement Sheet including annotations indicating the changes made to the previous version. The marked-up copy must be clearly labeled as “Annotated Sheets” and must be presented in the amendment or remarks section that explains the change(s) to the drawings. See 37 CFR 1.121(d)(1). Failure to timely submit the proposed drawing and marked-up copy will result in the abandonment of the application.
Claim Objections
Claims 18-20 are objected to because of the following informalities which recite grammatical issues:
Claim 18 lines 1-2 “ according to claims 1” should be “according to claim 1”.
Claims 19-20 are objected to based on their dependence on an above-objected claim.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5-10, 15, and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites the limitation “a front neuron rotor circuit” on line 28. It is unclear if this mention of “a front neuron rotor circuit” is the same as the front neuron rotor circuit(s) as recited in the same claim line 3 or some other front neuron rotor circuit. Appropriate correction is required. For examination purposes the front neuron rotor circuit as recited on line 28 will be construed to be the same front neuron rotor circuit as recited on line 3.
Claim 5 recites the limitation “a rear neuron rotor circuit” on lines 28-29. It is unclear if this mention of “a rear neuron rotor circuit” is the same as the rear neuron rotor circuit(s) as recited in the same claim line 6 or some other rear neuron rotor circuit. Appropriate correction is required. For examination purposes the rear neuron rotor circuit as recited on lines 28-29 will be construed to be the same rear neuron rotor circuit as recited on line 6.
Because claims 6-10 and 15 depend upon claim 5, claims 6-10 and 15 are also rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite.
Claim 20 recites the limitation “the training input signal” on line 12. There is lack of antecedent basis for this limitation. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 11, and 18-19 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Takeda et al. (US 2019/0205742 A1) (hereinafter “Takeda”).
Regarding claim 1, Takeda teaches:
A reservoir computing apparatus, comprising:
a signal input circuit, configured to receive an input signal (Fig. 1 110 data generator obtains input from database and prepares data for further processing);
a reservoir circuit, comprising a plurality of reservoir sub-circuits, wherein each reservoir sub-circuit of the plurality of reservoir sub-circuits comprises (Fig. 1 120+130+210 as reservoir sub circuits):
a mask sub-circuit, configured to receive the input signal and perform a first processing on the input signal with a first weight to obtain a first processing result (Fig. 1 element 120 as mask sub-circuit; ¶ 0025 first processing with multiplication by weights at element 120), and
a rotating neuron sub-circuit, configured to receive the first processing result from the mask sub-circuit (Fig.1 element 130 also explained in ¶ 0026), and perform a second processing on the first processing result to perform a dimension raising (¶ 0079 raising of dimensions in 120 in order), a nonlinear operation and a recursive connection to obtain a second processing result (¶ 0026 element 130 to output a second processing result from a recurrent connection i.e., recurrent operation and the nodes are nonlinear i.e., nonlinear operation would take place); and
an output layer circuit, configured to multiply a plurality of second processing results of the plurality of reservoir sub-circuits by a second weight matrix to obtain a third processing result, and output the third processing result (output layer Fig. 1 140, ¶ 0071 discusses Wout, which is the matrix coupled between reservoir and the output layer, where the output layer multiplies output from reservoir and multiplies by Wout as shown by Equation 4 in ¶ 0070 for y'(n), also discussed at ¶ 0042).
Regarding claim 11, Takeda teaches:
The reservoir computing apparatus according to claim 1, wherein the output layer circuit comprises:
a multiply accumulating sub-circuit, configured to multiply the plurality of second processing results by the second weight matrix to obtain the third processing result (output layer Fig. 1 140, ¶ 0071 discusses Wout, which is the matrix coupled between reservoir and the output layer, where the output layer multiplies output from reservoir and multiplies by Wout as shown by Equation 4 in ¶ 0070 for y'(n), also discussed at ¶ 0042).
Regarding claim 18, Takeda teaches:
A data processing method, used in the reservoir computing apparatus according to claims 1, comprising:
using the reservoir computing apparatus to perform an inference computing operation (¶ 0021 data used to make predictions i.e., inferences); or
using the reservoir computing apparatus to perform a training computing operation (Fig.1 and ¶ 0021-0022 generating training data i.e., training computing).
Regarding claim 19 recites the method practiced by the apparatus of claim 1 and is therefore rejected for the same reasons therein.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Takeda.
Regarding claim 2, while Takeda teaches an input terminal to receive an input signal (Takeda: Fig. 1 input to 120), performing of the first processing on the input signal using a first weight (Takeda: Fig. 1 element 120 ¶ 0025 first processing with multiplication by weights at element 120), and an output terminal to output the first processing result (Takeda: Fig. 1 output from 120), Takeda does not explicitly teach an input weight configuring sub-circuit.
However, Takeda does discuss the configuring or setting of weights (Takeda: ¶ 0048 configuration being set between Fig. 1 120 and 130). It would be obvious to one of ordinary skill in the art that circuitry would have to be present in order for this functionality to occur.
It would obvious before the effective filing date of the claimed invention to combine the functionality of weight setting as discussed in Takeda with actual circuitry because it would be known to a person having ordinary skill in the art that circuitry would be necessary in order for the functionality to occur.
Regarding claim 12, Takeda teaches:
The reservoir computing apparatus according to claim 2, wherein the output layer circuit comprises:
a multiply accumulating sub-circuit, configured to multiply the plurality of second processing results by the second weight matrix to obtain the third processing result (output layer Fig. 1 140, ¶ 0071 discusses Wout, which is the matrix coupled between reservoir and the output layer, where the output layer multiplies output from reservoir and multiplies by Wout as shown by Equation 4 in ¶ 0070 for y'(n), also discussed at ¶ 0042).
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Takeda further in view of Zhang et al. (10970441) (hereinafter “Zhang”).
Regarding claim 16, while Takeda teaches the reservoir computing apparatus of claim 11, Takeda does not explicitly teach a multiply-accumulating sub-circuit of the output layer comprising a memristor array, having conductance values of the memristors corresponding to the second weight matrix values.
However, Zhang teaches RRAM crossbar arrays i.e., memristor arrays at each layer i.e., including output layer for carrying out a NN operations such as VMM and NAF i.e., matrix multiplication with corresponding weights and having conductance values at the RRAM crossbar arrays representing the values of the matrices during computation, yielding an output in the form of a voltage i.e., conductance (Zhang: Col. 22 Lines 7-29).
It would be obvious before effective filing date of the claimed invention to combine the memristor arrays as taught by Zhang with the reservoir computing apparatus as taught by Takeda as both teachings are directed towards layer-based neural network operations. One with ordinary skill in the art would be motivated to combine the teachings because doing so would allow for a more scaling-compatible and synthesis-friendly configuration (Zhang: Col. 22 Lines 50-55).
Regarding claim 17, Takeda in view of Zhang further teaches the reservoir computing apparatus of claim 16, and additionally the output layer circuit having parameter setting in order to have a conductance value of the memristor array (Zhang: Col. 22 Lines 7-29). It would be obvious to one having ordinary skill in the art to have parameter setting circuitry i.e., parameter setting sub-circuit if there is the functionality of parameter setting already occurring.
The motivation to combine with respect to claim 16 applies equally to claim 17.
Allowable Subject Matter
Claims 3-4, and 13-14 would be allowable if rewritten to include all of the limitations of the base claim and any intervening claims.
Claims 5-10, 15 and 20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Applicant claims an apparatus wherein the apparatus as in claim 1 comprises:
a signal input circuit, configured to receive an input signal;
a reservoir circuit, comprising a plurality of reservoir sub-circuits, wherein each reservoir sub-circuit of the plurality of reservoir sub-circuits comprises:
a mask sub-circuit, configured to receive the input signal and perform a first processing on the input signal with a first weight to obtain a first processing result, and
a rotating neuron sub-circuit, configured to receive the first processing result from the mask sub-circuit, and perform a second processing on the first processing result to perform a dimension raising, a nonlinear operation and a recursive connection to obtain a second processing result; and
an output layer circuit, configured to multiply a plurality of second processing results of the plurality of reservoir sub-circuits by a second weight matrix to obtain a third processing result, and output the third processing result.
Wherein claim 2 is dependent on claim 1 further comprising:
wherein the mask sub-circuit comprises:
an input terminal, configured to receive the input signal;
an input weight configuring sub-circuit, configured to receive a control signal that is related to the first weight, and perform the first processing on the input signal, which is received by the input terminal, and the first weight to obtain the first processing result; and
an output terminal, configured to output the first processing result of the input weight configuring sub-circuit.
Wherein claim 3 is dependent on claim 2 further comprising:
wherein the input weight configuring sub-circuit comprises:
an inverter;
a plurality of switches, wherein each switch of the plurality of switches comprises:
a first switch input terminal,
a second switch input terminal,
a switch output terminal, and
a switch control terminal,
the first switch input terminal is connected with an input terminal of the mask sub-circuit to receive the input signal; the inverter is connected with the input terminal of the mask subcircuit to receive the input signal and inverts the input signal to obtain an inverted input signal;
the second switch input terminal is connected with the inverter to receive the inverted input signal;
the switch output terminal is connected with the output terminal of the mask sub-circuit;
the switch control terminal is configured to receive the control signal and output the input signal that is received by the first switch input terminal or the inverted input signal that is received by the second switch input terminal from the switch output terminal.
The specific reason for indication of allowable subject matter is the specific arrangement of the connections and the terminals of the corresponding switches. Takeda discloses the claimed invention according to the claim mappings above. Takeda does not explicitly disclose the specific arrangement of the connections and the terminals of the corresponding switches.
Claims 4 and 13-14, dependent on claim 3, are therefore also allowable.
Wherein claim 5 is dependent on claim 1 further comprising:
The reservoir computing apparatus according to claim 1, wherein the rotating neuron sub-circuit comprises:
N front neuron rotor circuits, wherein each front neuron rotor circuit of the N front neuron rotor circuits comprises a first gate signal terminal, a first input terminal, and N first output terminals that are ranked from 1st to Nth;
N rear neuron rotor circuits, wherein the N rear neuron rotor circuits are in one-to-one correspondence with the N front neuron rotor circuits, each rear neuron rotor circuit of the N rear neuron rotor circuits comprises a second gate signal terminal, N second input terminals that are ranked from 1st to Nth and a second output terminal;
N neuron circuits, wherein a first terminal of an mth neuron circuit of the N neuron circuits is connected with an mth first output terminal of each front neuron rotor circuit of the N front neuron rotor circuits, a second terminal of the mth neuron circuit of the N neuron circuits is connected with an mth second input terminal of each rear neuron rotor circuit of the N rear neuron rotor circuits;
a timing control circuit, connected with the first gate signal terminal of each front neuron rotor circuit of the N front neuron rotor circuits, connected with the second gate signal terminal of each rear neuron rotor circuit of the N rear neuron rotor circuits, and configured to generate a gate signal, thereby applying the gate signal to the N front neuron rotor circuits and the N rear neuron rotor circuits, simultaneously,
the N front neuron rotor circuits are configured as a whole, such that each front neuron rotor circuit of the N front neuron rotor circuits gates one of the N first output terminals of its own according to the gate signal, and serial numbers of first output terminals that are gated by the N front neuron rotor circuits are different from each other,
the N front neuron rotor circuits are configured as a whole, such that each rear neuron rotor circuit of the N rear neuron rotor circuits gates one of the N second input terminals of its own according to the gate signal, and serial numbers of second input terminals that are gated by the N rear neuron rotor circuits are different from each other,
a first output terminal of a front neuron rotor circuit and a second input terminal of a rear neuron rotor circuit, which are connected with a same neuron circuit, are simultaneously gated,
N is a positive integer greater than 1, m = 1, 2, ... , N.
The specific reason for indication of allowable subject matter is the sub-components of the reservoir sub-circuits, specifically the arrangement of N front neuron rotor circuits, the N neuron circuits, N rear neuron rotor circuits. Takeda and Zhang disclose the claimed invention according to the claim mappings above. Neither Takeda nor Zhang disclose the sub-components of the reservoir sub-circuits, specifically the arrangement of N front neuron rotor circuits, the N neuron circuits, N rear neuron rotor circuits.
Claims 6-10 and 15 are dependent on claim 5, are therefore also allowable.
Wherein claim 18 is dependent on claim 1 further comprising:
A data processing method, used in the reservoir computing apparatus according to claims 1, comprising:
using the reservoir computing apparatus to perform an inference computing operation; or
using the reservoir computing apparatus to perform a training computing operation.
Wherein claim 20 is dependent on claim 18 further comprising:
The data processing method according to claim 18, wherein the training computing operation comprises:
receiving the input signal for the training computing operation and a tag value for the input signal through the signal input circuit;
performing the first processing on the input signal and the first weight through the reservoir circuit to obtain the first processing result, and performing the second processing on the first processing result to perform the dimension raising, the nonlinear operation and the recursive connection to obtain the plurality of second processing results;
multiplying the plurality of second processing results by the second weight matrix through the output layer circuit to obtain the third processing result;
calculating an error of the second weight matrix according to the plurality of third processing results and the tag value for the training input signal to update the second weight matrix; and
writing an updated second weight matrix into the output layer circuit.
The specific reason for indication of allowable subject matter is the tag value inputs and the calculation of an error, followed by writing of an updated second weight matrix. Takeda and Zhang discloses the claimed invention according to the claim mappings above. Neither Takeda nor Zhang disclose the sub-components of the reservoir sub-circuits, specifically the arrangement of N front neuron rotor circuits, the N neuron circuits, N rear neuron rotor circuits.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARIA DE JESUS RIVERA whose telephone number is (571)272-2793. The examiner can normally be reached Monday-Friday 7:30AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Trujillo can be reached at (571) 272-3677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/M.D.R./Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
