DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to amendment filed on 12/29/2025.
Response to Amendment
By this amendment, claims 1-20 are amended. Therefore, claims 1-20 are pending. Any objections and rejections not repeated below is withdrawn due to Applicant's amendment.
Response to Arguments
Applicant's arguments filed 12/29/2025 have been fully considered but they are not persuasive. Applicant argues in substance:
Applicant traverses the OA' s interpretation of "given initiator component" as a "means" element to be interpreted under 35 U.S.C. § 112(f). Page 14, lines 5-10 of the specification explains that "Figure 1 is a block diagram of a system in accordance with one example implementation. A plurality 10 of initiator components 12, 14, 16, 18 is provided, each of which is able to initiate transactions to access a shared resource 25. The initiator components could take a variety of forms, but for the purposes of the present discussion it will be assumed that each initiator component is a separate processing device, for example a separate CPU." The term component is not simply a placeholder term but denotes structure. To avoid this improper interpretation, the claims are amended to replace "given initiator component" with "given initiator processing circuit." Accordingly, no claim terms are to be interpreted under 35 U.S.C. §112(f).
The rejections of all claims 1-20 under 35 U.S.C. § 112(a) and 35 U.S.C. § 112(b) are moot for the reasons stated above.
With regard to point (a), due to claim amendments, Examiner has withdrawn the previous 112(a) and 112(b) rejections.
The proposed combination of Gehman and Neuman fails to teach at least the following features of claim 1: "the gating circuitry is configured, when ... the currently granted initiator processing circuit is other than the given initiator processing circuit, to [A] block onward propagation of the given transaction to the shared resource and to [B] trigger a recovery action to seek to facilitate future handling of the given transaction." Gehman is cited for feature A, NS Neuman is cited for feature B.
For feature A, the OA cites Gehman's col. 3, lines 19-23: "In the event, two or more of devices 107a, 107b, 107c, 107d, and 108 assert requests simultaneously, arbiter 106 will initially grant access to only one of the devices 107a, 107b, 107c, 107d, and 108 and then only according to the priority scheme identified in FIG. 2," and col. 3 lines 35-37: "When multiple requests are received, the master with the highest priority is granted the shared resource." In contrast to the claim language that requires blocking onward propagation of the given transaction to the shared resource, Gehman simply queues the transaction. Consequently, onward propagation is not blocked, but instead merely delayed. See, for example, Gehman's Figure 2, where steps 212 and 224 return to process any other requests. This delayed propagation is also apparent from column 3, lines 23-27: "Once the granted device completes its transaction, the other requesting devices will each have access depending upon their priority at the time of the request." Thus, Gehman does not block the onward propagation, and instead, processes requests in order of their priority.
With regard to point (b), Examiner respectfully disagrees with Applicant that Gehman does not block the onward propagation in independent claims 1, 19, and 20. As Applicant’s claims do not disclose the timing nor length of the request blockage, Examiner utilizes broadest reasonable interpretation on Gehman’s disclosure of priority queuing to read on Applicant’s claims. Gehman discloses that when multiple devices request access to a shared resource, all other requests except for the request of the highest priority device (currently granted initiator processing circuit) are denied. This exclusion of requests functions similarly to a lock where only one device’s request has access to a shared resource and all other requests are blocked (and wait until the device’s request has completed). Therefore, independent claims 1, 19, and 20 and their respective dependent claims are rejected for the reasons in this Office Action’s 103 rejection below. Argument has not been found to be persuasive.
For feature B, "trigger a recovery action to seek to facilitate future handling of the given transaction," the OA cites paragraph [0043] of Neuman quoting "[i]n a pre-emptive system, if a request is received from a higher priority client while a lower priority client is being serviced by the common resource, the arbiter 110 interrupts the processing of the lower priority client's request and provides access to the shared resource to the higher priority client." The OA does not explain how this interrupt of the lower priority client's request in favor of processing a higher-priority client discloses "trigger a recovery action to seek to facilitate future handling of the given transaction." There is no description of facilitating future handling of a given transaction; only the handling of a current transaction is disclosed.
With regard to point (c), Examiner interpreted “trigger a recovery action” in independent claims 1, 19, and 20 in the same manner as with Applicant’s dependent claim 2 (the recovery action which allowed the given transaction to access the shared resource). Thus, Examiner interpreted Neuman’s higher priority client’s request to be the given transaction which interrupts the processing of the lower priority client's request after the arbiter confirms client priorities (future handling of the given transaction). In addition, “future handling” does not have much patentable weight in the limitation as Applicant does not define the breadth nor scope of term “future handling”. Therefore, independent claims 1, 19, and 20 and their respective dependent claims are rejected for the reasons in this Office Action’s 103 rejection below. Argument has not been found to be persuasive.
In addition, claim feature B is inextricably linked to the preceding condition of "when the currently granted initiator processing circuit is other than the given initiator processing circuit," and feature A "block onward propagation of the given transaction to the shared resource." Without this condition being met, there is no blocking of the transaction, and therefore, no recovery action would be required. Claim feature B must be considered in this context. In Neuman, the claimed given transaction corresponds to processing the higher-priority client's transaction, as this is the processing that is actually performed in the cited passage, and therefore, is the only transaction for which "future handling" is even remotely suggested.
In line with the above discussion regarding the claimed preceding condition, the cited passage from Neuman which teaches that if a given client has a higher priority, then current processing is interrupted, is not consistent with the claimed condition ("when ... the currently granted initiator processing circuit is other than the given initiator processing circuit"), which in Neuman, corresponds to the given client having a lower priority and being interrupted.
Therefore, in Neuman, the given client would not be the granted initiator. In other words, if Gehman teaches that in the case that condition X is satisfied then action Y is performed, then a person having ordinary skill in the art (POSITA) would not have considered an action W described in Neuman as being compatible when action W requires that the inverse of condition X is satisfied. Accordingly, even if the claimed feature "trigger a recovery action to seek to facilitate future handling of the given transaction" was disclosed in the cited passage of Neuman, (which it is not), it would not have been obvious to a POSITA to incorporate it within the teaching of Gehman given the incompatibility between the respective contexts.
With regard to point (d), Examiner respectfully disagrees with Applicant that prior arts Gehman and Neuman have different contexts. Both prior arts disclose priority of devices/clients (initiator processing circuits) and requests (transactions) to arbitrate processing requests. In addition, Neuman discloses the condition "when the currently granted initiator processing circuit is other than the given initiator processing circuit" wherein Neuman’s higher priority client is the given initiator processing circuit with a request (given transaction) which interrupts the processing of the lower priority client (original currently granted initiator processing circuit) after the arbiter confirms client priorities (future handling of the given transaction). In addition, “future handling” does not have much patentable weight in the limitation as Applicant does not define the breadth nor scope of term “future handling”. Therefore, independent claims 1, 19, and 20 and their respective dependent claims are rejected for the reasons in this Office Action’s 103 rejection below. Argument has not been found to be persuasive.
Claim Objections
Claims 1-20 are objected to because of the following informalities:
In Claim 1 and 20, “one of a plurality of initiator processing circuit” should read “one of a plurality of initiator processing circuits”.
In Claim 1, 19, and 20, “from amongst the plurality of initiator processing circuit” should read “from amongst the plurality of initiator processing circuits”.
In Claim 13, “in the plurality of initiator processing circuit” should read “in the plurality of initiator processing circuits”.
In Claim 13, “amongst the plurality of initiator processing circuit” should read “amongst the plurality of initiator processing circuits”.
In Claim 14, “by the plurality of initiator processing circuit” should read “by the plurality of initiator processing circuits”.
In Claim 17, “one of the initiator processing circuits in the plurality of initiator processing circuit” should read “one initiator processing circuit in the plurality of initiator processing circuits”.
In Claim 19, “accessible to a plurality of initiator processing circuit” should read “accessible to a plurality of initiator processing circuits”.
In Claim 19, “a given initiator processing circuit of the plurality of initiator processing circuit” should read “a given initiator processing circuit of the plurality of initiator processing circuits”.
Any claim not specifically mentioned above, is objected due to its dependency on an objected claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 10-11, 14-15, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Gehman Pat. No. 6,073,132 in view of Neuman Pub. No. US 2003/0167294 Al.
Regarding claim 1, Gehman teaches an apparatus comprising: a given initiator processing circuit configured to initiate transactions to access a shared resource, where the given initiator processing circuit is one of a plurality of initiator processing circuits that share access to the shared resource (Col. 3 lines 9-11: “Prior to accessing the shared resource 109, one of the devices 107a, 107b, 107c, 107d, and 108 will assert a request to the arbiter 106.”, Note: The devices are the initiator processing circuits that initiate requests (transactions)); shared resource management circuitry configured to select, from amongst the plurality of initiator processing circuits, a currently granted initiator processing circuit that is currently allowed to access the shared resource, and to identify the currently granted initiator processing circuit within a storage structure (Col. 5 lines 1-6: “Once the granted device's transaction is complete (step 218), arbiter 106 changes the priority of the granted device to the lowest priority (step 220) and re-configures the priority of the remaining shifting sequential devices 107a, 107b, 107c, 107d (step 222) according to that found in FIG. 6.”, Col. 7 lines 51-62: “FIG. 6 illustrates the priority schemes immediately in place after a device terminates request for the shared resource 109. First row 602 represents the state from FIG. 4 which was last active. First row 602 further demonstrates a possible order, from left to right, in which devices are granted access, and thereafter relinquish the shared resource 109 where the state idle represents no grants or the default device is granted access. The columns 614, 616, 618, 620, 622, and 624 indicate the re-configured priority levels of each device 107a, 107b, 107c, 107d, and 108 in descending order after the device identified in first row 602 terminates access to shared resource 109.”, Note: The devices are the initiator processing circuits, the arbiter functions similar to the shared resource management circuitry, and the priority scheme is the storage structure that shows the currently granted initiator processing circuit (highest priority initiator processing circuit that requested the same shared resource)); and gating circuitry located in a communication path between the given initiator processing circuit and the shared resource and configured to receive a given transaction initiated by the given initiator processing circuit to access the shared resource, and configured to determine with reference to the storage structure whether the given initiator processing circuit is the currently granted initiator processing circuit (Col. 3 lines 9-14: “Prior to accessing the shared resource 109, one of the devices 107a, 107b, 107c, 107d, and 108 will assert a request to the arbiter 106. The arbiter 106 will then either grant access to shared resource 109 or deny access to the shared resource 109 according to that certain priority scheme identified in FIG. 2.”, Note: The devices are the initiator processing circuits, the arbiter functions similar to the gating circuitry, and the priority scheme is the storage structure); wherein the gating circuitry is configured, when the currently granted initiator processing circuit is the given initiator processing circuit, to allow onward propagation of the given transaction to the shared resource (Col. 3 lines 19-23: “In the event, two or more of devices 107a, 107b, 107c, 107d, and 108 assert requests simultaneously, arbiter 106 will initially grant access to only one of the devices 107a, 107b, 107c, 107d, and 108 and then only according to the priority scheme identified in FIG. 2.”, Col. 3 lines 35-37: “When multiple requests are received, the master with the highest priority is granted the shared resource.”, Note: The devices are the initiator processing circuits, the arbiter functions similar to the gating circuitry, the priority scheme is the storage structure that shows the currently granted initiator processing circuit (highest priority initiator processing circuit that requested the same shared resource), and the highest priority device request (currently granted initiator processing circuit) is allowed), and is configured, when the currently granted initiator processing circuit is other than the given initiator processing circuit, to block onward propagation of the given transaction to the shared resource (Col. 3 lines 19-23: “In the event, two or more of devices 107a, 107b, 107c, 107d, and 108 assert requests simultaneously, arbiter 106 will initially grant access to only one of the devices 107a, 107b, 107c, 107d, and 108 and then only according to the priority scheme identified in FIG. 2.”, Col. 3 lines 35-37: “When multiple requests are received, the master with the highest priority is granted the shared resource.”, Note: The devices are the initiator processing circuits, the arbiter functions similar to the gating circuitry, the priority scheme is the storage structure that shows the currently granted initiator processing circuit (highest priority initiator processing circuit that requested the same shared resource), and all other requests except for the highest priority device request (currently granted initiator processing circuit) are denied)…
Gehman fails to teach to trigger a recovery action to seek to facilitate future handling of the given transaction.
In analogous art Neuman teaches to trigger a recovery action to seek to
facilitate future handling of the given transaction ([0043] “…In a preemptive system, if a request is received from a higher priority client while a lower priority client is being serviced by the common resource, the arbiter 110 interrupts the processing of the lower priority client's request and provides access to the shared resource to the higher priority client…”, Note: The higher priority client is the given initiator processing circuit with a request (given transaction) which interrupts the processing of the lower priority client (original currently granted initiator processing circuit)).
It would have been obvious to a person having ordinary skill in the art prior to the
effective filing date of the claimed invention to have modified Gehman to incorporate the teachings of Neuman to prioritize clients (initiator processing circuits) based on their real-time needs (Neuman [0037] “…rate monotonic scheduling provides a means to prioritize clients based on their real-time needs…”).
Regarding claim 2, Gehman and Neuman teach the apparatus as claimed in Claim 1, and Neuman further teaches wherein the gating circuitry is configured to trigger the recovery action by asserting a signal that triggers processing to be performed in order to cause the shared resource management circuitry to select the given initiator processing circuit as the currently granted initiator processing circuit, to thereby allow the given transaction to be propagated to the shared resource ([0043] “…In a preemptive system, if a request is received from a higher priority client while a lower priority client is being serviced by the common resource, the arbiter 110 interrupts the processing of the lower priority client's request and provides access to the shared resource to the higher priority client…”, Note: The higher priority client is the given initiator processing circuit with a request (given transaction) which interrupts the processing of the lower priority client (original currently granted initiator processing circuit), and the arbiter functions similar to the gating circuitry and the shared resource management circuitry to allow a higher priority client process its request before lower priority clients).
Regarding claim 3, Gehman and Neuman teach the apparatus as claimed in Claim 1, Gehman further teaches wherein the given initiator processing circuit is configured, prior to initiating a first transaction of a sequence of transactions, to determine with reference to the storage structure whether the given initiator processing circuit is the currently granted initiator processing circuit (Col. 3 lines 19-23: “In the event, two or more of devices 107a, 107b, 107c, 107d, and 108 assert requests simultaneously, arbiter 106 will initially grant access to only one of the devices 107a, 107b, 107c, 107d, and 108 and then only according to the priority scheme identified in FIG. 2.”, Col. 3 lines 35-37: “When multiple requests are received, the master with the highest priority is granted the shared resource.”, Note: The devices are the initiator processing circuits, and the priority scheme is the storage structure that shows the currently granted initiator processing circuit (highest priority initiator processing circuit that requested the same shared resource)), and Neuman further teaches to issue a grant request signal to the shared resource management circuitry when the currently granted initiator processing circuit is indicated to be other than the given initiator processing circuit ([0043] “…In a preemptive system, if a request is received from a higher priority client while a lower priority client is being serviced by the common resource, the arbiter 110 interrupts the processing of the lower priority client's request and provides access to the shared resource to the higher priority client…”, Note: The client is the initiator processing circuit, and the arbiter functions similar to the shared resource management circuitry).
Regarding claim 4, Gehman and Neuman teach the apparatus as claimed in Claim 3, Neuman further teaches the shared resource management circuitry is configured, in response to the grant request signal, to select the given initiator processing circuit as the currently granted initiator processing circuit ([0043] “…In a preemptive system, if a request is received from a higher priority client while a lower priority client is being serviced by the common resource, the arbiter 110 interrupts the processing of the lower priority client's request and provides access to the shared resource to the higher priority client…”, Note: The client is the initiator processing circuit, and the arbiter functions similar to the shared resource management circuitry), and Gehman further teaches the given initiator processing circuit is configured, following issuance of the grant request signal, to monitor the storage structure in order to detect when the given initiator processing circuit is indicated as the currently granted initiator processing circuit (Col. 3 lines 19-23: “In the event, two or more of devices 107a, 107b, 107c, 107d, and 108 assert requests simultaneously, arbiter 106 will initially grant access to only one of the devices 107a, 107b, 107c, 107d, and 108 and then only according to the priority scheme identified in FIG. 2.”, Col. 3 lines 35-37: “When multiple requests are received, the master with the highest priority is granted the shared resource.”, Note: The device is the initiator processing circuit, and the priority scheme is the storage structure).
Regarding claim 5, Gehman and Neuman teach the apparatus as claimed in Claim 3, and Gehman further teaches wherein the given initiator processing circuit is configured, responsive to detecting that the currently granted initiator processing circuit is the given initiator processing circuit, to initiate the first transaction (Col. 3 lines 19-23: “In the event, two or more of devices 107a, 107b, 107c, 107d, and 108 assert requests simultaneously, arbiter 106 will initially grant access to only one of the devices 107a, 107b, 107c, 107d, and 108 and then only according to the priority scheme identified in FIG. 2.”, Note: The arbiter grants a device (initiator processing circuit) access to the shared resource), and to then initiate each subsequent transaction in the sequence of transactions without further reference to the storage structure, unless interrupted by the gating circuitry triggering the recovery action in response to detecting that the given initiator processing circuit is no longer the currently granted initiator processing circuit (Col. 4 lines 6-9: “If no other devices are requesting the shared resource except one of the master devices with a low priority in the current shifting sequential arbitration scheme, the master device gets the bus on that cycle.”, Col. 3 lines 19-23: “In the event, two or more of devices 107a, 107b, 107c, 107d, and 108 assert requests simultaneously, arbiter 106 will initially grant access to only one of the devices 107a, 107b, 107c, 107d, and 108 and then only according to the priority scheme identified in FIG. 2.”, Col. 3 lines 35-37: “When multiple requests are received, the master with the highest priority is granted the shared resource.”, Note: Subsequent transactions of the device (initiator processing circuit) are initiated without referencing the priority scheme (storage structure) as there are no other devices with pending transactions).
Regarding claim 6, Gehman and Neuman teach the apparatus as claimed in Claim 1, and Neuman further teaches wherein the gating circuitry is configured to trigger the recovery action by asserting an interrupt signal to the given initiator processing circuit to cause the given initiator processing circuit to execute a given exception handling routine ([0043] “…In a preemptive system, if a request is received from a higher priority client while a lower priority client is being serviced by the common resource, the arbiter 110 interrupts the processing of the lower priority client's request and provides access to the shared resource to the higher priority client…”, Note: The client is the initiator processing circuit, and the arbiter functions similar to the gating circuitry).
Regarding claim 7, Gehman and Neuman teach the apparatus as claimed in Claim 6, Neuman further teaches wherein the given initiator processing circuit is configured, on executing the given exception handling routine, to issue a grant request signal to the shared resource management circuitry ([0043] “…In a preemptive system, if a request is received from a higher priority client while a lower priority client is being serviced by the common resource, the arbiter 110 interrupts the processing of the lower priority client's request and provides access to the shared resource to the higher priority client…”, Note: The client is the initiator processing circuit, and the arbiter functions similar to the shared resource management circuitry), and Gehman further teaches to then monitor the storage structure in order to detect when the given initiator processing circuit is once again indicated to be the currently granted initiator processing circuit (Col. 3 lines 19-23: “In the event, two or more of devices 107a, 107b, 107c, 107d, and 108 assert requests simultaneously, arbiter 106 will initially grant access to only one of the devices 107a, 107b, 107c, 107d, and 108 and then only according to the priority scheme identified in FIG. 2.”, Col. 3 lines 35-37: “When multiple requests are received, the master with the highest priority is granted the shared resource.”, Note: The device is the initiator processing circuit, and the priority scheme is the storage structure).
Regarding claim 8, Gehman and Neuman teach the apparatus as claimed in Claim 7, and Neuman further teaches wherein the given initiator processing circuit is configured to re-initiate the given transaction in response to detecting that the given initiator processing circuit is once again indicated to be the currently granted initiator processing circuit ([0047] “…a new request is received from client 1, and because this is a preemptive system and client 1 has the highest priority, the servicing of client 3 is interrupted and client 1 is granted access to the common resource. When client 1's new request is completely serviced, access to the shared resource is returned to client 3…”, Note: The client is the initiator processing circuit wherein the shared resource is returned to client 3 (currently granted initiator processing circuit)).
Regarding claim 10, Gehman and Neuman teach the apparatus as claimed in Claim 6, and Gehman further teaches wherein the transactions initiated by the given initiator processing circuit conform to a transaction protocol that requires a response to be provided to the given initiator processing circuit for each transaction initiated by the given initiator processing circuit, and the gating circuitry is configured, when blocking onward propagation of the given transaction to the shared resource, to provide a dummy response to the given initiator processing circuit in order to provide compliance with the transaction protocol (Col. 3 lines 9-14: “Prior to accessing the shared resource 109, one of the devices 107a, 107b, 107c, 107d, and 108 will assert a request to the arbiter 106. The arbiter 106 will then either grant access to shared resource 109 or deny access to the shared resource 109 according to that certain priority scheme identified in FIG. 2.”, Note: The devices are the initiator processing circuits, the arbiter functions similar to the gating circuitry, and wherein the device is either granted or denied access to the shared resource (dummy response)).
Regarding claim 11, Gehman and Neuman teach the apparatus as claimed in Claim 1, and Neuman further teaches wherein the gating circuitry is configured to trigger the recovery action by sending a request signal to the shared resource management circuitry to request that the currently granted initiator processing circuit is updated to be the given initiator processing circuit ([0043] “…In a preemptive system, if a request is received from a higher priority client while a lower priority client is being serviced by the common resource, the arbiter 110 interrupts the processing of the lower priority client's request and provides access to the shared resource to the higher priority client…”, Note: The client is the initiator processing circuit, and the arbiter functions similar to the gating circuitry and the shared resource management circuitry).
Regarding claim 14, Gehman and Neuman teach the apparatus as claimed in Claim 1, and Gehman further teaches wherein the gating circuitry is configured to receive transactions issued by the plurality of initiator processing circuits and, for a given received transaction, to determine an initiator processing circuit that initiated the given received transaction and to block or allow onward propagation of the given received transaction in dependence on whether the initiator processing circuit that initiated the given received transaction is identified in the storage structure as the currently granted initiator processing circuit (Col. 3 lines 19-23: “In the event, two or more of devices 107a, 107b, 107c, 107d, and 108 assert requests simultaneously, arbiter 106 will initially grant access to only one of the devices 107a, 107b, 107c, 107d, and 108 and then only according to the priority scheme identified in FIG. 2.”, Col. 3 lines 35-37: “When multiple requests are received, the master with the highest priority is granted the shared resource.”, Note: The devices are the initiator processing circuits, the arbiter functions similar to the gating circuitry, the priority scheme is the storage structure that shows the currently granted initiator processing circuit (highest priority initiator processing circuit that requested the same shared resource), and the highest priority device request (currently granted initiator processing circuit) is allowed while all other device requests are denied).
Regarding claim 15, Gehman and Neuman teach the apparatus as claimed in Claim 1, and Gehman further teaches wherein the shared resource management circuitry is configured to control the storage structure to ensure that, at any point in time, only one initiator processing circuit is indicated as the currently granted initiator processing circuit (Col. 3 lines 19-23: “In the event, two or more of devices 107a, 107b, 107c, 107d, and 108 assert requests simultaneously, arbiter 106 will initially grant access to only one of the devices 107a, 107b, 107c, 107d, and 108 and then only according to the priority scheme identified in FIG. 2.”, Col. 3 lines 35-37: “When multiple requests are received, the master with the highest priority is granted the shared resource.”, Note: The devices are the initiator processing circuits, the arbiter functions similar to the shared resource management circuitry, the priority scheme is the storage structure that shows the currently granted initiator processing circuit (highest priority initiator processing circuit that requested the same shared resource)).
Regarding claim 17, Gehman and Neuman teach the apparatus as claimed in Claim 1, and Gehman further teaches wherein the storage structure comprises a plurality of storage elements, where each storage element is associated with one initiator processing circuit in the plurality of initiator processing circuits and is configured to identify whether an associated initiator processing circuit is the currently granted initiator processing circuit (Col. 7 lines 51-62: “FIG. 6 illustrates the priority schemes immediately in place after a device terminates request for the shared resource 109. First row 602 represents the state from FIG. 4 which was last active. First row 602 further demonstrates a possible order, from left to right, in which devices are granted access, and thereafter relinquish the shared resource 109 where the state idle represents no grants or the default device is granted access. The columns 614, 616, 618, 620, 622, and 624 indicate the re-configured priority levels of each device 107a, 107b, 107c, 107d, and 108 in descending order after the device identified in first row 602 terminates access to shared resource 109.”, Note: The devices are the initiator processing circuits, and the priority scheme is the storage structure that shows the currently granted initiator processing circuit (highest priority initiator processing circuit that requested the same shared resource) wherein there is an order, from left to right, in which devices are granted access).
Regarding claim 18, Gehman and Neuman teach the apparatus as claimed in Claim 1, and Neuman further teaches wherein the gating circuitry is configured to receive at least write transactions issued by the given initiator processing circuit ([0078] “…The system in steps 784, 788 and 790 places other lowest priority tasks such as a graphics accelerator read/write request, a DMA read/write request and a CPU write request, respectively, in this round robin arbitration with four clients.”, Note: The clients are the initiator processing circuits, and the arbiter functions similar to the gating circuitry).
Regarding claim 19, it is a process claim whose limitations are substantially the same as those of claim 1. Accordingly, it is rejected for substantially the same reasons.
Regarding claim 20, Neuman further teaches a non-transitory computer-readable medium to store computer-readable code for fabrication of an apparatus comprising ([0033] “The unified memory architecture may include a memory that is shared by a plurality of devices, and a memory request arbiter coupled to the memory, wherein the memory request arbiter performs real time scheduling of memory requests from different devices having different priorities…”). The other limitations are substantially the same as those of claim 1. Accordingly, it is rejected for substantially the same reasons.
Claims 9 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Gehman Pat. No. 6,073,132 in view of Neuman Pub. No. US 2003/0167294 Al as applied to claims 1-8, 10-11, 14-15, and 17-20 above, and further in view of Kaushik et al. Pub. No. US 2004/0128563 Al (hereafter Kaushik).
Regarding claim 9, Gehman and Neuman teach the apparatus as claimed in Claim 6.
Gehman and Neuman fail to teach wherein: the gating circuitry is configured, when triggering the recovery action, to store the given transaction within buffer circuitry accessible to the gating circuitry, to enable the given transaction to be forwarded on to the shared resource by the gating circuitry once the given initiator processing circuit is once again indicated to be the currently granted initiator processing circuit, without the given initiator processing circuit being required to re-initiate the given transaction.
In analogous art Kaushik teaches wherein: the gating circuitry is configured, when triggering the recovery action, to store the given transaction within buffer circuitry accessible to the gating circuitry ([0040] “…During normal system operation, various types of user applications and system tasks are performed by the system. The task priority and power state of each processor is tracked at block 620. The tracking can include gathering information about task priority, power state, and/or activity state of various physical and/or logic processors. At block 630, a check is made to determine whether any interrupt requests have been received…”, [0045] “The interrupt request is received at the selected processor at block 646. The processor pauses its present task at block 647, if there is a task currently in process. At block 648, the task priority entry for that processor is updated with a new priority value. For one embodiment, the task priority entry is updated at a physical register location on the processor and at the chipset. In another embodiment, the task priority entry at a memory structure maintained by the operating system is updated. At block 649, the processor services the interrupt…”, Note: The processor/OS is the gating circuitry which stores the activity state of its task(s) into a table (buffer circuitry)), to enable the given transaction to be forwarded on to the shared resource by the gating circuitry once the given initiator processing circuit is once again indicated to be the currently granted initiator processing circuit, without the given initiator processing circuit being required to re-initiate the given transaction ([0045] “…The processor resumes the task that was in process before the interrupt and the chipset continues its operations at block 652…”, Note: The processor/OS is the gating circuitry which forwards and resumes the activity of its task(s) from a table (buffer circuitry)).
It would have been obvious to a person having ordinary skill in the art prior to the
effective filing date of the claimed invention to have modified Gehman and Neuman to incorporate the teachings of Kaushik to resume the task that was in process before the interrupt (Kaushik [0045] “…The processor resumes the task that was in process before the interrupt and the chipset continues its operations at block 652…”).
Regarding claim 12, Gehman and Neuman teach the apparatus as claimed in Claim 11, and Gehman further teaches the gating circuitry is configured, following sending of the request signal to the shared resource management circuitry, to monitor the storage structure in order to detect when the given initiator processing circuit is once again indicated to be the currently granted initiator processing circuit (Col. 3 lines 19-23: “In the event, two or more of devices 107a, 107b, 107c, 107d, and 108 assert requests simultaneously, arbiter 106 will initially grant access to only one of the devices 107a, 107b, 107c, 107d, and 108 and then only according to the priority scheme identified in FIG. 2.”, Col. 3 lines 35-37: “When multiple requests are received, the master with the highest priority is granted the shared resource.”, Note: The device is the initiator processing circuit, the arbiter functions similar to the gating circuitry and the shared resource management circuitry, and the priority scheme is the storage structure).
Gehman and Neuman fail to teach wherein: the gating circuitry is configured, when triggering the recovery action, to store the given transaction within buffer circuitry accessible to the gating circuitry … and upon such detection to output the given transaction from the buffer circuitry for onward propagation to the shared resource.
In analogous art Kaushik teaches wherein: the gating circuitry is configured, when triggering the recovery action, to store the given transaction within buffer circuitry accessible to the gating circuitry ([0040] “…During normal system operation, various types of user applications and system tasks are performed by the system. The task priority and power state of each processor is tracked at block 620. The tracking can include gathering information about task priority, power state, and/or activity state of various physical and/or logic processors. At block 630, a check is made to determine whether any interrupt requests have been received…”, [0045] “The interrupt request is received at the selected processor at block 646. The processor pauses its present task at block 647, if there is a task currently in process. At block 648, the task priority entry for that processor is updated with a new priority value. For one embodiment, the task priority entry is updated at a physical register location on the processor and at the chipset. In another embodiment, the task priority entry at a memory structure maintained by the operating system is updated. At block 649, the processor services the interrupt…”, Note: The processor/OS is the gating circuitry which stores the activity state of its task(s) into a table (buffer circuitry)) … and upon such detection to output the given transaction from the buffer circuitry for onward propagation to the shared resource ([0045] “…The processor resumes the task that was in process before the interrupt and the chipset continues its operations at block 652…”, Note: The processor/OS is the gating circuitry which forwards and resumes the activity of its task(s) from a table (buffer circuitry)).
It would have been obvious to a person having ordinary skill in the art prior to the
effective filing date of the claimed invention to have modified Gehman and Neuman to incorporate the teachings of Kaushik to resume the task that was in process before the interrupt (Kaushik [0045] “…The processor resumes the task that was in process before the interrupt and the chipset continues its operations at block 652…”).
Claims 13 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Gehman Pat. No. 6,073,132 in view of Neuman Pub. No. US 2003/0167294 Al as applied to claims 1-8, 10-11, 14-15, and 17-20 above, and further in view of Mikael et al. Pat. No. US 7,174,552 B2 (hereafter Mikael).
Regarding claim 13, Gehman and Neuman teach the apparatus as claimed in Claim 1.
Gehman and Neuman fail to teach wherein a separate instance of the gating circuitry is provided for each initiator processing circuit in the plurality of initiator processing circuits, such that a given instance of the gating circuitry has an associated initiator processing circuit amongst the plurality of initiator processing circuits and is configured to control whether to block or allow onward propagation of a transaction issued by the associated initiator processing circuit in dependence on whether the associated initiator processing circuit is identified in the storage structure as the currently granted initiator processing circuit.
In analogous art Mikael teaches wherein a separate instance of the gating circuitry is provided for each initiator processing circuit in the plurality of initiator processing circuits, such that a given instance of the gating circuitry has an associated initiator processing circuit amongst the plurality of initiator processing circuits and is configured to control whether to block or allow onward propagation of a transaction issued by the associated initiator processing circuit in dependence on whether the associated initiator processing circuit is identified in the storage structure as the currently granted initiator processing circuit (Col. 4 lines 16-23: “FIG. 4 illustrates processes 302, 304 having corresponding semaphore systems 316, 318. Each of the semaphore systems 316, 318 comprises a semaphore 400 to indicate the availability or unavailability of a resource, and a local arbiter 402 that arbitrates for access to a given resource 308 on behalf of its corresponding process 302, 304 by monitoring events of its corresponding process 302, 304 to determine the status of the semaphore 400.”, Figs. 3-4, Note: Each process (initiator processing circuit) has a local arbiter (gating circuitry) which allows or denies access to a resource based on the resource’s semaphore (storage structure)).
It would have been obvious to a person having ordinary skill in the art prior to the
effective filing date of the claimed invention to have modified Gehman and Neuman to incorporate the teachings of Mikael to manage access to shared system resources fairly (Mikael Col. 2 lines 32-34: “In one aspect of the invention is a method for a fairness-based semaphore system for managing access to shared system resources.”).
Regarding claim 16, Gehman and Neuman the apparatus as claimed in Claim 1.
Gehman and Neuman fail to teach wherein the storage structure is a single storage element identifying the currently granted initiator processing circuit.
In analogous art Mikael teaches wherein the storage structure is a single storage element identifying the currently granted initiator processing circuit (Col. 4 lines 16-23: “FIG. 4 illustrates processes 302, 304 having corresponding semaphore systems 316, 318. Each of the semaphore systems 316, 318 comprises a semaphore 400 to indicate the availability or unavailability of a resource, and a local arbiter 402 that arbitrates for access to a given resource 308 on behalf of its corresponding process 302, 304 by monitoring events of its corresponding process 302, 304 to determine the status of the semaphore 400.”, Figs. 3-4, Note: The resource’s semaphore is the storage structure).
It would have been obvious to a person having ordinary skill in the art prior to the
effective filing date of the claimed invention to have modified Gehman and Neuman to incorporate the teachings of Mikael to manage access to shared system resources fairly (Mikael Col. 2 lines 32-34: “In one aspect of the invention is a method for a fairness-based semaphore system for managing access to shared system resources.”).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. In particular, US 20090172675 A1 is cited because it discloses interrupting a transaction without corrupting it.
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/J.C.T./Examiner, Art Unit 2196