DETAILED ACTION
This action is in response to the submission filed on 1/18/2023. Claims 1-12 are presented for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3, 7, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over US 20090030660 A1 (“Celik”) in view of US 9881120 B1 (“Ginetti”).
Regarding claims 1 and 7, Celik teaches:
An electronic device, comprising:
a storage device comprising a program code and a database, wherein the database comprises a plurality of combinations of printed circuit boards and packages and a plurality of channel models (Celik: para [0026], “process 100 transfers the geometric information into one or more tables having a format, such as an ASCII file format, that is compatible with the ANSYS APDL language. For example, the geometric information for each layer of the electronic structure can be transferred into a respective table for that layer. Other file structures and data formats can be used in alternative examples”; para [0027], “each table created in step 103 includes all of the two-dimensional geometric information for a particular layer in the electronic structure. Since the tables are created from the package (or and/or board) design software tool, no assumptions are made regarding the package or board, and no geometrical simplifications are necessary. All of the geometrical information for each layer is contained in the tables in step 103”; para [0028], “beginning at step 104, a parametric detailed model of the electronic structure is generated using the geometrical information contained in the tables created in step 103”); and
a processor, coupled to the storage device, configured to execute the program code to perform the steps of:
obtaining a first combination of the plurality of combinations of printed circuit boards and packages from the database (Celik: Fig. 1, 101, “Package and/or Board Design Tool”; para [0042], “At step 113, process 100 generates or imports a volumetric model of the geometry above the package substrate. The model of any layers or materials above the package substrate can be created to reflect a variety of different package assembly options and methodologies. For example, the model can reflect different sizes of die attached to the substrate and the use of a mold and/or heat spreader. By using different assembly options, the model can be used to analyze different package constructions, such as a molded flip-chip package, a bare die flip-chip package, a package with a stiffener only, etc. Therefore, depending on the package options and the die size, the model of the layers above the package substrate can provide geometric information for these layers to the numerical analysis tool for analysis”);
obtaining a first channel model of the plurality of channel models from the database, wherein the first channel model is generated according to the first combination (Celik: para [0030], “At step 107, process 100 converts the geometrical information from each table to a two-dimensional array, for example. The data for individual layers are used to generate two-dimensional footprints for the geometry of each layer, which include all of the layer attributes, such as locations of … individual traces”; para [0034], “The geometrical information includes the location of each via and via pad, the geometrical center of each conductive trace and the length of each trace along the x and/or y-axis, such as by specifying a start point and an end point. For example, each trace can be represented by a plurality of segments of a known length. Interconnections of vias, via pads and conductive trace segments can be determined from intersections of the geometrical information. The geometrical information for each attribute can be represented in any suitable manner”; para [0036], “Process 100 groups areas with specific attributes (e.g., vias, via plating, individual traces, etc.). For example, all vias are grouped as a via component, and all traces are grouped as a trace component. However, geometric areas having specific attributes can be organized in smaller groups or grouped individually, such by as grouping each via or trace as a separate component, for example. By grouping all vias (or traces, etc.) as a grouped component, these components can be conveniently modeled as a single component for purposes of analyzing thermal, mechanical, electrical or other physical properties”);
determining first die information (Celik: para [0042], “At step 113, process 100 generates or imports a volumetric model of the geometry above the package substrate. The model of any layers or materials above the package substrate can be created to reflect a variety of different package assembly options and methodologies. For example, the model can reflect different sizes of die attached to the substrate and the use of a mold and/or heat spreader. By using different assembly options, the model can be used to analyze different package
constructions, such as a molded flip-chip package, a bare die flip-chip package, a package
with a stiffener only, etc. Therefore, depending on the package options and the die size, the model of the layers above the package substrate can provide geometric information for these layers to the numerical analysis tool for analysis”); and
Celik does not teach but Ginetti does teach:
performing simulation to generate characteristics of a power delivery network (Ginetti: col. 6, lines 51-57, “The power distribution network model aware system schematic may be generated in such a way that designers may utilize any EDA tools (e.g., an IC schematic and layout tool) specific to one or more design fabrics to perform various other tasks such as modifications, analyses, simulations, optimizations, closure, sign-off, etc. with the power distribution network model aware system schematic”; col.s 3-4, “the power delivery network (PDN) model may be determined from the electrical analysis layout by constructing a simulation model that accounts for the one or more I/O nets and electromagnetic coupling effects between the one or more signal nets and power and/or ground. In addition or in the alternative, analysis results may be generated by performing, at a schematic analysis or simulation mechanism or module, one or more system driven analyses on the PDN-aware, multi-fabric full system schematic; the analysis results may be stored at a first location of a non-transitory computer accessible storage medium as the analysis results are being generated or in one or more batches”) and a voltage drop of a system according to the first channel model and the first die information (Ginetti: col.s 13-14, “One or more full system electrical and/or thermal analyses or full system electrical-thermal co-simulations 114B may be performed with the system schematic 112B in light of the power
delivery network of the entire system, not merely a portion thereof. In these embodiments, the PDN is loaded by the entire system. Therefore, impacts on power delivery to individual circuit components, blocks, or cells as well as additional voltage drops caused by, for example, IC packages and/or PCB before delivering power to individual circuit components may be more accurately captured by the full system analyses 114B. For example, additional voltage
drops caused by traces in the power delivery network may cause insufficient power supplied
to an IC. This insufficient power supplied to an IC as well as the additional voltage drops
may skew the IR-drop analysis results in conventional approaches yet can be more accurately modeled and captured with the PDN model aware system schematic 112B”).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Celik (directed to designing an electronic device) and Ginetti (directed to simulating PDN and voltage drop) and arrived at designing an electronic device with simulating PDN and voltage drop. One of ordinary skill in the art would have been motivated to make such a combination “for implementing a multi-fabric mixed-signal electronic design spanning across multiple design fabrics with electrical and thermal analysis awareness” (Ginetti: col. 3).
Regarding claims 3 and 9, Celik does not teach but Ginetti does teach:
The electronic device of claim 1, wherein the first channel model comprises an equivalent resistance and inductance, S- parameters used to represent behaviors of the first combination under different frequencies, or a Simulation Program with Integrated Circuit Emphasis (SPICE) model (Ginetti: col. 16, lines 15-25, “ A chip power model includes a compact electrical representation (e.g., a SPICE, SPICE-like, or SPICE compatible model) of the full-chip or the full-chip PDN of a die in various operating modes so that an IC package or PCB designer may optimize IC package designs or PCB designs with the chip power models of the chips in the IC packages or PCB by, for example, eliminating excessive package layers, decoupling capacitors, power pads, etc. while maintaining power integrity to minimize late stage design issues in some embodiments”).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Celik (directed to designing an electronic device) and Ginetti (directed to SPICE modeling) and arrived at designing an electronic device using SPICE modeling. One of ordinary skill in the art would have been motivated to make such a combination “for implementing a multi-fabric mixed-signal electronic design spanning across multiple design fabrics with electrical and thermal analysis awareness” (Ginetti: col. 3).
Claim 2 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over US 20090030660 A1 (“Celik”) in view of US 9881120 B1 (“Ginetti”), further in view of US 20200258593 A1 (“Badrieh”).
Regarding claims 2 and 8, Celik and Ginetti do not teach but Badrieh does teach:
The electronic device of claim 1, wherein the first die information comprises in-die resistance (Badrieh: para [0054], “The process flow 400 may be performed by, for example, a circuit designer or a computing device configured to aid in designing a circuit, to generate the model of memory die 100 using various circuit design and simulation tools. Description of features related to resistance, resistors, resistive grids or the like may also be applied to inductance, inductors, inductive grids, or a combination of resistive and inductive components, and vice-versa. The process flow may be applied to a single stack die or a cube with multiple stacks.”) and capacitance information and a current profile (Badrieh: para [0015], “the electrical response of the memory die may be frequency-dependent. Meaning that the resistivity, capacitance, and/or inductance of the memory die—each of which may affect the electrical response of the memory die—may vary depending on the frequency at which the die is operated”; para [0043] “Circuit 300 may include multiple capacitive elements 330 that may be connected between the upper grid 310 and the lower grid 315. Capacitive elements 330 may include elements that are intentionally added to the circuit (such as discrete capacitors, including container capacitors, metal capacitors, complementary metal-oxide-semiconductor (CMOS) capacitors, etc.) to provide capacitance in circuit 300. Capacitive elements 330 may also include other types of elements that may contribute to parasitic capacitance in circuit 300. In some cases, capacitive elements 330 may not be ideal capacitors, and thus may each be modeled by or represented by an RC circuit 335. In some cases, the reactance of capacitive elements 330 may be frequency-dependent; thus, the overall impedance of circuit 300 may also be frequency-dependent. In some cases, full grids of components (e.g., resistive components, inductive components, and/or capacitive components) may be approximated using a frequency-dependent die model, which may model the voltage response across the die for various current stimuli. In some cases, the model may be used to try different capacitor models and/or different resistive/inductive grits to optimize on-die power delivery”; para [0018], “it may be sufficient to determine the electrical response of the die at specific ports of interest on the die, such as at the pads and at some or all of the current sources (e.g., circuitry that draws current) on the die. Thus, in some cases, a simplified simulation model of a memory die may be determined by selecting a subset of the ports on a memory die, applying one or more excitation signals (e.g., alternating
current (AC) signals) to each of the selected ports, and determining an impedance associated with each of the selected ports by simulating or measuring a voltage or current produced at each of the selected ports in response to applying the excitation signal(s)”).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Celik (directed to designing an electronic device) and Badrieh (directed towards in-die resistance and capacitance) and arrived at designing an electronic device including in-die resistance and capacitance. One of ordinary skill in the art would have been motivated to make such a combination because “it may be desirable to develop a simulation model for the die that accurately simulates the electrical response of the die across a range of operating conditions in order to assess and characterize the PDN, predict the voltage drop between pads of the memory die and various components on the memory die, assess package and board designs that include the memory die, and/or predict voltages at the pads of the memory die, for example” (Badrieh: para [0014]).
Additional References Cited
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure and are cited in the attached PTOL-892:
US 8656329 B1: A system and method are provided for generating a programmably implemented model which emulates a power delivery network serving an integrated circuit (IC) core in an electronic system. The system and method generally comprise measures for establishing a power integrity (PI) topology including models for a voltage regulator module that generates at least one predetermined supply voltage level, and for a conductive power rail portion of the power delivery network (PDN). The system and method further comprise measures for interconnecting to the conductive power rail portion model a first behavioral model indicative of the current consumption characteristics of the IC core, and a second behavioral model indicative of the current consumption of an IO interface buffer driving an output signal of the electronic system.
US 20080195363 A1: An analogue signal modelling routine for a hardware description language, wherein an output providing an analogue signal is represented by a value stored in an output variable, an input accepting the analogue signal is represented by a value stored in an input variable, and the routine is arranged to update the value stored in the input variable when the value stored on the output value is changed. The level of an analogue signal can be represented using a floating point number.
Allowable Subject Matter
Claim 4-6 and 10-12 contain allowable subject matter.
The independent claims will be in condition for allowance when the allowable dependent claims are incorporated into the independent claims.
The closest prior art of record, Celik, Ginetti and Badrieh teach a system simulation method, which can evaluate a power delivery network (PDN) or voltage drop of the system through a simple simulation method in the early stage of chip power development, to determine whether the planned/designed printed circuit board, package and chip power models meet the specifications.
However, these references and the remaining prior art of record, alone or in combination, fails to disclose or suggest
(claims 4 and 10)
“determining whether the characteristics of the power delivery network and the voltage drop meet a specification;
in response to the characteristics of the power delivery network and the voltage drop not meeting the specification, generating a second channel model different from the first model;
and performing the simulation to generate the characteristics of the power delivery network and the voltage drop of the system according to the second channel model and the first die information”,
(claims 5 and 11)
“determining whether the characteristics of the power delivery network and the voltage drop meet a specification;
in response to the characteristics of the power delivery network and the voltage drop not meeting the specification, selecting a second combination of the plurality of combinations of printed circuit boards and packages from the database;
selecting a second channel model of the plurality of channel models from the database, wherein the second channel model is generated according to the second combination; and
performing the simulation to generate the characteristics of the power delivery network and the voltage drop of the system according to the second channel model and the first die information”,
(claims 6 and 12)
“determining whether the characteristics of the power delivery network and the voltage drop meet a specification;
in response to the characteristics of the power delivery network and the voltage drop not meeting the specification, determining second die information; and
performing the simulation to generate the characteristics of the power delivery network and the voltage drop of the system according to the first channel model and the second die information”,
in combination with the remaining elements and features of the claimed invention. It is for these reasons that the applicant’s invention defines over the prior art of record.
Conclusion
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/NITHYA J. MOLL/Primary Examiner, Art Unit 2189
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