Prosecution Insights
Last updated: April 19, 2026
Application No. 18/099,123

VISUALIZATION SYSTEM FOR DEBUG OR PERFORMANCE ANALYSIS OF SOC SYSTEMS

Non-Final OA §101
Filed
Jan 19, 2023
Examiner
LIN, KATHERINE Y
Art Unit
2113
Tech Center
2100 — Computer Architecture & Software
Assignee
Nanjing Tenafe Electronic Technology Co. Ltd.
OA Round
4 (Non-Final)
91%
Grant Probability
Favorable
4-5
OA Rounds
2y 5m
To Grant
98%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allow Rate
320 granted / 351 resolved
+36.2% vs TC avg
Moderate +7% lift
Without
With
+7.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
31 currently pending
Career history
382
Total Applications
across all art units

Statute-Specific Performance

§101
23.4%
-16.6% vs TC avg
§103
36.8%
-3.2% vs TC avg
§102
22.1%
-17.9% vs TC avg
§112
6.3%
-33.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 351 resolved cases

Office Action

§101
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claim(s) 1-5, 7-12, 14-22 is/are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The claims fall within at least one of the four categories of patent eligible subject matter. However, the claimed invention is directed to performing steps that fall within the mental process groupings of abstract ideas because they cover concepts performed in the human mind. An analysis of the claims regarding subject matter eligibility follows: Step1: Claim(s) 1-5, 7-12, 14-22 recite a system and a method, therefore satisfying Step 1 of the analysis. Step 2A, Prong 1: Claim(s) 1, 8 recite select[ing], based at least in part on the selection associated with the desired set of visual analysis information, a template from a plurality of available templates; identifying a starting event-based message and an ending event-based message based at least in part on a same value for a unique operation identifier in the starting event-based message and the ending event-based message; and calculating a latency by subtracting a starting timestamp, included in the starting event-based message, from an ending timestamp, included in the ending event-based message, which, under their broadest reasonable interpretation, covers performance of the limitations entirely in the human mind and/or with the aid of pen and paper. Specifically, the steps of select[ing], based at least in part on the selection associated with the desired set of visual analysis information, a template from a plurality of available templates; identifying a starting event-based message and an ending event-based message based at least in part on a same value for a unique operation identifier in the starting event-based message and the ending event-based message; and calculating a latency by subtracting a starting timestamp, included in the starting event-based message, from an ending timestamp, included in the ending event-based message may be practically performed in the human mind using observation, evaluation, and judgement of the visual analysis information and the messages (MPEP 2106.04(a)(2), subsection Ill). For example, “select[ing]” in the context of the claim(s) encompasses a user select[ing], based at least in part on the selection associated with the desired set of visual analysis information, a template from a plurality of available templates; “identifying” in the context of the claim(s) encompasses the user identifying a starting event-based message and an ending event-based message based at least in part on a same value for a unique operation identifier in the starting event-based message and the ending event-based message; and “calculating” in the context of the claim(s) encompasses the user calculating a latency by subtracting a starting timestamp, included in the starting event-based message, from an ending timestamp, included in the ending event-based message. Claim(s) 2-5, 7, 9-12, 14-22 recite further limitations that fall under the judicial exception as recited in claim(s) 1, 8. Each of the further limitations encompass performance of the steps within the human mind. Step 2A, Prong 2: The additional elements recited in claim(s) 1, 8, “an interface,” “a processor,” “a display device,” “a memory,” “SOC,” “receive a selection associated with a desired set of visual analysis information, wherein the desired set of visual analysis information is associated with a system on chip (SOC) that includes a hardware functional module and a firmware functional module that collectively are able to generate a plurality of event-based messages;” “send the selected template to the SOC, wherein at the SOC: the hardware functional module in the SOC is configured as prescribed by the selected template to generate select hardware-reported information; and the firmware functional module in the SOC is configured as prescribed by the selected template to generate select firmware-reported information, wherein after being configured as prescribed by the selected template, the configured hardware functional module and the configured firmware functional module collectively generate a reduced set of event-based messages that excludes at least one event-based message from the plurality of event-based messages;” “receive, from the SOC, reported information, including the select hardware- reported information and the select firmware-reported information;” “generate the desired set of visual analysis information, including by: using the select hardware-reported information and the select firmware- reported information; generating latency-related visual information based at least in part on the latency, wherein the desired set of visual analysis information includes the latency-related visual information;” “display, via a display device, the desired set of visual analysis information, including the latency-related visual information,” do not integrate the judicial exception into a practical application. These limitations are directed to implementing the abstract idea using generic computer components (MPEP 2106.05(f)) and recite mere data gathering and outputting recited at a high level of generality, and thus are insignificant extra-solution activity (MPEP 2106.05(g)). Claim(s) 2-5, 7, 9-12, 14-22 recite further details regarding hardware functional modules, reported information, timestamping. These claims contain no additional elements which would integrate the abstract idea into a practical application. Accordingly, the additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the identified abstract idea. Step 2B: Claim(s) 1, 8 do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed in Step 2A, Prong 2 above, the recitations of “an interface,” “a processor,” “a display device,” “a memory,” “SOC,” “receive a selection associated with a desired set of visual analysis information, wherein the desired set of visual analysis information is associated with a system on chip (SOC) that includes a hardware functional module and a firmware functional module that collectively are able to generate a plurality of event-based messages;” “send the selected template to the SOC, wherein at the SOC: the hardware functional module in the SOC is configured as prescribed by the selected template to generate select hardware-reported information; and the firmware functional module in the SOC is configured as prescribed by the selected template to generate select firmware-reported information, wherein after being configured as prescribed by the selected template, the configured hardware functional module and the configured firmware functional module collectively generate a reduced set of event-based messages that excludes at least one event-based message from the plurality of event-based messages;” “receive, from the SOC, reported information, including the select hardware- reported information and the select firmware-reported information;” “generate the desired set of visual analysis information, including by: using the select hardware-reported information and the select firmware- reported information; generating latency-related visual information based at least in part on the latency, wherein the desired set of visual analysis information includes the latency-related visual information;” “display, via a display device, the desired set of visual analysis information, including the latency-related visual information,” are recited at a high level of generality. These elements amount to receiving or transmitting data using generic computers and are well-understood, routine, conventional activity (MPEP 2106.05(d), subsection II). Regarding claim(s) 2-5, 7, 9-12, 14-22, the additional elements are not sufficient to amount to significantly more than the judicial exception because they simply apply the exception using a generic computer. Therefore, claim(s) 1-5, 7-12, 14-22 recite an abstract idea without significantly more, and are not patent eligible. Response to Remarks Applicant's Remarks have been fully considered but they are not persuasive. Regarding the rejections under 101, the Remarks state, “without the limitations recited by amended claims 1 and 8, it may not be possible for the SOC to generate the appropriate messages that produce the desired set of desired set of visual analysis information while accommodating storage limitations of the system.” However, the examiner respectfully disagrees. Generating a reduced set of event-based messages that excludes at least one event-based message from the plurality of event-based messages is not an improvement to the functioning of a computer or to any other technology or technical field. The claims simply gather diverse data and decide how to best display the information. The Remarks state, “’the invention recited by amended claims 1 and 8 is clearly integrated into a practical application, specifically a visual analysis system to analyze SOC systems.” However, the examiner respectfully disagrees. The claims that simply gather diverse data and decide how to best display the information would not integrate the abstract idea into a practical application. ConclusionAny inquiry concerning this communication or earlier communications from the examiner should be directed to KATHERINE LIN whose telephone number is (571)431-0706. The examiner can normally be reached Monday-Friday; 8 a.m. - 5 p.m. EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bryce Bonzo can be reached at (571) 272-3655. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KATHERINE LIN/Primary Examiner, Art Unit 2113
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Prosecution Timeline

Jan 19, 2023
Application Filed
Jun 29, 2024
Non-Final Rejection — §101
Aug 20, 2024
Interview Requested
Sep 10, 2024
Applicant Interview (Telephonic)
Sep 10, 2024
Examiner Interview Summary
Sep 12, 2024
Response Filed
Jan 13, 2025
Non-Final Rejection — §101
Feb 20, 2025
Interview Requested
Mar 05, 2025
Applicant Interview (Telephonic)
Mar 05, 2025
Examiner Interview Summary
Mar 06, 2025
Response Filed
Mar 22, 2025
Final Rejection — §101
Jun 19, 2025
Request for Continued Examination
Jun 23, 2025
Response after Non-Final Action
Sep 24, 2025
Non-Final Rejection — §101 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

4-5
Expected OA Rounds
91%
Grant Probability
98%
With Interview (+7.1%)
2y 5m
Median Time to Grant
High
PTA Risk
Based on 351 resolved cases by this examiner. Grant probability derived from career allow rate.

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