Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Non-Final Office Action
DETAILED ACTION
Examiner’s Notes
(a) Claim date: 01/20/2023
(b) Priority date: 02/18/2022.
(c) Field: Layout design while considering electromagnetic field and interference.
Claim Rejections - 35 USC 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:A person shall be entitled to a patent unless:(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.Claims 1-4, 7, 10-11, are rejected under 35 U.S.C. 102(a)(1) as being anticipated by the prior art of record Uriu <US 20090249264 A1>.(As to claim 1, 10 and 11, Uriu discloses):1. A pattern generation device comprising [0178: “patterns is designed by the use of the CAD”]:
a memory [0009: “memory”]; and
a processor coupled to the memory, the processor being configured to [0009: “processor as the CPU”]:
generate pattern data corresponding to a pattern of a metal layer provided on a surface of a dielectric layer based on a generation condition [Fig. 13];
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determine whether the generated pattern data satisfies a predetermined condition [0171: “designer of the circuit board” and “values”][Fig. 13, refer to the dotted line block depicting correction feedback loops ];
return to generate the pattern data when it is determined that the predetermined condition is not satisfied [Fig. 13, refer to the dotted line block depicting correction feedback loops] [Para. 178, as highlighted];
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[0178] It is also possible to manufacture an additionally designed circuit board by successively carrying out the circuit board designing method after carrying out the circuit board analyzing method according to this embodiment. The analyzing method according to this embodiment can be performed not only as a partial process of the circuit board designing method, but also as an independent process. In the typical circuit board designing method, basic specifications (function, performance, and the like) as an electronic apparatus are first determined, a circuit (logical circuit diagram) for embodying the specifications is prepared, the resultant logical circuit diagram is repeatedly simulated, the layout including actual elements and wiring patterns is designed by the use of the CAD when there is no problem in the logical circuit diagram, and then a mask is prepared. The analyzing method
according to this embodiment can be carried out as one step in designing the layout. It is also possible to manufacture a circuit board using the mask prepared by the designing method including the analyzing method according to this embodiment.
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calculate a characteristic of the pattern or an element or circuit having the pattern when a high-frequency signal is inputted to a first portion of the pattern and a high- frequency signal is outputted from a second portion of the pattern by performing an electromagnetic field analysis based on the pattern data when it is determined that the predetermined condition is satisfied [0010, 0011, “frequency point increases/decreases”, “calculate the amount of inter-wiring interference by the electromagnetic field analysis”] [Fig. 14, depicting interference impedance with respect to high frequency ranges];
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determine whether the calculated characteristic is within a target range; change the generation condition when it is determined that the calculated characteristic is not within the target range; and return to generate the pattern data after changing the generation condition [Fig. 12: depicting pattern generation process, wherein, the process goes through various steps of design-check and design-update].
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(As to claim 2, Uriu discloses):2. The pattern generation device according to claim 1, wherein the processor changes the generation condition so that the characteristic calculated based on pattern data generated based on the changed generation condition approaches the target range [Fig. 12, here, step S464 is functionally equivalent to approaching design target range.].
(As to claim 3, Uriu discloses):3. The pattern generation device according to claim 1, wherein when it is determined that the predetermined condition is not satisfied, before returning to generate the pattern data, the processor changes the generation condition so that the pattern data generated based on the changed generation condition approaches the predetermined condition [Fig. 12: depicting pattern generation process, wherein, the process goes through various steps of design-check and design-update].
(As to claim 4, Uriu discloses):4. The pattern generation device according to claim 1, wherein when the processor generates the pattern data, the processor generates a plurality of weights respectively associated with a plurality of positions on the surface, and generates the pattern data based on the generated plurality of weights, and wherein the generation condition is a condition for generating the plurality of weight [Fig. 4- 6. Notice that, the pattern data in Fig. 4 is getting some weight as shown in Fig. 5 that are associated with a plurality of positions on the surface. That data is further being analyzed in a matrix from, while given specific weight value to each component, as depicted in Fig. 6].
(As to claim 7, Uriu discloses):7. The pattern generation device according to claim 1, wherein the predetermined condition is that the first portion and the second portion are physically connected via the pattern [Fig. 13. Notice that part 1 and part 2 are physically connected via intermediate pattern].
Allowable Subject Matter
The following claims would be allowable if all rejections/objections cited in this office action (if any) are overcome and rewritten to include all of the limitations of the base claim and any intervening claims.The reason for this allowance is: the claimed subject matter could not have been anticipated or obviated using any prior arts.Allowable claims are: 5-6 and 8-9.
Conclusion
The prior art made of record in the form PTO-892 are not relied upon is considered pertinent to applicant's disclosure.Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.Contact information:Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED ALAM whose telephone number is (571) 270-1507, email address: [mohammed.alam@uspto.gov] and fax number (571) 270-2507. The examiner can normally be reached on 10AM to 4PM (EST), Monday to Friday. If attempts to reach the examiner by telephone are unsuccessful, the Examiner's Supervisor, JACK CHIANG can be reached on (571) 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300./Mohammed Alam/Primary Examiner, Art Unit 2851