DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the application and claims filed 1/20/2023. Claims 1-10 are pending and have been examined. Claims 1-10 are rejected.
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. The present application claims foreign priority to Korean patent application No. KR10-2022-0008843 filed on 1/20/2022.
The examiner acknowledges that a certified copy of Korean patent application No. KR10-2022-0008843 has been retrieved (on 3/09/2023, in Korean). The examiner notes that a translation of Korean patent application No. KR10-2022-0008843 does not appear to have been furnished to-date.
Although a certified copy of the foreign priority application was retrieved, a translation of said application has not yet been made of record in accordance with 37 CFR 1.55. See MPEP §§ 215 and 216. Applicant is reminded of requirements set forth in 37 CFR 1.55(g)(3)-(4) Claim for foreign priority:
“(3) An English language translation of a non-English language foreign application is not required except:
(i) When the application is involved in an interference (see § 41.202 of this chapter) or derivation (see part 42 of this chapter) proceeding;
(ii) When necessary to overcome the date of a reference relied upon by the examiner; or
(iii) When specifically required by the examiner.
(4) If an English language translation of a non-English language foreign application is required, it must be filed together with a statement that the translation of the certified copy is accurate” (emphasis added).
Since an English language translation of Application No. KR10-2022-0008843 has not been made of record to-date, the Examiner notes that prior art references with a filing date or a publication date prior to the instant Application’s filing date of 1/20/2023 are considered applicable prior art references.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(3) because Figures 2B, 3A, 4, 7A and 7B include letters which do not measure at least .32 cm. (1/8 inch) in height (see, e.g., the lowercase characters in FIGs. 2B, 3A, 4 and 6, including Korean text in FIG. 4, and the superscript exponent numbers in FIGs. 7A and 7B). See MPEP 507 (A) and 37 CFR 1.84(p)(3): Numbers, letters, and reference characters must measure at least .32 cm. (1/8 inch) in height.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference characters not mentioned in the description:
402, 403 and 40n (see, e.g., pages 15-17 describing FIG. 4).
The drawings are also objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: 501 (see, e.g., page 17 describing FIG. 5 and stating “a crossbar array feature extractor 501”).
The drawings are further objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “502” has been used to designate both an “output” and a “Crossbar Array feature extractor” in FIG. 5 (see, e.g., FIG. 5 and description of FIG. 5 on page 17 stating “output 502”).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency.
Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
Reference characters 402, 403 and 40n shown in Figure 4 are not described in applicant’s specification (see, e.g., pages 15-17 describing FIG. 4). Appropriate correction is required.
The description of FIG. 5 on page 17 states “a crossbar array feature extractor 501”. However, FIG. 5 depicts “Crossbar Array feature extractor” 502. Appropriate correction is required.
Portions of Equation 1 included in the specification are not legible. For example, Equation 1 on page 15, line 16 is partially illegible. The relevant portion of the specification reads:
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Appropriate correction is required.
On page 19, lines 4-5 and page 20, lines 11-13 of the specification, a reference is referred to: “The RRAM and PS32 cases described herein may be implemented based on 5 the drawing shown in FIG. 4 of Korean Patent No. 10-1991041.” and “In the present application, unlike the aforementioned Korean Patent No. 10-1991041, even though the hardware structure of FIG. 6 is borrowed, the weight and active value are set to have real numbers.” The listing of a reference in the specification is not a proper information disclosure statement. 37 CFR 1.98(b) requires a list of all patents, publications, or other information submitted for consideration by the Office, and MPEP § 609.04(a) states, "the list may not be incorporated into the specification but must be submitted in a separate paper." Therefore, unless the reference has been cited by the examiner on form PTO-892, it has not been considered.
Claim Objections
Claims 1-10 are objected to because of the following informalities:
The preambles of independent claims 1 and 7 both recite “solving circuit equations of a processing element (PE) using a neural network by a graphic processing unit (GPU)”. These recitations are unclear and appear to be missing punctuation or one or more words. In particular, it appears that the recited GPU is used for “solving circuit equations”, but this is unclear in the above-noted recitations. If supported by applicant’s original specification, the examiner suggests that one possible way to address these objections would be to amend “solving circuit equations of a processing element (PE) using a neural network by a graphic processing unit (GPU)” to read “solving, by a graphic processing unit (GPU), circuit equations of a processing element (PE) using a neural network. Appropriate correction is required.
Independent claim 1 recites “performing 3D convolution on each of the virtual cell arrays” and independent claim 7 recites “perform 3D convolution on each of the virtual cell arrays” (see, line 6 of claim 1 and line 7 of claim 7). These recitations are grammatically incorrect and appear to be missing one or more words between performing/perform and “3D convolution”. If supported by the original specification, the examiner suggests that two possible ways to address these objections would be to amend performing/perform “3D convolution on each of the virtual cell arrays” to read performing/perform “a 3D convolution on each of the virtual cell arrays” or performing/perform “one or more 3D convolutions on each of the virtual cell arrays”. Appropriate correction is required.
In claim 1, the word “and” is missing between “performed;” and “solving” in the penultimate and last steps. Appropriate correction is required.
Line 5 of claim 1 recites “a processing element”. Applicant previously introduced “a processing element (PE)” in the preamble of the claim in line 1. As such, the subsequently-recited “a processing element” does not clearly refer to the previously-introduced “processing element (PE)”. For clarity and consistency, it appears the subsequent recitation of “a processing element” in line 5 should recite “the [[a]] processing element” (see, e.g., the recitation of “the processing element” in the last step of the claim. Appropriate correction is required.
The first two lines of claim 5 recite “further comprising solving a circuit equation of the processing element using the output value”. The last step of base claim 1 recites “solving a circuit equation of the processing element using the output value of the virtual cell arrays.” As such, the above-noted recitation in the first limitation of dependent claim 5 does not further limit base claim 1 and is superfluous. Appropriate correction is required.
Claims 2-6 and 8-10 which each depend directly or indirectly from claims 1 and 7, respectively, are objected to based on their respective dependencies from claims 1 and 7.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Independent claims 1 and 7 both “the memory cells of the crossbar array” (see, line 8 of claim 1 and line 9 of claim 7). There is insufficient antecedent basis for “the memory cells” in these claims. No “memory cells” were previously introduced in these claims. Applicant previously introduced plural “virtual cell arrays … each virtual cell array corresponding to a crossbar array circuit” in these claims (see, lines 3-5 of claim 1 and lines 4-6 of claim 7). However, it is unclear if the subsequently-recited “the memory cells” refer to physical memory cells in the previously-introduced “crossbar array circuit”, virtual memory cells in some or all of the previously-introduced “virtual cell arrays”, or to some other physical, hardware, non-virtual “memory cells” (see, e.g., page 14, lines 9-12 of the specification reciting “each array may be composed of virtual memory cells 311. Each of virtual memory cells 311 is mapped to multiple filters whose channels represent features of physical memory cells, and the entire array may implement a virtual crossbar array.”). For the purposes of determining patent eligibility and comparison with the prior art, “the memory cells of the crossbar array” have been interpreted as any physical memory cells of the previously-introduced “crossbar array circuit”. Appropriate correction is required.
Independent claims 1 and 7 both “the output value of the virtual cell arrays” (see, the last two lines of claims 1 and 7). There is insufficient antecedent basis for “the output value of the virtual cell arrays” in these claims. No “output value” of the virtual cell arrays previously introduced in these claims. For the purposes of determining patent eligibility and comparison with the prior art, “the output value of the virtual cell arrays” has been interpreted as any output value of the previously-introduced “virtual cell arrays”. Appropriate correction is required.
Claim 2 recites “the memory cell” in line 1. There is insufficient antecedent basis for “the memory cell” in this claim. No singular “memory cell” was previously introduced in this claim, or in its base claim, claim 1. Applicant previously introduced plural “memory cells of the crossbar array” in claim 1. For examination purposes, “the memory cell” has been interpreted as any one of the previously-introduced “memory cells of the crossbar array”. Appropriate correction is required.
Claims 3 and 8 both recite “wherein the parameter of the memory cell comprises parameters which are set as variables from parameters of the conductance of the memory element of the memory cell, the voltage applied to the memory cell, the threshold voltage of the memory cell, and the width/length ratio of the transistor of the memory cell.” As discussed below, these recitations include multiple terms which lack antecedent basis.
First, there is insufficient antecedent basis for “the parameter of the memory cell” in these claims. No singular “parameter of the memory cell” was previously introduced in these claims, or in their respective base claims, claims 1 and 7. Applicant previously introduced plural “parameters of the memory cells of the crossbar array” in claims 1 and 7. For examination purposes, “the parameter of the memory cell” has been interpreted as any one of the previously-introduced “the parameters of the memory cells of the crossbar array”. Appropriate correction is required.
Second, there is insufficient antecedent basis for “the memory cell” in these claims. No singular “memory cell” was previously introduced in these claims, or in their respective base claims, claims 1 and 7. Applicant previously introduced plural “memory cells of the crossbar array” in claims 1 and 7. For examination purposes, “the memory cell” has been interpreted as any one of the previously-introduced “memory cells of the crossbar array”. Appropriate correction is required.
Lastly, there is insufficient antecedent basis for “the conductance of the memory element of the memory cell, the voltage applied to the memory cell, the threshold voltage of the memory cell, and the width/length ratio of the transistor of the memory cell” in these claims. No “conductance”, no “memory element of the memory cell” no “voltage applied to the memory cell, no “threshold voltage of the memory cell”, no “transistor of the memory cell” and no “width/length ratio of the transistor of the memory cell” were previously introduced in these claims, or in their respective base claims, claims 1 and 7. For examination purposes, recitations of “the conductance of the memory element of the memory cell, the voltage applied to the memory cell, the threshold voltage of the memory cell, and the width/length ratio of the transistor of the memory cell” have been interpreted as any conductance of any memory element of a memory cell, any voltage applied to the memory cell, any threshold voltage of the memory cell, and any width/length ratio of any transistor of the memory cell. Appropriate correction is required.
Also, claims 2-6 and 8-10 which depend directly or indirectly from claims 1 and 7, respectively, are rejected under 35 U.S.C. 112(b) as being indefinite under the same rationale as claims 1 and 7.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by non-patent literature Lees, et al. ("SEMULATOR: Emulating the Dynamics of Crossbar Array-based Analog Neural System with Regression Neural Networks." arXiv preprint arXiv:2101.07864 (19 Jan 2021). hereinafter “Lees”). Although Lees was co-authored by “Chaeun Lees and Seyoung Kim” (see, Lees, page 1), examiner notes a similarity between the name of co-author “Chaeun Lees” and the inventor of the instant application, Lee, Chaeun. However, even assuming arguendo that the applied Lees reference has a common co-author with the instant application, Lees was published on 1/19/2021 and this date is more than one year before the earliest effective filing date of this application, i.e., 1/20/20221. Therefore, Lees constitutes prior art under 35 U.S.C. 102(a)(1). Further, even if Lees reference is deemed to have one common co-author/inventor with the instant application, the 35 USC § 102(b)(1)(A) grace period exception does not apply because the reference was co-authored by Seyoung Kim, who is not named as an inventor of the instant application. See MPEP § 2153.01(a): “If ... the application names fewer joint inventors than a publication (e.g., the application names as joint inventors A and B, and the publication names as authors A, B and C), it would not be readily apparent from the publication that it is by the inventor (i.e., the inventive entity) or a joint inventor and the publication would be treated as prior art under AIA 35 U.S.C. 102(a)(1).”
With respect to claim 1, Lees discloses the invention as claimed including a method for solving circuit equations of a processing element (PE) using a neural network by a graphic processing unit (GPU) (see, e.g., pages 1-2, Sect. 1, “make use of machine learning frameworks which are run on GPU environment [i.e., using a GPU] … a methodology and neural network architecture for emulating the analog computing block … includes feature extractors that fit with crossbar array architecture and circuit equation solver for extracted features of crossbar arrays (memory units) and circuit parameters of peripheral circuits (computing units)” [i.e., method for solving circuit equations of circuits/computing units/processing elements using a neural network]), the method comprising:
forming M aligned virtual cell arrays in the neural network, wherein the cell arrays have a height value N and a width value O (see, e.g., FIG. 3, reproduced below – depicting “The architecture of Conv4Xbar” [3D convolution crossbar] where “Input feature maps has N depths which corresponds to the number of total tiles and C0 channels whose values are features of a cell in the crossbar array” and a number M of tiles/virtual cell arrays, pages 3-4, Sect. 3.2, “The neural network to emulate the analog computation block is mainly composed of two parts: Crossbar array feature extractor and circuit equation solver. … In the crossbar array, the behavior of each cell is mainly determined by the features of the cell”, “the architecture of crossbar array has structural and physical similarity with the convolutional neural network (CNN). At the first layer, the unit size filters which has unit width” and page 9, Sect. A, “kernel_size=(D,H,W), stride_size=(D,H,W) … where D,H, and W stands for depth, height, and width Computing Blocks Neural Network Architecture RRAM+PS32 Conv3d(2,16,(1,1,1),(1,1,1))” [i.e., form a number M of emulated/virtual cell arrays in the neural network having a height/depth value N and width value of O]), each virtual cell array corresponding to a crossbar array circuit included in a processing element (see, e.g., page 2, Sects. 1 and 3.1, “emulating analog computing blocks includes feature extractors that fit with crossbar array architecture and circuit equation solver for extracted features of crossbar arrays (memory units) and circuit parameters of peripheral circuits (computing units).”, “emulating the response of circuits using crossbar array by neural networks. As shown in Figure 1, general circuit simulators builds circuit equations and find solutions” [i.e., each emulated/simulated/virtual cell array corresponds to a crossbar array circuit included in a processing element/computing unit]);
performing 3D convolution on each of the virtual cell arrays until the height value N of each of the virtual cell arrays becomes 1 (see, e.g., FIG. 3 – reproduced below, depicting “The architecture of Conv4Xbar [3D convolution crossbar] … Input feature maps has N depths … of a cell in the crossbar array” where 3D convolutions are performed on cell arrays until the height/depth value N of the each virtual cell is 1, page 4, Sect. 3.2, “we adopt 3D convolutional neural networks (3D-CNN) whose depth is 1” and page 9, Sect. A, “Conv3d(in_channels, out_channels, kernel_size=(D,H,W), stride_size=(D,H,W) … where D,H, and W stands for depth, height, and width Computing Blocks Neural Network Architecture RRAM+PS32 Conv3d(2,16,(1,1,1),(1,1,1))” [i.e., perform 3D convolution/Conv3d on the virtual cell arrays until the depth and height value N of each array becomes 1]);
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Lees, FIG. 3
inputting parameters of the memory cells of the crossbar array2 to each of the virtual cell arrays in which the three-dimensional convolution is performed (see, e.g., FIG. 3, reproduced above, showing “The architecture of Conv4Xbar” [3D convolution crossbar] where “Input feature maps has N depths … and C0 channels whose values are features of a cell in the crossbar array such as resistance, applied voltage, and so on.” and Table 1 – showing that “Inputs have four axes, each of whom corresponds to (hardware parameters, tile, row address, column address).”, page 2, Sect. 1, “memory units have thousands of input parameters … feature extractors that fit with crossbar array architecture and circuit equation solver for extracted features of crossbar arrays (memory units) and circuit parameters” and pages 3-4, sect. 3.2, “In the crossbar array, the behavior of each cell is mainly determined by the features of the cell such as applied voltage to the cell and the conductance of memory device in the cell … we adopt 3D convolutional neural networks (3D-CNN) … We denote this type of neural networks as Conv4Xbar as shown in Figure 3. … The filters are trained scanning through all cells” [i.e., inputting parameters of the memory units/cells of the Xbar/crossbar array to the emulated/virtual cell crossbar/Xbar arrays where the 3D convolution is performed]);
solving a circuit equation of the processing element using the output value of the virtual cell arrays3 (see, e.g., FIG. 2 – depicting “Circuit Equation Solver” that uses the output values from a “Crossbar Array Feature Extractor” and page 3, Sect. 3.2, “The neural network to emulate the analog computation block is mainly composed of two parts: Crossbar array feature extractor and circuit equation solver. Figure 2 shows the schematic of our proposed architecture for SEMULATOR. The extracted hidden features and features of analog computing units which in general accumulates the current from analog memory units are concatenated. The concatenated features are interpreted as boundary conditions for circuit differential equations … and so the circuit equation solver is expected to solve differential equations … we use FCNN or Neural ODE [18] as circuit equation solvers.” [i.e., solve a circuit equation of the PE using the output of the emulated/virtual cell crossbar arrays]).
Regarding claim 2, as discussed above, Lees discloses the method of claim 1.
Lees further discloses wherein the memory cell4 consists of one resistor memory and one transistor, one resistor memory and one selector5, or one resistor memory (see, e.g., Tables 1 and 2, showing “Computing Blocks” consisting of “RRAM” and FIG. 4 – depicting “Train and test loss of RRAM32+PS32 case.” [i.e., resistive random access memory - a resistor memory] and page 4, Sect. 3.2, “According to the choice of a cell, the features of a cell are differed [i.e. a selector to make a choice of the memory cell]. For instance, 1R cell [19] has two features, applied voltage to the cell and the conductance of the cell, T1R cell [19] has additional 1 transistor whose features such as threshold voltage and W/L ratio” [i.e., and one transistor] and page 5, Sect. 4.2, “Table 1 shows the experimental results for various analog computing blocks with SEMULATOR. We use SPYCE [23] to generate data for SEMULATOR. RRAM+PS32 use 1T1R cell as analog memory units and customized analog circuit” [i.e., the memory cell/unit includes a resistor memory/RRAM and one transistor in the 1T1R cell, the RRAM resistor memory and one selector to make a cell choice, or one resistor memory/RRAM]).
Regarding claim 6, as discussed above, Lees discloses the method of claim 1.
Lees further discloses wherein the 3D convolution is performed over M arrays (see, e.g., FIG. 3 – reproduced above, depicting “The architecture of Conv4Xbar” where “Input feature maps has N depths which corresponds to the number of total tiles and C0 channels whose values are features of a cell in the crossbar array” and showing a number M of tiles/arrays, and pages 2-3, Sect. 3.1, “SEMULATOR aims at emulating the response of circuits using crossbar array by neural networks … Crossbar arrays of analog memory units are linearly approximated”, “emulate computation or memory units such as logic gates and the non-linear factor in crossbar arrays.” and page 4, Sect. 3.2, “we adopt 3D convolutional neural networks (3D-CNN) … We denote this type of neural networks as Conv4Xbar as shown in Figure 3.” [i.e., a 3D convolution performed over a number M of tiles/arrays]).
With respect to independent claim 7, claim 7 is substantially similar to claim 1 and therefore is rejected on the same ground as claim 1, discussed above. In particular, claim 7 is a device claim that performs operations that correspond to the method steps of claim 1.
In addition, Lees further discloses a device for solving circuit equations of a processing element (PE) using a neural network by a graphic processing unit (GPU), wherein the graphic processing unit is configured (see, e.g., pages 1-2, Sect. 1, “make use of machine learning frameworks which are run on GPU environment [i.e., by/using a GPU] … neural network architecture for emulating the analog computing block … includes feature extractors that fit with crossbar array architecture and circuit equation solver for extracted features of crossbar arrays (memory units) and circuit parameters of peripheral circuits (computing units)” [i.e., architecture and device for solving circuit equations of circuits/computing units/processing elements using a neural network]).
Regarding claims 3 and 8, as discussed above, Lees discloses the method of claim 1 and the device of claim 7.
Lees further discloses wherein the parameter of the memory cell comprises parameters which are set as variables from parameters of the conductance of the memory element of the memory cell, the voltage applied to the memory cell, the threshold voltage of the memory cell, and the width/length ratio of the transistor of the memory cell6 (see, e.g., page 4, Sect. 3.2, “According to the choice of a cell, the features of a cell are differed. For instance, 1R cell [19] has two features, applied voltage to the cell and the conductance of the cell, T1R cell [19] has additional 1 transistor whose features such as threshold voltage and W/L ratio” [i.e., memory cell parameter includes variables of conductance, applied voltage, threshold voltage and W/L width/length ratio of a transistor of the cell]).
Regarding claims 4 and 9, as discussed above, Lees discloses the method of claim 1 and the device of claim 7.
Lees further discloses wherein the processing element further comprises peripheral circuitry and wherein the method further comprises solving a circuit equation of the processing element using the output value and circuit characteristics of the peripheral circuit (see, e.g., FIG. 2 – depicting “Circuit Equation Solver” that solves a circuit equation using the output values from a “Crossbar Array Feature Extractor” and “Peripheral Circuit Features” [i.e., characteristics of the peripheral circuit] and pages 1-2, Sect. 1, “machine learning frameworks which are run on GPU environment. … The neural network architecture for the purpose of emulating analog computing blocks includes feature extractors that fit with crossbar array architecture and circuit equation solver for extracted features of crossbar arrays (memory units) and circuit parameters of peripheral circuits (computing units).” and page 3, Sect. 3.2, “Figure 2 shows the schematic of our proposed architecture for SEMULATOR. The extracted hidden features and features of analog computing units which in general accumulates the current from analog memory units are concatenated. The concatenated features are interpreted as boundary conditions for circuit differential equations … the circuit equation solver is expected to solve differential equations … we use FCNN or Neural ODE [18] as circuit equation solvers.” [i.e., the processing element includes peripheral circuits/circuitry and the method/GPU solves a circuit equation using output and circuit characteristics of the peripheral circuit]).
Regarding claim 5, as discussed above, Lees discloses the method of claim 4.
Lees further discloses solving a circuit equation of the processing element using the output value7, wherein circuit characteristics of the peripheral circuit comprise solving the circuit equation using a Fully Connected Neural Network (FCNN) or Neural Ordinary Differential Equation (ODE) (see, e.g., FIG. 2 – depicting “Circuit Equation Solver” that uses the output values from a “Crossbar Array Feature Extractor” and “Peripheral Circuit Features” and page 3, Sect. 3.2, “The neural network to emulate the analog computation block is mainly composed of two parts: Crossbar array feature extractor and circuit equation solver. Figure 2 shows the schematic of our proposed architecture for SEMULATOR. The extracted hidden features and features of analog computing units which in general accumulates the current from analog memory units are concatenated. The concatenated features are interpreted as boundary conditions for circuit differential equations … and so the circuit equation solver is expected to solve differential equations … we use FCNN or Neural ODE [18] as circuit equation solvers.” [i.e., solving a circuit equation of the PE using the output of the emulated/virtual cell crossbar arrays where circuit characteristics of the peripheral circuit include solving the circuit equation using a Fully Connected Neural Network/FCNN or Neural Ordinary Differential Equation/ODE]).
Regarding claim 10, as discussed above, Lees discloses the device of claim 7.
Lees further discloses wherein the graphic processing unit is configured to solve the circuit equation using a Fully Connected Neural Network (FCNN) or Neural Ordinary Differential Equation (ODE) (see, e.g., page 1, Sect. 1, “machine learning frameworks which are run on GPU environment.” and page 3, Sect. 3.2, “The neural network to emulate the analog computation block is mainly composed of two parts: Crossbar array feature extractor and circuit equation solver. Figure 2 shows the schematic of our proposed architecture for SEMULATOR. The extracted hidden features and features of analog computing units which in general accumulates the current from analog memory units are concatenated. The concatenated features are interpreted as boundary conditions for circuit differential equations … and so the circuit equation solver is expected to solve differential equations … we use FCNN or Neural ODE [18] as circuit equation solvers.” [i.e., the GPU solves the circuit equation using a Fully Connected Neural Network/FCNN or Neural Ordinary Differential Equation/ODE]).
Conclusion
The prior art made of record, listed on form PTO-892, and not relied upon, is considered pertinent to applicant's disclosure.
The references listed on form PTO-892 are generally related to techniques, methods, devices and systems using arrays, such as crossbar arrays, of processing elements (PEs), units, or nodes for neural network operations such as convolutions.
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line no(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application.
When responding to this office action, Applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of the art disclosed by the reference cited or the objections made. He or she must also show how the amendments avoid such references or objections See 37 CFR 1.111 (c).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RANDY K BALDWIN whose telephone number is (571)270-5222. The examiner can normally be reached on Mon - Fri 9:00-6:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kamran Afshar can be reached on 571-272-7796. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/RANDALL K. BALDWIN/Primary Examiner, Art Unit 2125
1 As noted above in the Priority section, this is the filing date of the priority Korean application, and no English language translation of the Korean application has been made of record to-date. As also noted above, the instant application was filed on 1/20/2023.
2 As indicated above in the section 112(b) rejections of this claim, “the memory cells of the crossbar array” have been interpreted as any physical memory cells of the previously-introduced “crossbar array circuit”.
3 As indicated above in the section 112(b) rejections of this claim, “the output value of the virtual cell arrays” has been interpreted as any output value of the previously-introduced “virtual cell arrays”.
4 As indicated in the section 112(b) rejection of this claim above, the memory cell” has been interpreted as any one of the previously-introduced “memory cells of the crossbar array”.
5 Aside from merely repeating the claim language in lines 8-10 of page 3, applicant’s specification does not mention, let alone define what is meant by “one selector”. Therefore, under the broadest reasonable interpretation (BRI), in view of the specification, “one selector” is any component of a memory cell usable for a choice, selection or configuration.
6 As indicated in the section 112(b) rejections of these claims above, “the conductance of the memory element of the memory cell, the voltage applied to the memory cell, the threshold voltage of the memory cell, and the width/length ratio of the transistor of the memory cell” have been interpreted as any conductance of any memory element of a memory cell, any voltage applied to the memory cell, any threshold voltage of the memory cell, and any width/length ratio of any transistor of the memory cell.
7 As noted in the objection to this claim above, this limitation was already recited in the last step of base claim 1.