DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/24/2023 and 09/23/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description:
S6 in Fig. 9
4300 in Fig. 10
341-344, 441-444 and 44 in Fig. 16
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: Extraction logic in claims 9-11
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
Extraction logic (claims 9-11): See paragraph [0044] the extraction logic is implemented by a barrel shifter
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “the mixed-precision multiplication circuit outputs a result according to the product” in line 10. This limitation is unclear because it merely states a function (that the mixed-precision multiplication circuit must somehow output a result according to the product) that is not performed by any structure recited in the claim. The recited function does not follow from the structure recited in the claim, i.e., the subset selector and the mantissa multiplier, so it is unclear whether the function requires some other structure or is simply a result of operating the system in a certain manner. Further clarification is required. Perhaps Applicant may want to include the features of claim 10 into claim 1 to clarify that an extraction logic outputs the result according to the product as disclosed in Fig. 10 and paragraph [0051]. Claims 2-10 inherit the same deficiency as claim 1 by reason of dependence.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Detrey et al. (NPL – “Floating-Point Trigonometric Functions for FPGAs”), hereinafter Detrey, in view of Brightman et al. (US 5042001 A), hereinafter Brightman.
Regarding claim 1, Detrey teaches a mixed-precision multiplication circuit that computes according to a first operand and a second operand, wherein the first operand comprises an exponent and a mantissa, and the mixed- precision multiplication circuit comprises (Detrey Figs. 1 and 4; page 30 left column bottom; page 31 left column top; first operand –
x
; second operand -
π
4
; exponent -
E
x
; mantissa -
F
x
):
a subset selector configured to store the second operand and receive the exponent, wherein the subset selector outputs a selected subset (Detrey Fig. 4 and page 30 left column top; subset selector – exponent adder, shifter and multiplexer on top left of Fig. 4; selected subset -
3
w
F
); and
a mantissa multiplier coupled to the subset selector for receiving a multiplicand associated with the selected subset, and configured to receive the mantissa, wherein the mantissa multiplier generates a product by performing a multiplication according to the multiplicand and the mantissa, and the mixed-precision multiplication circuit outputs a result according to the product (Detrey Fig. 4 and page 30 left column top; page 30 right col bottom to page 31 left column top; mantissa multiplier – multiplier; multiplicand – output of the multiplexer; product – output of the multiplier; result - output of the multiplier or y represented by
E
y
,
M
y
or Y).
Detrey does not explicitly teach a subset selector configured to store the second operand and receive the exponent, wherein the subset selector outputs a selected subset from a plurality of subsets according to the exponent, with the plurality of subsets representing the second operand.
However, on the same field of endeavor, Brightman discloses a multiplication circuit comprising a subset selector configured to store an operand, wherein the subset selector outputs a selected subset from a plurality of subsets, wherein the plurality of subsets representing the operand (Figs. 2 and 5; col 7 lines 32-33 “ the C-latch 44 generally contains the multiplier of a multiplication operation”; col 10 lines 6-8 “FIG. 5 is a tabular description of MUX 62. MUX 62 selects from five different combinations of the C-latch 44”; plurality of subsets - five different combinations of the C-latch 44).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Detrey using Brightman and configure the subset selector to include a plurality of subsets representing the operand using different bit combinations of the operand and configure the multiplexer to select the subset based on the exponent in order to select portion of the second operand to drive the multiplier (Brightman col 9 line 60-63). Furthermore, as discussed in page 31 left column top of Detrey, only
3
w
F
bits of the
2
w
E
-
1
+
3
w
F
bits of the second operand are used by the multiplier. Therefore, it would be obvious to generate of a plurality of subsets of the second operand and selecting the appropriate subset to extract the
3
w
F
bits from the
2
w
E
-
1
+
3
w
F
bits that is needed by the multiplier.
Therefore, the combination of Detrey as modified in view of Brightman teaches a subset selector configured to store the second operand and receive the exponent, wherein the subset selector outputs a selected subset from a plurality of subsets according to the exponent, with the plurality of subsets representing the second operand.
Regarding claim 2, Detrey as modified in view of Brightman teaches all the limitations of claim 1 as stated above. Further, Detrey as modified in view of Brightman teaches wherein the plurality of subsets comprises a first subset and a second subset, the first subset comprises a first portion serving as a second portion of the second subset (Brightman Fig. 5; first subset – first quadrant; second subset – second (20 bit) quadrant; first portion and/or second portion – c[17]). The motivation to combine is the same as claim 1.
Regarding claim 3, Detrey as modified in view of Brightman teaches all the limitations of claim 1 as stated above. Further, Detrey as modified in view of Brightman teaches wherein the plurality of subsets comprises a first subset and a second subset, the first subset comprises a first portion, the second subset comprises a second portion, and a bit pattern of the first portion is identical to a bit pattern of the second portion (Brightman Fig. 5; first subset – first quadrant; second subset – second (20 bit) quadrant; first portion and/or second portion – c[17]). The motivation to combine is the same as claim 1.
Regarding claim 10, Detrey as modified in view of Brightman teaches all the limitations of claim 1 as stated above. Further, Detrey as modified in view of Brightman teaches further comprising an extraction logic coupled to the mantissa multiplier for receiving the product, wherein the product comprises a left portion, a right portion, and a result portion between the left portion and the right portion, and the extraction logic shifts the left portion and the right portion out to extract the result portion as the result (Detrey Fig. 4 and page 30 right col middle to page 31 left col top; page 31 right col bottom to page 32 left col top; extraction logic – logic downstream of the multiplier; the logic includes a right shifter and a left shifter to shift left and right to extract the output Y (
w
F
+ g bits)).
Allowable Subject Matter
Claims 11-12 are allowed.
Claims 4-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and if rewritten to overcome the 35 U.S.C. 112(b) rejection discussed above.
The following is a statement of reasons for the indication of allowable subject matter:
Detrey is the closet prior art found. Detrey discloses a multiplication (argument reduction) circuit for performing a multiplication operation of a first floating-point input operand x and a second operand
π
4
as shown in Fig. 4 comprising of a subset selector including an exponent adder, a shifter circuit and a multiplexer for extracting a subset of bits of the second operand as a multiplicand; a multiplier for generating a product of the multiplicand and a mantissa of the operand x; and a post-processing logic circuit for extracting a portion of the output result based on the product. However, as shown in Fig. 4, there is no additional circuit extraction logic (i.e., shifter) between the multiplexer and the multiplier. Therefore, Detrey fails to explicitly teach or suggest “further comprising an extraction logic coupled between the subset selector and the mantissa multiplier for receiving the selected subset, wherein the extraction logic extracts a portion as the multiplicand from the selected subset” as recited in claim 9. Furthermore, Detrey fails to explicitly teach or suggest the second operand
π
4
is partitioned into a plurality of subsets “wherein a bit width of each of the plurality of subsets comprises a base width and an overlap width, the base width is associated with the exponent of the first operand and a quantity of the plurality of subsets, and the overlap width is a bit width of the first portion or a bit width of the second portion” as recited in claim 4; and “wherein: the second operand is partitioned into a plurality of subsets, and the mantissa multiple is partitioned into a plurality of reference subsets, each of the plurality of subsets comprises a plurality of groups, and each of the plurality of reference subsets comprises a plurality of reference groups, each of the plurality of groups is a portion of the second operand shifted in an offset, each of the plurality of reference groups is a portion of the mantissa multiple shifted in a reference offset, the offset adopted in each of the plurality of groups is different, the reference offset adopted in each of the plurality of reference groups is different, the partial product selector selects a desired subset from the plurality of subsets and selects a desired reference subset from the plurality of reference subsets according to the exponent” as recited in claim 12. Furthermore, as shown in Fig. 4 of Detrey, the subset selection/extraction is performed before the multiplication operation. Therefore, Detrey fails to explicitly teach or suggest “a subset selector coupled to the mantissa multiplier for receiving the product, wherein the subset selector outputs a selected subset from a plurality of subsets according to the exponent, and each of the plurality of subsets representing a part of the product; and an extraction logic coupled to the subset selector for receiving the selected subset, wherein the extraction logic extracts a portion as the result from the selected subset” as recited in claim 11.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ng et al. (NPL – “Argument Reduction for Huge Arguments: Good to the Last Bit”) related to extracting the subset B of an operand
2
π
needed to perform a multiplication operation of y = x(
2
π
) using y = xB as part of an argument reduction operation. Ng is cited in the IDS submitted on 01/24/2023.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlo Waje whose telephone number is (571)272-5767. The examiner can normally be reached 9:00-6:00 M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Trujillo can be reached at (571) 272-3677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Carlo Waje/Examiner, Art Unit 2151 (571)272-5767
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