DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities. Paragraph [0016] references figure 7A, but it appears it should reference figure 7B.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4, and 8-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 line 5 recites a “direct digital synthesizer”. It is unclear whether the direct digital synthesizer recited in claim 4 is the same direct digital synthesizer recited in claim 1 or different. For purposes of examination, Examiner interprets as the same.
Claim 8 line 11 recites a “direct digital synthesizer”. It is unclear whether the direct digital synthesizer recited in line 11 is the same direct digital synthesizer recited in claim 8 line 5 or different. For purposes of examination, Examiner interprets as the same. Claims 9-12 inherit the same deficiency as claim 8 based on dependence.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 13-15, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 7576616 B2 Iwasaki (hereinafter “Iwasaki”).
Regarding claim 13, Iwasaki teaches the following:
a first direct digital synthesizer (fig 1 100a);
a second direct digital synthesizer (fig 1 100b); and
a controller comprising a memory that stores instructions and a processor that executes the instructions, wherein the instructions when executed by the processor (fig 1 200 DDS controlling section and 300 computer section, wherein CPU comprises a processor that executes instructions), cause the controller to:
trigger the first direct digital synthesizer to transmit a first signal based on a trigger and trigger the second direct digital synthesizer to transmit a second signal based on the trigger (fig 1 trigger from 200 to DDS 100a and 100b, col 4 lie 53-56);
measure a residual timing alignment mismatch between the first signal and the second signal (col 4 line 63-col 5 line 8, col 5 line 47-col 6 line 9);
set the first direct digital synthesizer to determine a first phase preset value for a selected frequency of a periodic signal and a first time offset for a time specified by a controlling event so that the first direct digital synthesizer is aligned with the second direct digital synthesizer using the first time offset based on measuring the residual time alignment mismatch between the first signal and the second signal (col 5 line 47- col 6 line 7 line 45, fig 5A-E); and
set the second direct digital synthesizer to determine a second phase preset value for the selected frequency of the periodic signal and a second time offset for the time specified by the controlling event so that the second direct digital synthesizer is aligned with the first direct digital synthesizer using the second time offset based on measuring the residual time alignment mismatch between the first signal and the second signal (col 5 line 47- col 6 line 7 line 45, fig 5A-E).
Regarding claim 14, in addition to the teachings addressed in the claim 13 analysis, Iwasaki teaches the following:
provide a common frequency to a first phase preset calculator of the first direct digital synthesizer and to a second phase preset calculator of the second direct digital synthesizer such that the first direct digital synthesizer determines the first phase preset value for the first signal with reference to the common frequency and such that the second direct digital synthesizer determines the second phase preset value for the second signal with reference to the common frequency (col 6 line 17-40, common frequency f1 are sent from the computer section to each DDS and phase preset determined therefrom also shown in fig 5A-E, internal register and phase accumulator of each respective DDS for first and second phase present calculator).
Regarding claim 15, in addition to the teachings addressed in the claim 14 analysis, Iwasaki teaches the following:
provide a first baseband delay to the first phase preset calculator of the first direct digital synthesizer to determine the first phase preset value for the first signal with reference to the common frequency (col 4 line 63- col 5 line 8, phase change request); and
provide a second baseband delay to the second phase preset calculator of the second direct digital synthesizer to determine the second phase preset value for the second signal with reference to the common frequency (col 4 line 63- col 5 line 8, phase change request).
Regarding claim 19, in addition to the teachings addressed in the claim 13 analysis, Iwasaki teaches the following:
align the first direct digital synthesizer and the second direct digital synthesizer across a bandwidth that includes the first signal and the second signal using the second time offset based on measuring the residual timing alignment mismatch between the first signal and the second signal such that the second direct digital synthesizer is set to compensate a phase of the second signal using the second phase preset value for the selected frequency of the periodic signal and the second time offset (col 5 line 47- col 6 line 7 line 45, fig 5A-E).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, and 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over US 9520831 B1 Foster et al., (hereinafter “Foster”) in view of Iwasaki.
Regarding claim 1, Foster teaches the following:
a direct digital synthesizer which transmits a signal (abstract, fig 1 figure 1 output for transmits a signal), comprising:
a phase increment calculator configured to determine a phase increment for a selected frequency (col 3 line 36-44, fig 1 phase increment calculator 110);
a phase accumulator configured to accumulate the phase increment over time and provide an accumulated phase value (col 5 line 18-21, fig 1 phase accumulator 130);
a phase-to-amplitude converter (PAC) configured to convert the accumulated phase value to a periodic signal having the selected frequency (col 5 line 42-50, fig 1 PAC 140); and
a phase preset calculator configured to determine a phase preset value for the selected frequency of the periodic signal and a provided time for a time specified by a controlling event (col 4 line 1-7, fig 1 phase preset calculator 120).
Foster discloses providing a phase preset value at any given time (col 4 line 10-42), but does not explicitly disclose wherein the time provided is a time offset, wherein the direct digital synthesizer is aligned with another direct digital synthesizer using the time offset based on measurements of a residual time alignment mismatch between the signal and another signal transmitted by the other direct digital synthesizer.
However, in the same field of endeavor Iwasaki discloses an apparatus similar to Foster comprising direct digital synthesis (DDS), wherein the apparatus comprises multiple DDS and control thereof with each DDS having the same internal structure (abstract, fig 1,col 4 line 4-45). Iwasaki further discloses providing a time offset, wherein the direct digital synthesizer is aligned with another direct digital synthesizer using the time offset based on measurements of a residual time alignment mismatch between the signal and another signal transmitted by the other direct digital synthesizer (col 4 line 53 – col 5 line 8, the DDS controlling section (fig 1 200) outputs a change trigger signal to its respective DDS at a timing considering the latency of the respective DDS, wherein the latency of the respective DDS is due to its pipeline delay and so forth, col 2 line 33-37, the phase controlling apparatus includes a clock signal generating section that generates a clock signal to each section of the phase controlling apparatus and each of the plurality of signal sources which are operated based on the clock signal, col 5 line 47-col 6 line 9, fig 3, fig 4,the register 231a of figure 4 stores a UT1inidactin update timing of DDS 100a, and DDS 100b, and triggering for matching).
It would have been obvious to one of ordinary skill in the art before the effective filing date to substitute Foster’s single DDS for each of the DDS of Iwasaki and to use the DDS controller and clock generator and computer of Iwasaki to match the triggering of multiple DDS. It would have been obvious to achieve the benefit of controlling the timing and phase of multiple DDS (abstract, col 1 line 14-28).
Regarding claim 2, Foster in view of Iwasaki teach the claim 1 limitations. Iwasaki further discloses a common frequency and determining a phase present value for the signal with reference to the common frequency (col 6 line 17-40, common frequency f1 are sent from the computer section to each DDS and phase preset determined therefrom also shown in fig 5A-E).
It would have been obvious to one of ordinary skill in the art before the effective filing date to use Iwasaki’s phase controlling section within Foster’s phase preset calculator to receive the common frequency and determine the phase preset value as in Iwasaki. The motivation to combine provided with respect to claim 1 applies equally to claim 2.
Regarding claim 3, Foster in view of Iwasaki teach the claim 2 limitations. Iwasaki further discloses a baseband delay and determining a phase preset value with reference to the baseband delay (col 4 line 63- col 5 line 8, phase change request).
It would have been obvious to one of ordinary skill in the art before the effective filing date to use Iwasaki’s phase controlling section within Foster’s phase preset calculator to receive the baseband delay and determine a phase present value with reference to the baseband delay. The motivation to combine provided with respect to claim 1 applies equally to claim 2.
Regarding claim 5, Foster teaches the following:
a first direct digital synthesizer which transmits a signal (abstract, fig 1 figure 1 output for transmits a signal), and comprising
a first phase increment calculator configured to determine a first phase increment for a selected frequency (col 3 line 36-44, fig 1 phase increment calculator 110);
a first phase accumulator configured to accumulate the first phase increment over time and provide a first accumulated phase value (col 5 line 18-21, fig 1 phase accumulator 130);
a first phase-to-amplitude converter (PAC) configured to convert the first accumulated phase value to a first periodic signal having the selected frequency (col 5 line 42-50, fig 1 PAC 140); and
a first phase preset calculator configured to determine a first phase preset value for the selected frequency of the periodic signal and a provided time for a time specified by a controlling event (col 4 line 1-7, fig 1 phase preset calculator 120).
Foster discloses providing a single direct digital synthesizer, and providing a phase preset value at any given time (col 4 line 10-42), but does not explicitly disclose first and second direct digital synthesizers, and wherein the time provided is a time offset, wherein the direct digital synthesizer is aligned with another direct digital synthesizer using the time offset based on measurements of a residual time alignment mismatch between the signal and another signal transmitted by the other direct digital synthesizer.
However, in the same field of endeavor Iwasaki discloses an apparatus similar to Foster comprising direct digital synthesis (DDS), wherein the apparatus comprises multiple DDS and control thereof with each DDS having the same internal structure (abstract, fig 1,col 4 line 4-45). Iwasaki further discloses providing a time offset, wherein the direct digital synthesizer is aligned with another direct digital synthesizer using the time offset based on measurements of a residual time alignment mismatch between the signal and another signal transmitted by the other direct digital synthesizer (col 4 line 53 – col 5 line 8, the DDS controlling section (fig 1 200) outputs a change trigger signal to its respective DDS at a timing considering the latency of the respective DDS, wherein the latency of the respective DDS is due to its pipeline delay and so forth, col 2 line 33-37, the phase controlling apparatus includes a clock signal generating section that generates a clock signal to each section of the phase controlling apparatus and each of the plurality of signal sources which are operated based on the clock signal, col 5 line 47-col 6 line 9, fig 3, fig 4,the register 231a of figure 4 stores a UT1inidactin update timing of DDS 100a, and DDS 100b, and triggering for matching).
It would have been obvious to one of ordinary skill in the art before the effective filing date to substitute Foster’s single DDS for each of the DDS of Iwasaki and to use the DDS controller and clock generator and computer of Iwasaki to match the triggering of multiple DDS. It would have been obvious to achieve the benefit of controlling the timing and phase of multiple DDS (abstract, col 1 line 14-28).
Regarding claim 6, Foster in view of Iwasaki teach the claim 5 limitations. Iwasaki further discloses a common frequency and determining a phase present value for the signal with reference to the common frequency (col 6 line 17-40, common frequency f1 are sent from the computer section to each DDS and phase preset determined therefrom also shown in fig 5A-E).
It would have been obvious to one of ordinary skill in the art before the effective filing date to use Iwasaki’s phase controlling section within Foster’s phase preset calculator to receive the common frequency and determine the phase preset value as in Iwasaki. The motivation to combine provided with respect to claim 5 applies equally to claim 6.
Regarding claim 7, Foster in view of Iwasaki teach the claim 6 limitations. Iwasaki further discloses a baseband delay and determining a phase preset value with reference to the baseband delay for each direct digital synthesizer (col 4 line 63- col 5 line 8, phase change request).
It would have been obvious to one of ordinary skill in the art before the effective filing date to use Iwasaki’s phase controlling section within Foster’s phase preset calculator to receive the baseband delay and determine a phase present value with reference to the baseband delay for each direct digital synthesizer. The motivation to combine provided with respect to claim 5 applies equally to claim 7.
Allowable Subject Matter
Claims 16-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 4, and 8-12 would be allowable if rewritten to overcome the rejections under 35 USC 112(b) and if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter. Applicant claims apparatus related to direct digital synthesis wherein the apparatus as in claim 1 comprises:
a direct digital synthesizer which transmits a signal, comprising:
a phase increment calculator configured to determine a phase increment for a selected frequency;
a phase accumulator configured to accumulate the phase increment over time and provide an accumulated phase value;
a phase-to-amplitude converter (PAC) configured to convert the accumulated phase value to a periodic signal having the selected frequency; and
a phase preset calculator configured to determine a phase preset value for the selected frequency of the periodic signal and a provided time offset for a time specified by a controlling event, wherein the direct digital synthesizer is aligned with another direct digital synthesizer using the time offset based on measurements of a residual time alignment mismatch between the signal and another signal transmitted by the other direct digital synthesizer.
The apparatus as in claim 5 comprises:
a first direct digital synthesizer which transmits a first signal and comprising a first phase increment calculator configured to determine a first phase increment for a selected frequency; a first phase accumulator configured to accumulate the first phase increment over time and provide a first accumulated phase value; a first phase-to-amplitude converter (PAC) configured to convert the first accumulated phase value to a first periodic signal having the selected frequency; and a first phase preset calculator configured to determine a first phase preset value for the selected frequency of the first periodic signal and a first provided time offset for a time specified by a controlling event; and a
second direct digital synthesizer which transmits a second signal and comprising a second phase increment calculator configured to determine a second phase increment for the selected frequency; a second phase accumulator configured to accumulate the second phase increment over time and provide a second accumulated phase value; a second phase-to-amplitude converter (PAC) configured to convert the second accumulated phase value to a second periodic signal having the selected frequency; and a second phase preset calculator configured to determine a second phase preset value for the selected frequency of the second periodic signal and a second provided time offset for the time specified by the controlling event, wherein the first direct digital synthesizer and the second direct digital synthesizer are aligned using the second provided time offset based on measurements of a first residual timing alignment mismatch between the first signal and the second signal.
The apparatus as in claim 13 comprises:
a first direct digital synthesizer;
a second direct digital synthesizer; and
a controller comprising a memory that stores instructions and a processor that executes the instructions, wherein the instructions when executed by the processor, cause the controller to:
trigger the first direct digital synthesizer to transmit a first signal based on a trigger and trigger the second direct digital synthesizer to transmit a second signal based on the trigger;
measure a residual timing alignment mismatch between the first signal and the second signal;
set the first direct digital synthesizer to determine a first phase preset value for a selected frequency of a periodic signal and a first time offset for a time specified by a controlling event so that the first direct digital synthesizer is aligned with the second direct digital synthesizer using the first time offset based on measuring the residual time alignment mismatch between the first signal and the second signal; and
set the second direct digital synthesizer to determine a second phase preset value for the selected frequency of the periodic signal and a second time offset for the time specified by the controlling event so that the second direct digital synthesizer is aligned with the first direct digital synthesizer using the second time offset based on measuring the residual time alignment mismatch between the first signal and the second signal.
The primary reason for indication of allowable subject matter are the limitations in combination with the remaining limitations with respect to the modulator with respect to the direct digital synthesizer and measured delay. Specifically the limitations as in claim 4:
a waveform generator; and
a modulator, wherein a measured delay between the phase preset calculator and the modulator is compensated for so that a phase of the signal at the modulator is identical to the signal of a direct digital synthesizer that was delayed so that a waveform from the waveform generator and the signal are synchronized to simultaneously reach the modulator from a common controlling event.
The limitations as in claim 8:
wherein the first direct digital synthesizer further comprises a first waveform generator and a first modulator, wherein a measured first delay between the first phase preset calculator and the first modulator is compensated for so that a phase of the first signal at the first modulator is identical to a signal of a direct digital synthesizer that was delayed so that a waveform from the first waveform generator and the first signal are synchronized to simultaneously reach the first modulator from a common controlling event, and
wherein the second direct digital synthesizer further comprises a second waveform generator and a second modulator, wherein a measured second delay between the second phase preset calculator and the second modulator is compensated for so that the phase of the signal at the second modulator is identical to the signal of a direct digital synthesizer that was delayed so that a waveform from the second waveform generator and the second signal are synchronized to simultaneously reach the second modulator from a common controlling event.
The limitations as in claim 16:
measure a first delay between the first phase preset calculator and a first modulator of the first direct digital synthesizer; compensate for the first delay between the first phase preset calculator and the first modulator; measure a second delay between the second phase preset calculator and a second modulator of the second direct digital synthesizer; and compensate for the second delay between the second phase preset calculator and the second modulator.
Foster and Iwasaki each teach the claimed invention according to the above claim mappings. Foster and Iwasaki are each silent with respect to a modulator, not teaching or suggesting the above highlighted limitations.
US 6459404 B1 Nussbaum et al., (hereinafter “Nussbaum”) discloses a direct digital synthesizer, and shifting the phase pulse-to-pulse by a phase shift to correct the DDS phasing (abstract). Nussbaum further discloses a modulator that generates a phase shift to correct pulse to pulse phasing (col 1 line 58-67, fig 3). Nussbaum does not however, explicitly disclose measuring a delay between a phase preset calculator and the modulator, and does not teach or suggest the above highlighted limitations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY E LAROCQUE whose telephone number is (469)295-9289. The examiner can normally be reached on 10:00am - 1200pm, 2:00pm - 8pm ET M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor Andrew Caldwell can be reached on 571-272-3701. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/EMILY E LAROCQUE/Examiner, Art Unit 2182
Prosecution Insights