DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is non-final and is in response to the claims filed 01/27/2023. Claims 1-30 are currently pending, of which claims 1-30 are currently rejected.
Claim Objections
Claim 11 is objected to because of the following informalities:
“determine the scaling parameter is based on…” when it should read “determine the scaling parameter based on…”
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
The following limitations invoke 35 U.S.C. 112(f) because they use the word means and are not modified by sufficient structure, material, or acts for performing the claimed function:
Claim 25:
means for receiving an input
means for performing an integer quantization process on the input, each element of the input being scaled based on a scaling parameter to generate an m-bit floating point output
Claim 26:
means for processing the m-bit floating point output via an artificial neural network to generate an inference
Claim 27:
means for determining the scaling parameter based on a first number of mantissa bits, a nearest integer power of two below the input, and an exponent bias
Claim 28:
means for determining a range of m-bit floating point values represented in a quantization grid based on a first number of mantissa bits, a second number of exponent bits, and a bias value.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 25-30 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim limitations “means for receiving an input” and “means for performing an integer quantization process on the input, each element of the input being scaled based on a scaling parameter to generate an m-bit floating point output” from claim 25, “means for processing the m-bit floating point output via an artificial neural network to generate an inference” from claim 26, “means for determining the scaling parameter based on a first number of mantissa bits, a nearest integer power of two below the input, and an exponent bias” from claim 27, and “means for determining a range of m-bit floating point values represented in a quantization grid based on a first number of mantissa bits, a second number of exponent bits, and a bias value” from claim 28.
Regarding all the limitations specified in the paragraph above, the specification merely repeats the claim language in paragraphs 0099-00102 and does not include sufficient structure to perform the claimed features. Paragraphs 00105-00106 describe generally all means being generically a GPU, program memory associated with the GPU, fully connected layers, NPU, and or routing connection processing unit, but provide insufficient software or hardware to describe the specific structure and/or acts for each entire claimed function. See rejection under 35 U.S.C. 112(b) rejection below for further details.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4, 12, 20, and 25-30 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 4, 12, and 20 recite the limitation “in which the exponent bias is a floating point value.” It is unclear how an exponent bias itself is a floating point value. Appropriate correction is required.
Claim 25 recites the limitations “means for receiving an input” and “means for performing an integer quantization process on the input, each element of the input being scaled based on a scaling parameter to generate an m-bit floating point output”. These descriptions describe functional language, and no algorithm or structure could be found in the specification. Claims 26-30 inherit the same deficiency by reason of dependence.
Claim 26 recites the limitation “means for processing the m-bit floating point output via an artificial neural network to generate an inference”. This description describes functional language, and no algorithm or structure could be found in the specification.
Claim 27 recites the limitation “means for determining the scaling parameter based on a first number of mantissa bits, a nearest integer power of two below the input, and an exponent bias”. This description describes functional language, and no algorithm or structure could be found in the specification.
Claim 28 recites the limitation “means for determining a range of m-bit floating point values represented in a quantization grid based on a first number of mantissa bits, a second number of exponent bits, and a bias value.”. This description describes functional language, and no algorithm or structure could be found in the specification.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Apparatus Claims 9-16 will be addressed before method claims 1-8, media claims 17-24, and means plus functions claims 25-30.
Claims 1-30 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Regarding Claim 9, at Step 1 the claim is directed to an apparatus, which is a statutory category of invention.
At Step 2A, Prong 1, Examiner notes that claims are directed to mathematical concepts and/or mental processes:
An apparatus, comprising:
a memory; and
at least one processor coupled to the memory, the at least one processor configured to:
receive an input; and
perform an integer quantization process on the input, each element of the input being scaled based on a scaling parameter to generate an m-bit floating point output, where m is an integer (mathematical calculations/relationships / mental process (observation and evaluation using pen and paper)).
At Step 2A Prong 2, the additional elements are bolded above. These additional elements are merely an “apply it” scenario using generically recited computer components. See MPEP 2106.05 (f). In the “a memory; and at least one processor coupled to the at least one processor configured to” limitations, the claims is simply using generic processor(s) coupled to a memory to perform the mathematical calculations/relationships (perform an integer quantization process on the input), or the mental process of evaluating a integer quantization using pen and paper (perform an integer quantization process). Alternatively, even if not considered as merely an ”apply it” scenario, this type of architecture of a system using a processor coupled to a memory is well understood routine and conventional. See Step 2B analysis below.
Additionally, the italicized limitations above are describing insignificant extra-solution activity used for the processing of the mathematical concepts.
At Step 2B, there are no additional elements claimed that amount to significantly more than the recited judicial exception.
Regarding the architecture of the system, this is a well understood routine and conventional architecture known to be used in generic computers. As per the book As per the book Computer Organization and Design : The Hardware/Software Interface, Chapter 1: Computer Abstractions and Technology, “A plastic board containing packages of integrated circuits or chips, including processor, cache, memory, and connectors for I/O devices such as networks and disks.” (Page 20, “motherboard” description). These limitations therefore are considered well understood routine and conventional even upon consideration. Thus, these limitations do not amount to significantly more.
In regards to the insignificant extra-solution activity found in the Italicized limitations, the “receive an input” limitation describe mere data transmitting recited at a high level of generality. Per MPEP 2106.05(d)(II), the courts have recognized the following computer functions as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity: i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362. These limitations therefore remain insignificant extra-solution activity even upon consideration. Thus, these limitations do not amount to significantly more.
Claim 10 is directed to the mathematical concept generating m-bit floating point result (mathematical calculations/relationships), or the mental process of evaluating an m-bit floating point result (observation and evaluation). Moreover, the limitation “via an artificial neural network to generate an inference” merely generally links the use of the judicial exception to a particular technological environment or field of use. Examples of limitations that the courts have described as merely indication a field of use or technological environments in which to apply a judicial exception include, as discussed in MPEPE 2106.05(h):
iv. Specifying that the abstract idea of monitoring audit log data relates to transactions or activities that are executed in a computer environment, because this requirement merely limits the claims to the computer field, i.e., to execution on a generic computer, FairWarning V. latric Sys., 839 F.3d 1089, 1094-95, 120 USPQ2d 1293, 1295 (Fed. Cir. 2016); and
vi. Limiting the abstract idea of collecting information, analyzing it, and displaying certain results of the collection and analysis to data related to the electric power grid, because limiting application of the abstract idea to power-grid monitoring is simply an attempt to limit the use of the abstract idea to a particular technological environment, Electric Power Group, LLC V. Alstom S.A., 830 F.3d 1350, 1354, 119 USPQ2d 1739, 1742 (Fed. Cir. 2016);
Claim 11 is directed to the mathematical concept and/or mental process of determining a scaling parameter (mathematical calculations / observation and evaluation). Under Steps 2A prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application nor do they amount to significantly more than the judicial exception.
Claim 12 merely describes the exponent bias used for the mathematical concept and/or mental process of determining a scaling parameter. Under Steps 2A prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application nor do they amount to significantly more than the judicial exception.
Claim 13 is directed to the mathematical concept and/or mental process of determining a range of m-bit floating point values (mathematical calculations / observation and evaluation). Under Steps 2A prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application nor do they amount to significantly more than the judicial exception.
Claim 14 is directed to the mathematical concept and/or mental process of determining a range of m-bit floating point values, further describing the determining of mantissa bits, exponent bits, and bias value (mathematical calculations / observation and evaluation). Under Steps 2A prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application nor do they amount to significantly more than the judicial exception.
Claim 15 merely describes the m-bit floating point output generated from the mathematical concept and/or mental process of quantizing an integer. Under Steps 2A prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application nor do they amount to significantly more than the judicial exception.
Claim 16 merely describes the input being a 32-bit input used for the mathematical concept and/or mental process of quantizing an integer, and the m-bit floating point output being an eight-bit floating point output generated from the mathematical concept and/or mental process of quantizing an integer. Under Steps 2A prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application nor do they amount to significantly more than the judicial exception.
Claim 1 is a method version of claim 9 and is rejected for at least the same reasons therein. Herein, claim 1 is directed towards the statutory categories of a method, thus also satisfying Step 1. Under Steps 2A prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application nor do they amount to significantly more than the judicial exception.
Claims 2-8 recite similar limitations as claims 10-16 and are rejected for at least the same reasons therein. Under Steps 2A prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application nor do they amount to significantly more than the judicial exception.
Claim 17 is media version of claim 9 and is rejected for at least the same reasons therein. Herein, claim 17 is directed towards the statutory category of an apparatus, thus also satisfying Step 1. Under Step 2A Prong 2, the claim merely recites a generic computer using media having a program code to perform the mathematical concept recited in claim 9. At Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Claims 18-24 recite similar limitations as claims 10-16 and are rejected for at least the same reasons therein. Under Steps 2A prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application nor do they amount to significantly more than the judicial exception.
Claim 25 is an apparatus claim using means plus function limitations and reciting similar limitations as claim 9 and is rejected for at least the same reasons therein. Herein, claim 25 is directed towards the statutory category of an apparatus, thus also satisfying Step 1. Under Step 2A Prong 2, the claim merely recites a generic apparatus to perform the mathematical concept recited in claim 9. At Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Claims 26-30 recite similar limitations as claims 10-15 and are rejected for at least the same reasons therein. Under Steps 2A prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application nor do they amount to significantly more than the judicial exception.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Apparatus Claims 9-8 and 15-16 will be addressed before method claims 1-2 and 7-8, media claims 17-18 and 23-24, and means plus functions claims 25-26, and 30.
Claims 1-2, 7-10, 15-18, 23-26, 30 are rejected under 35 U.S.C. 102 (a)(1) and (a)(2) as being anticipated by Sun et al. (U.S. Patent Application Publication No.: US 20210064985 A1), hereinafter “Sun”.
Regarding Claim 9, Sun teaches:
An apparatus, comprising:
a memory (Fig. 13, e.g., shows memory 1328); and
at least one processor coupled to the memory (Fig. 13, e.g., shows processing unit 1316 coupled to memory 1328; ¶0099, e.g., processing unit 1316 comprises circuitry 100; Fig. 1, e.g., circuitry 100 comprises quantization unit 108 , scale up unit 106, and scale down unit 112 (at least one processor)), the at least one processor configured to:
receive an input (Fig. 1, e.g., quantization unit 108 receives precise residual Resp); and
perform an integer quantization process on the input (¶0040, e.g., quantization unit 108 quantizes precise residual Resp, and outputs a lower precision floating point format such as FP16 or FP8), each element of the input being scaled based on a scaling parameter to generate an m-bit floating point output, where m is an integer (Fig. 1, e.g., shows scale down unit 112 inputting data to multiply-and-add unit 102; ¶0046 and Equation 7, e.g., scale value scales down Resq; ¶0030, e.g., multiply-and-add unit 102 receives Resq as an FP8 input (8-bit input))
Regarding Claim 10, Sun teaches:
The apparatus of claim 9, in which the at least one processor is further configured to process the m-bit floating point output via an artificial neural network to generate an inference (Abstract, e.g., apparatus is used for training and inferencing a neural network).
Regarding Claim 15, Sun teaches:
The apparatus of claim 9, in which the m-bit floating point output comprises an eight-bit floating point output (¶0040, e.g., quantization unit 108 quantizes precise residual Resp, and outputs a lower precision floating point format such as FP16 or FP8).
Regarding Claim 16, Sun teaches:
The apparatus of claim 9, in which the input is a single precision 32-bit value and the m-bit floating point output comprises an eight-bit floating point output ((¶0040, e.g., quantization unit 108 quantizes precise residual Resp, which is a FP32 value, and outputs a lower precision floating point format such as FP16 or FP8).
Regarding Claims 1-2 and 7-8, they are method claims practiced by the apparatus of claims 9-10 and 15-16. They are rejected for the same reasons as claims 9-10 and 15-16.
Regarding Claims 17-18 and 23-24, they are media claims practiced by the apparatus of claims 9-10 and 15-16. They are rejected for the same reasons as claims 9-10 and 15-16.
With regards to Claims 25-26, and 30, they are means plus function versions of the claimed apparatus above (Claims 9-10 and 15 respectively), wherein all claim limitations also have been addressed and/or covered in cited areas. Thus, accordingly, these claims are rejected for at least the same reasons therein.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Apparatus Claims 11-14 will be addressed before method claims 3-6, media claims 19-22, and means plus functions claims 27-29.
Claims 3-6, 11-14, 19-22, and 27-29 are rejected under 35 U.S.C. 103 as being unpatentable over Sun, in view of Michael L. Overton in NPL “Numerical Computing with IEEE Floating Point Arithmetic” (www.r-5.org/files/books/computers/hw-layers/assembly/overviews/Michael_L_Overton-Numerical_Computing-EN.pdf.), hereinafter “Overton”.
Regarding Claim 11, Sun teaches:
The apparatus of claim 9, in which the at least one processor is further configured to determine the scaling parameter is based on a first number of mantissa bits, a nearest integer power of two below the input, … (¶0042, e.g., scale is chosen based on function f(qmin/Pmin, qmax/pmax); ¶0065, e.g., FP8 format comprises sign bit, exponent bits, and mantissa bits; ¶0054, e.g., scale of 28 is used).
Sun does not teach:
The apparatus of claim 9, in which the at least one processor is further configured to determine the scaling parameter is based on a first number of mantissa bits, a nearest integer power of two below the input, and an exponent bias.
However, Overton teaches floating point values being represented by a fraction field (mantissa), an exponent, and a bias. Overton explains “The first line shows that the representation for zero requires a special zero bitstring for the exponent field as well as a zero bitstring for the fraction field” (Overton: Page 19, The Single Format, Second Paragraph) and “The number 127, which is added to the desired exponent E, is called the exponent bias” (Page 20, First Paragraph).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the single format representation as taught by Overton with the FP8 floating point number representation as taught by Sun. One would have been motivated to combine these references because both references disclose using floating point numbers, and Overton enhances the model of Sun by properly representing floating point values.
Regarding Claim 12, Sun in view of Overton teach:
The apparatus of claim 11, in which the exponent bias is a floating point value (Overton: Page 20, First Paragraph, e.g., Exponent bias is added to exponent value to represent mantissa bits in a floating point value).
The motivation to combine provided with respect to claim 11 applies equally to claim 12.
Regarding Claim 13, Sun teaches:
The apparatus of claim 9, in which the at least one processor is further configured to determine a range of m-bit floating point values represented in a quantization grid based on a first number of mantissa bits, a second number of exponent bits, … ((¶0040, e.g., quantization unit 108 quantizes precise residual Resp, and outputs a lower precision floating point format such as FP16 or FP8; ¶0065, e.g., FP8 format comprises sign bit, exponent bits, and mantissa bits) …
Sun does not teach:
The apparatus of claim 9, in which the at least one processor is further configured to determine a range of m-bit floating point values represented in a quantization grid based on a first number of mantissa bits, a second number of exponent bits, and a bias value.
However, Overton teaches floating point values being represented by a fraction field (mantissa), an exponent, and a bias. Overton explains “The first line shows that the representation for zero requires a special zero bitstring for the exponent field as well as a zero bitstring for the fraction field” (Overton: Page 19, The Single Format, Second Paragraph) and “The number 127, which is added to the desired exponent E, is called the exponent bias” (Page 20, First Paragraph).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the single format representation as taught by Overton with the FP8 floating point number representation as taught by Sun. One would have been motivated to combine these references because both references disclose using floating point numbers, and Overton enhances the model of Sun by properly representing floating point values.
Regarding Claim 14, Sun in view of Overton teach:
The apparatus of claim 13, in which the range of m-bit floating point values and the first number of mantissa bits are learnable parameters (Sun: ¶0030-0033, e.g., circuitry 100 receives learning rate Ir), the second number of exponent bits is determined from the first number of mantissa bits (¶0042, e.g., exponent bits are used to represent the range of the value), and the bias value is determined from the range of m-bit floating point values, the first number of mantissa bits, and the second number of exponent bits (Overton: Page 20, First Paragraph, e.g., Exponent bias is added to exponent value to represent mantissa bits).
The motivation to combine provided with respect to claim 13 applies equally to claim 14.
Regarding Claims 3-6, they are method claims practiced by the apparatus of claims 11-14. They are rejected for the same reasons as claims 11-14.
Regarding Claims 19-22, they are media claims practiced by the apparatus of claims 9-10 and 15-16. They are rejected for the same reasons as claims 11-14.
With regards to Claims 27-29, they are means plus function versions of the claimed apparatus above (Claims 11-13 respectively), wherein all claim limitations also have been addressed and/or covered in cited areas. Thus, accordingly, these claims are rejected for at least the same reasons therein.
Prior Art Made of Record
US 20210034982 A1 – teaches transitioning a floating point network to a quantized network using scale and shift parameters. See ¶0086. This is pertinent to the quantization of floating point numbers described in the instant application on at least ¶0026.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CARLOS H DE LA GARZA whose telephone number is (571)272-0474. The examiner can normally be reached Monday-Friday 9:30AM-6PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Caldwell can be reached at (571) 272-3702. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C.H.D./
Carlos H. De La GarzaExaminer, Art Unit 2182 (571)272-0474
/EMILY E LAROCQUE/Primary Examiner, Art Unit 2182
Prosecution Insights