Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is nonfinal and is in response to claims filed on 11/21/2023. Claims 1-20 are pending for examination.
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on 11/21/2023 is in compliance with the provisions of 37 CFR 1.97, 1.98, and MPEP § 609. It has been placed in the application file, and the information referred to therein has been considered as to the merits.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitations are: the matrix computation unit, the accumulator, the ISUM processing unit, the ISUM matrix integrator, in claims 6-8, 13-18, and 20.
Because these claim limitations are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, they are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have these limitations interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitations to avoid them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitations recite sufficient structure to perform the claimed function so as to avoid them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
The claims recite a “matrix computation unit”, an “accumulator”, an “ISUM processing unit”, and “ISUM matrix integrator”, etc. The specification in paragraph [0090] recites “ISUM TCS 300 is shown comprising memories 302A, 302B, and 302C (collectively, "memories 302"), integrator 304, and ISUM MCU 310. ISUM TCS 300 can comprise an ISUM TCS such as ISUM TCS 220 in FIG. 2B. While not shown in FIG. 3A, as previously described, a TCS such as ISUM TCS 300 can include processors, such as a neural network, a host processor, runtime processor, RDU and/or processors of RDUs, and/or accelerator processors (CGRAs, FPGAs, GPUs, etc.)”.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 recites “wherein the first program instructions are executable by at least one processor”. It is unclear if this processor is the same one as the one in claim 9. For examination purposes, examiner has interpreted “wherein the first program instructions are executable by at least one processor” as “wherein the first program instructions are executable by the at least one processor”.
Claim 11 recites “wherein the first program instructions are executable by at least one processor”. It is unclear if this processor is the same one as the one in claim 9. For examination purposes, examiner has interpreted “wherein the first program instructions are executable by at least one processor” as “wherein the first program instructions are executable by the at least one processor”.
Claim 12 recites “wherein the first program instructions are executable by at least one processor”. It is unclear if this processor is the same one as the one in claim 9. For examination purposes, examiner has interpreted “wherein the first program instructions are executable by at least one processor” as “wherein the first program instructions are executable by the at least one processor”.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to abstract ideas without significantly more.
With regards to claim 1, at step 1, the claim is directed to a method, which is a statutory category of invention.
At Step 2A Prong 1, the examiner notes that the claim is directed to mental processes and/or mathematical concepts. The claim language has been reproduced below:
A method, the method comprising: (mental process, evaluation)
generating, by a computing system, (mental process, evaluation) an Integrated Summation (ISUM) integrated matrix comprising number K of multiplicand columns and number P of addend columns, (mathematical calculation) wherein each of columns 1 though the number K of multiplicand columns comprises respective columns 1 through the number K of a first multiplicand matrix having the number K of columns, (mental process, evaluation; mathematical relationship) and wherein each of the number P of addend columns comprises an integrated addend; (mental process, evaluation; mathematical relationship)
generating, by the computing system, (mental process, evaluation) an ISUM row-extended matrix comprising the number K of multiplicand rows and the number P of extended rows, (mathematical calculation) wherein rows 1 through the number K of the multiplicand rows comprise respective rows 1 though the number K of a second multiplicand matrix having the number K of rows, (mental process, evaluation; mathematical relationship) and wherein each extended row, among the number P of extended rows, comprises a constant row; (mental process, evaluation; mathematical relationship)
computing, by the computing system, (mental process, evaluation) (K+P) number of products, (mathematical calculation) the (K+P) number of products comprising each column element of columns 1 through (K+P) of a row of the ISUM integrated matrix, multiplied by a corresponding row element, among rows 1 through (K+P), of a column of the ISUM row-extended matrix; (mental process, evaluation; mathematical relationship)
and,
computing, by the computing system, (mental process, evaluation) an Integrated Sum comprising a sum of the (K+P) number of products. (mathematical calculation)
Each of the non-bolded limitations are mental processes and/or mathematical calculations. The “A method, the method comprising:” limitation is an evaluation mental process that can be performed by choosing what the method comprises. The “generating, by a computing system” limitation is an evaluation mental process that can be performed by choosing what does the generating. The “an Integrated Summation (ISUM) integrated matrix comprising number K” limitation is a mathematical calculation that can be performed by generating the ISUM matrix by hand using pen and paper. The “wherein each of columns 1 though the number K of multiplicand columns comprises respective columns 1 through the number K of a” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what the multiplicand columns comprises. The “and wherein each of the number P of addend columns comprises” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what the addend columns comprises. The “generating, by the computing system” limitation is an evaluation mental process that can be performed by choosing what does the generating. The “an ISUM row-extended matrix comprising the number K of multiplicand rows” limitation is a mathematical calculation that can be performed by generating the ISUM matrix by hand using pen and paper. The “wherein rows 1 through the number K of the multiplicand rows comprise respective rows 1 though the number K of a second multiplicand” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what the multiplicand rows comprises. The “and wherein each extended row, among the number P of extended rows,” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what the extended rows comprises. The “computing, by the computing system” limitation is an evaluation mental process that can be performed by choosing what does the computing. The “(K+P) number of products” limitation is a mathematical calculation that can be performed by computing the products by hand using pen and paper. The “the (K+P) number of products comprising each column element of columns 1 through (K+P)” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what the products comprises. The “computing, by the computing system” limitation is an evaluation mental process that can be performed by choosing what does the computing. The “an Integrated Sum comprising a sum of the" limitation is a mathematical calculation that can be performed by computing the integrated sum by hand using pen and paper.
At step 2A Prong 2, the additional elements are bolded above. The additional elements amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f).
At step 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
Regarding claim 9, It recites similar language as claim 1, and is rejected for at least the same reasons therein. Herein, claim 9 is directed towards the statutory category of an article of manufacture, thus also satisfying step 1. The “A computer program product, the computer program product comprising” limitation is an evaluation metal process that can be performed by choosing what the computer program product comprises. The “a computer readable storage medium having first program instructions embodied therewith” limitation is an evaluation metal process that can be performed by choosing what the computer readable storage medium has. The “wherein the first program instructions are executable by at least one processor to cause the at least one processor to” limitation is an evaluation metal process that can be performed by choosing what the first program instruction do. Under step 2A Prong 2, The “embodied” limitation, as claimed under BRI, are additional elements that are insignificant extra-solution activity. The “embodied” in the context of the claim encompasses mere data gathering. None of the additional elements regarding the generic computer components (i.e. the computer program product, the computer readable storage medium, the at least one processor, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under Step 2B, the claim recites “a computer readable storage medium having first program instructions embodied therewith”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network); and
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93.
Regarding claim 13, It recites similar language as claim 1, and is rejected for at least the same reasons therein. Herein, claim 13 is directed towards the statutory category of a machine, thus also satisfying step 1. The “A computing system, the computing system comprising” limitation is an evaluation mental process that can be performed by choosing what the computing system comprises. The “wherein the ISUM matrix integrator is configured to” limitation is an evaluation mental process that can be performed by choosing what the ISUM matrix integrator is configured to do. The “wherein the ISUM PU is configured to” limitation is an evaluation mental process that can be performed by choosing what the ISUM PU is configured to do. Under step 2A Prong 2, none of the additional elements regarding the generic computer components (i.e. the computing system, the ISUM matrix integrator, the ISUM processing unit, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under step 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claims 2 and 14, they are directed to mental processes and/or mathematical concepts. The “wherein the method of the computing system computing the Integrated Sum comprising the sum of the (K+P) number of products comprises” limitation is an evaluation mental process that can be performed by choosing what the method comprises. The “computing, by the computing system,” limitation is an evaluation mental process that can be performed by choosing what does the computing. The “the Integrated sum as a multiply-accumulate computation of each column element of the columns 1 through (K+P) of the row of the ISUM integrated matrix multiplied by” limitation is a mathematical calculation that can be performed by computing the products by hand using pen and paper. At Step 2A prong 2, none of the additional elements regarding the generic computer components (i.e. the computing system, the ISUM PU, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). At step 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claims 3, 10, and 15, they are directed to mental processes and/or mathematical concepts. The “wherein the method further comprises” limitation is an evaluation mental process that can be performed by choosing what the method comprises. The “outputting, by the computing system” limitation is an evaluation mental process that can be performed by choosing what does the outputting. The “the Integrated Sum to an element of an Integrated Sum Matrix” limitation is an evaluation mental process that can be performed by choosing what is output. The “the element of the Integrated Sum matrix included in” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what is included in a row element of the integrated sum matrix. The “included in a column element of the Integrated Sum matrix corresponding” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what is included in a column element of the integrated sum matrix. At step 2A Prong 2, The “output” limitation, as claimed under BRI, are additional elements that are insignificant extra-solution activity. The “output” in the context of the claim encompasses mere data gathering. None of the additional elements regarding the generic computer components (i.e. the at least one processor, the computing system, the ISUM PU, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under Step 2B, the claim recites “outputting, by the computing system, the Integrated Sum to an element of an Integrated Sum Matrix”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network); and
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93.
With regards to claim 4, it is directed to mental processes and/or mathematical concepts. The “wherein an integrated addend, among the number P of addend columns included in the ISUM integrated matrix, is selected from a group consisting of: a column of a first addend matrix and a column of a second addend matrix comprising products of a constant multiplied by each element of a column of a third addend matrix” limitation is an evaluation mental process and mathematical calculation that can be performed by choosing the integrated addend and then calculating the product of the constants and columns of the third addend matrix by hand using pen and paper. Under Steps 2A Prong 2 and step 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 5, it is directed to mental processes and/or mathematical concepts. The “wherein column element of an extended row, among the number P of extended rows, is a constant” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what the column element of an extended row is. Under Steps 2A Prong 2 and step 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 6, it is directed to mental processes and/or mathematical concepts. The “wherein the computing system comprises” limitation is an evaluation mental process that can be performed by choosing what the computing system comprises. The “and, wherein the method of the computing system computing the Integrated Sum comprises” limitation is an evaluation mental process that can be performed by choosing what the method comprises. The “computing, by a first MCU among the plurality of MCUs” limitation is an evaluation mental process that can be performed by choosing what does the computing. The “a first sum-product, the first sum- product comprising a sum of a first subset of the (K+P) number of products” limitation is a mathematical calculation that can be performed by computing the first sum-product by hand using pen and paper. The “computing, by a second MCU among the plurality of MCUs,” limitation is an evaluation mental process that can be performed by choosing what does the computing. The “a second sum-product, the second sum-product comprising a sum of a second subset of the (K+P) number of products;” limitation is a mathematical calculation that can be performed by computing the second sum-product by hand using pen and paper. The “and adding, by a third MCU among the plurality of MCUs,” limitation is an evaluation mental process that can be performed by choosing what does the adding. The “the first sum-product and the second sum- product” limitation is a mathematical calculation that can be performed by adding the first sum-product and the second sum- product by hand using pen and paper. At Step 2A prong 2, none of the additional elements regarding the generic computer components (i.e. the computing system, the matrix computation units, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). At step 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 7, it is directed to mental processes and/or mathematical concepts. The “wherein the method of the first MCU computing the first sum-product and the second MCU computing the second sum-product comprises the first MCU computing the first sum-product and the second MCU computing the second sum-product in parallel” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing when the calculations are performed. At Step 2A prong 2, none of the additional elements regarding the generic computer components (i.e. the first MCU, the second MCU, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). At step 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 8, it is directed to mental processes and/or mathematical concepts. The “wherein the computing system comprises an accumulator” limitation is an evaluation mental process that can be performed by choosing what the computing system comprises. The “and, wherein the method of the third MCU adding the first sum-product and the second sum-product comprises” limitation is an evaluation mental process that can be performed by choosing what the method comprises. The “adding product among the first subset of the (K+P) number of products” limitation is a mathematical calculation that can be performed by adding the product by hand using pen and paper. The “adding a product among the second subset of the (K+P) number of products” limitation is a mathematical calculation that can be performed by adding the product by hand using pen and paper. At Step 2A prong 2, none of the additional elements regarding the generic computer components (i.e. the computing system, the third MCU, the accumulator, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). At step 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 11, it is directed to mental processes and/or mathematical concepts. The “wherein the first program instructions are executable by at least one processor to further cause” limitation is an evaluation mental process that can be performed by choosing what the instructions cause the processor to do. The “compute the Integrated Sum as a multiply-accumulate computation” limitation is a mathematical calculation that can be performed by computing the Integrated Sum by hand using pen and paper. At Step 2A prong 2, none of the additional elements regarding the generic computer components (i.e. the least one processor, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). At step 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 12, it is directed to mental processes and/or mathematical concepts. The “wherein the first program instructions are executable by at least one processor to further cause” limitation is an evaluation mental process that can be performed by choosing what the instructions cause the processor to do. The “compute, in parallel, the Integrated Sum as a sum of a first sum-product and a second sum-product” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing when the calculations are performed. The “the first sum-product comprising” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing when the first sum-product comprises. The “the second sum-product comprising” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing when the second sum-product comprises. At Step 2A prong 2, none of the additional elements regarding the generic computer components (i.e. the least one processor, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). At step 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 16, it is directed to mental processes and/or mathematical concepts. The “wherein the ISUM PU comprises” limitation is an evaluation mental process that can be performed by choosing what the ISUM PU comprises. The “wherein the ISUM PU configured to compute the Integrated Sum comprises” limitation is an evaluation mental process that can be performed by choosing what the computation comprises. The “the first MCU configured to” limitation is an evaluation mental process that can be performed by choosing what the first MCU is configured to do. The “compute, in a first multiply-accumulate (MACC) computation, a first set of MACC sum-products” limitation is a mathematical calculation that can be performed by computing the first set of MACC sum-products by hand using pen and paper. The “the second ISUM MCU configured to” limitation is an evaluation mental process that can be performed by choosing what the second MCU is configured to do. The “in a second MACC computation, a second set of MACC sum-products” limitation is a mathematical calculation that can be performed by computing the second set of MACC sum-products by hand using pen and paper. The “the first set of MACC sum-products comprising a sum of a first subset of the (K+P) number of products” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what the first set of MACC sum-products comprises. The “and the second set of MACC sum-products comprising a sum of a second subset of the (K+P) number of products” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what the second set of MACC sum-products comprises. The “one of the first MCU and the second MCU further configured to” limitation is an evaluation mental process that can be performed by choosing what the first MCU and the second MCU are further configured to do. The “compute the Integrated Sum comprising a sum of the first set of MACC sum-products and the second set of MACC sum- products” limitation is a mathematical calculation that can be performed by computing the Integrated Sum by hand using pen and paper. At Step 2A prong 2, none of the additional elements regarding the generic computer components (i.e. the first MCU, the second MCU, the ISUM PU, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). At step 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 17, it is directed to mental processes and/or mathematical concepts. The “wherein the computing system further comprises an accumulator” limitation is an evaluation mental process that can be performed by choosing what the computing system comprises. The “wherein the ISUM PU comprises a first MCU and a second MCU” limitation is an evaluation mental process that can be performed by choosing what the ISUM PU comprises. The “wherein the ISUM PU is further configured to” limitation is an evaluation mental process that can be performed by choosing what the ISUM PU is configured to do. The “input, to the first MCU, a first column element” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what is input into the MCU. The “input, to the first MCU, a first row element,” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what is input into the MCU. The “input, to the second MCU, a second column element” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what is input into the MCU. The “input, to the second MCU, a second row element” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what is input into the MCU. The “ wherein the first MCU is configured to” limitation is an evaluation mental process that can be performed by choosing what the MCU is configured to do. The “compute a first product, among the (K+P) number of products, comprising the first row element multiplied by the first column element” limitation is a mathematical calculation that can be performed by computing the first product by hand using pen and paper. The “wherein the second MCU is configured to” limitation is an evaluation mental process that can be performed by choosing what the MCU is configured to do. The “compute a second product, among the (K+P) number of products, comprising the second row element multiplied by the second column element” limitation is a mathematical calculation that can be performed by computing the second product by hand using pen and paper. The “wherein at least one of the first MCU and the second MCU are further configured to” limitation is an evaluation mental process that can be performed by choosing what the MCU is configured to do. The “add the first product and the second product” limitation is a mathematical calculation that can be performed by adding the first and second product by hand using pen and paper. The “wherein the ISUM PU configured to compute the Integrated Sum comprises the ISUM PU further configured to” limitation is an evaluation mental process that can be performed by choosing what the ISUM PU is further configured to do. The “compute the Integrated Sum including the accumulator” limitation is a mathematical calculation that can be performed by computing the Integrated Sum by hand using pen and paper. At step 2A Prong 2, The “input” limitations, as claimed under BRI, are additional elements that are insignificant extra-solution activity. The “input” in the context of the claim encompasses mere data gathering. None of the additional elements regarding the generic computer components (i.e. the first MCU, the second MCU, the accumulator, the ISUM PU, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under Step 2B, the claim recites “ input, to the first MCU, a first column element”, “input, to the first MCU, a first row element”, “input, to the second MCU, a second column element”, “input, to the second MCU, a second row element”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network); and
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93.
With regards to claim 18, it is directed to mental processes and/or mathematical concepts. The “wherein the first MCU comprises” limitation is an evaluation mental process that can be performed by choosing what the MCU comprises. The “comprising a set of row element buffers” limitation is an evaluation mental process that can be performed by choosing what the first tensor buffer comprises. The “a second tensor buffer comprising” limitation is an evaluation mental process that can be performed by choosing what the second tensor buffer comprises. The “wherein the ISUM PU configured to” limitation is an evaluation mental process that can be performed by choosing what the ISUM PU is configured to do. The “input the first column element to the first MCU comprises the ISUM PU configured to input the first column element into” limitation is an evaluation mental process that can be performed by choosing what the input comprises. The “wherein the first MCU configured to compute the first product comprises the first MCU further configured to input the first column element” limitation is an evaluation mental process that can be performed by choosing what the input comprises. The “wherein the ISUM PU configured to input the first row element to the first MCU comprises the” limitation is an evaluation mental process that can be performed by choosing what the ISUM PU is configured to do. The “wherein the first MCU configured to compute the first product comprises the first MCU further configured to” limitation is an evaluation mental process that can be performed by choosing what the input comprises. At step 2A Prong 2, The “input” limitations, as claimed under BRI, are additional elements that are insignificant extra-solution activity. The “input” in the context of the claim encompasses mere data gathering. None of the additional elements regarding the generic computer components (i.e. the first MCU, the first tensor buffer, the row element buffers, the second tensor buffer , the ISUM PU, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under Step 2B, the claim recites “input the first column element to the first MCU comprises the ISUM PU configured to input the first column element into a column buffer”, “input the first column element from the column buffer”, “input the first row element to the first MCU comprises the ISUM PU configured to input the first row element into a row buffer”, “input the first row element from the row buffer”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network); and
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93.
With regards to claim 19, it is directed to mental processes and/or mathematical concepts. The “wherein the first multiplicand matrix comprises a matrix of weight values” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what the first multiplicand matrix comprises. The “wherein an addend column of the ISUM integrated matrix comprises” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what the addend column comprises. Under Steps 2A Prong 2 and step 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 20, it is directed to mental processes and/or mathematical concepts. The “wherein the ISUM PU comprises” limitation is an evaluation mental process that can be performed by choosing what the ISUM PU comprises. The “wherein the ISUM PU configured to” limitation is an evaluation mental process that can be performed by choosing what the ISUM PU is configured to do. The “compute the (K+P) number of products comprises the processor configured to compute at least a subset of the (K+P) number of products” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what performs the computations. At Step 2A prong 2, none of the additional elements regarding the generic computer components (i.e. the ISUM PU, the processor, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). At step 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
Allowable Subject Matter
Claims 1-20 would be allowable if rewritten to overcome the rejections set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
While prior art teaches of performing multiplication accumulation operations on matrices, the prior art fails to teach of “generating, by a computing system, an Integrated Summation (ISUM) integrated matrix comprising number K of multiplicand columns and number P of addend columns, wherein each of columns 1 though the number K of multiplicand columns comprises respective columns 1 through the number K of a first multiplicand matrix having the number K of columns, and wherein each of the number P of addend columns comprises an integrated addend”.
The closest prior art of record is Sikka et al. (US 20220197971 A1), as included in the IDS filed 11/21/2023, which teaches of performing multiplication accumulation operations on matrices in parallel. They also teach of padding the matrices. They fail to teach of generating, an Integrated Summation (ISUM) integrated matrix.
The next closest prior art of record is Phelps et al. (US 20180336163 A1), as included in the IDS filed 11/21/2023, which teaches of performing multiplication accumulation operations on matrices in parallel. They fail to teach of generating, an Integrated Summation (ISUM) integrated matrix.
The next closest prior art of record is Li et al. (US 11386212 B2), which teaches of performing multiplication accumulation operations on matrices in parallel. They also teach of appending columns to an input matrix. They fail to teach of generating, an Integrated Summation (ISUM) integrated matrix.
Conclusion
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/J.O.G./Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
