Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
Figure 2 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated: “FIG. 2 is a diagram illustrating a register storing a floating point number according to a related art technique” [0021]. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 13, 14 and 23 are objected to because of the following informalities: claim 13, line 9; claim 14, line 4; claim 23, line 11: “performs following steps” should read “performs. Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier.
The “arithmetic unit” recited in claims 1-23 is being interpreted to have the structure as shown in Figure 4, as well as paragraphs 0036-0039 of the specification.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-2 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 1 and 13, it is not clear where the preamble ends, and the body of the claim begins. For examination purposes, the Examiner is interpreting the preamble as ending at the first “wherein” on the second line of both claims 1 and 13.
Claims 2-12 and 14-22 are rejected by virtue of their dependency on claims 1 and 12, respectively.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-23 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
For the Alice analysis:
For Step 1, claims 1-23 all fall within a statutory category. Claims 1-12 are directed to a process and claims 13-23 are directed to a machine.
Regarding claim 1, for Step 2A, Prong One, the claim recites “comparing the first exponent with an exponent threshold”, which is the mathematical concept of comparing two numbers, “wherein when the first exponent is not smaller than the exponent threshold, the first mantissa is multiplied by the second mantissa to generate a mantissa operation result; and when the first exponent is smaller than the exponent threshold, the first mantissa is multiplied by the second mantissa after at least one bit of the first mantissa is discarded, to generate the mantissa operation result”, which is the mathematical concept of multiplication, and “adding the first exponent to the second exponent to generate an exponent operation result”, which is the mathematical concept of addition.
Regarding Step 2A, Prong Two, the claim recites the additional elements of “a first register and a second register”, “wherein the first register stores a first floating point number, and the second register stores a second floating point number”, “the first register comprises a first exponent bit(s) storing a first exponent, and a first mantissa bit(s) storing a first mantissa; the second register comprises a second exponent bit(s) storing a second exponent, and a second mantissa bit(s) storing a second mantissa”, “an arithmetic unit”, and “generating a calculated floating point number according to the mantissa operation result and the exponent operation result.” Regarding the arithmetic unit and registers, they are recited at such a high level of generality they represent no more than mere instructions to apply the mathematical concepts on a generic computer. Regarding the storing of floating-point numbers, it is claimed at such a high level of generality that represents no more than a means of mere data gathering per MPEP § 2106.05(g) and is therefore insignificant extra-solution activity. Regarding the layout of the floating-point number in the registers, the format the numbers are stored in is incidental to the mathematical concept and is therefore insignificant extra-solution activity. Regarding the generating of a calculated floating-point number, it is claimed at such a high level of generality that represents no more than a means of mere data outputting per MPEP § 2106.05(g) and is therefore insignificant extra-solution activity. Even when viewed in combination, these additional elements do not integrate the recited judicial exception into a practical application, and the claim is directed to the judicial exception.
For Step 2B, the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. Regarding the processor and registers, it is at best the equivalent of merely adding “apply it” to the judicial exception. See MPEP § 2106.05(f). Mere instructions to apply an exception cannot provide an inventive concept. Regarding the storing of floating-point numbers, previously explained as insignificant extra-solution activity, storing and retrieving information has been recognized by the courts as well-understood, routine and conventional per MPEP § 2106.06(d)(II)(iv). Regarding the layout of floating-point numbers as stored in the memory, previously explained as insignificant extra-solution activity, that specific format is the well-understood, routine and conventional IEEE 754 standard for floating point numbers. See Patterson et al., Computer Organization and Design, hereinafter Patterson, Chapter 3.5, “Floating Point”, “Floating-Point Representation”. Regarding the generating of the floating-point number, using the combined mantissa and exponent to make a new floating-point number is also well-understood, routine and conventional IEEE 754 floating-point number as explained above. Even when considered in combination, these additional elements represent mere instructions to apply an exception and insignificant extra-solution activity that is well-understood, routine and conventional, respectively, which do not provide an inventive concept. The claim is not eligible.
Regarding claim 2, for Step 2A, Prong One, the claim recites “performing an XOR operation upon the first sign and the second sign to generate a sign operation result”, which is a mathematical concept.
For Step 2A, Prong Two, the claim recites the additional elements of “wherein the first register further comprises a first sign bit storing a first sign, the second register further comprises a second sign bit storing a second sign”, and “generating the calculated floating point number according to the mantissa operation result, the sign operation result and the exponent operation result”. Regarding the sign bits, the format the numbers are stored in is incidental to the mathematical concept and is therefore insignificant extra-solution activity. Regarding the generating of a calculated floating-point number, it is claimed at such a high level of generality that represents no more than a means of mere data outputting per MPEP § 2106.05(g) and is therefore insignificant extra-solution activity.
For Step 2B, the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. Regarding the layout of floating-point numbers as stored in the memory, previously explained as insignificant extra-solution activity, that specific format is the well-understood, routine and conventional IEEE 754 standard for floating point numbers. See Patterson et al., Computer Organization and Design, hereinafter Patterson, Chapter 3.5, “Floating Point”, “Floating-Point Representation”. Regarding the generating of the floating-point number, using the combined mantissa and exponent to make a new floating-point number is also well-understood, routine and conventional IEEE 754 floating-point number as explained above. Even when considered in combination, these additional elements represent insignificant extra-solution activity that is well-understood, routine and conventional, which do not provide an inventive concept. The claim is not eligible.
Regarding claim 3, for Step 2A, Prong Two, the claim recites the additional elements of “the exponent threshold is stored in a third register and the arithmetic unit accesses the third register when performing multiplication between the first register and the second register”. Storing the threshold is claimed at such a high level of generality that it represents no more than a means of mere data gathering per MPEP § 2106.05(g) and is therefore insignificant extra-solution activity. Even when viewed in combination, these additional elements do not integrate the recited judicial exception into a practical application, and the claim is directed to the judicial exception.
For Step 2B, the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. Storing and retrieving information has been recognized by the courts as well-understood, routine and conventional per MPEP § 2106.06(d)(II)(iv). Even when considered in combination, this additional element represents insignificant extra-solution activity that is well-understood, routine and conventional, which does not provide an inventive concept. The claim is not eligible.
Regarding dependent claims 4-7 and 9-11, for Step 2A, Prong One, they all merely further limit the mathematical concepts of claim 1. For Step 2A, Prong Two, they recite no additional elements. Even when viewed in combination, none of the limitations integrate the recited judicial exception into a practical application and the claims are directed to the judicial exception. The claims are not eligible.
Regarding claim 8, for Step 2A, Prong Two, the claim recites the additional element of “the first register is coupled to a memory”. The register and memory are recited at such a high level of generality they represent no more than mere instructions to apply the mathematical concepts on a generic computer. Even when viewed in combination, these additional elements do not integrate the recited judicial exception into a practical application, and the claim is directed to the judicial exception.
For Step 2B, the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. The register and memory are at best the equivalent of merely adding “apply it” to the judicial exception. See MPEP § 2106.05(f). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not eligible.
Regarding claim 12, for Step 2A, Prong Two, the claim recites the additional element of “accessing a memory using the arithmetic unit” and “the memory stores a plurality of groups of batch normalization coefficients corresponding to a plurality of candidate thresholds”. Both are claimed at such a high level of generality that they represent no more than a means of mere data gathering per MPEP § 2106.05(g) and are therefore insignificant extra-solution activity. Even when viewed in combination, these additional elements do not integrate the recited judicial exception into a practical application, and the claim is directed to the judicial exception.
For Step 2B, the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. Storing and retrieving information has been recognized by the courts as well-understood, routine and conventional per MPEP § 2106.06(d)(II)(iv). Even when considered in combination, this additional element represents insignificant extra-solution activity that is well-understood, routine and conventional, which does not provide an inventive concept. The claim is not eligible.
Regarding claims 13-19 and 20-22, they are apparatus claims that correspond to method claims 1-7 and 10-12, respectively, and are not eligible for the same reasons.
Regarding claim 23, it is an apparatus claim that corresponds to method claim 1 and is not eligible for the same reasons.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 9-11, 13-21 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Patterson in view of Kim (US 2023/005809).
Regarding claim 1, Patterson discloses a first register stores a first floating point number, and the second register stores a second floating point number (Section 2.3, pp 80-81); the first register comprises a first exponent bit(s) storing a first exponent, and a first mantissa bit(s) storing a first mantissa; the second register comprises a second exponent bit(s) storing a second exponent, and a second mantissa bit(s) storing a second mantissa (Page 245, representation); and the method comprises using an arithmetic unit to perform following steps: comparing the first exponent with an exponent threshold, wherein when the first exponent is not smaller than the exponent threshold, the first mantissa is multiplied by the second mantissa to generate a mantissa operation result (Page 258, Figure 3.17, Step 2); adding the first exponent to the second exponent to generate an exponent operation result (Page 258, Figure 3.17, Step 1); and generating a calculated floating point number according to the mantissa operation result and the exponent operation result (Page 258, Figure 3.17). Patterson does not disclose discarding bits of a mantissa below a specific threshold.
Kim discloses when the first exponent is smaller than the exponent threshold, the first mantissa is multiplied by the second mantissa after at least one bit of the first mantissa is discarded, to generate the mantissa operation result (¶ 0090). It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to modify the floating-point multiplication disclosed by Patterson to include the mantissa discarding disclosed by Kim because “[a]s a result, through the reduction of the bit-width of the mantissa, the hardware accelerator of one or more embodiments may improve a hardware computation speed and power consumption compared to the typical floating point arithmetic or the typical hardware accelerator.” (¶ 0094).
Regarding claim 2, Patterson discloses the floating-point calculation method according to claim 1, wherein the first register further comprises a first sign bit storing a first sign, the second register further comprises a second sign bit storing a second sign (Page 245, representation), and the floating-point calculation method further comprises: performing an XOR operation upon the first sign and the second sign to generate a sign operation result (Page 258, Figure 3.17, Step 1); and generating the calculated floating point number according to the mantissa operation result, the sign operation result and the exponent operation result (Page 258, Figure 3.17).
Regarding claim 3, Patterson discloses the floating-point calculation method according to claim 1, wherein the exponent threshold is stored in a third register (Section 2.3, pp 80-81). Kim discloses the arithmetic unit accesses the third register when performing multiplication between the first register and the second register (Figure 4, 410).
Regarding claim 4, Kim discloses the floating-point calculation method according to claim 1, wherein when the first exponent is smaller than the exponent threshold, at least one bit of the first mantissa is temporarily stored without involving in arithmetic operations (Figure 4, Truncated parts of 405 and 406).
Regarding claim 5, Kim discloses the floating-point calculation method according to claim 4, wherein the exponent threshold is dynamically adjustable (¶ 0101).
Regarding claim 6, Kim discloses the floating-point calculation method according to claim 5, wherein the exponent threshold is dynamically adjusted according to temperature of the arithmetic unit and/or types of tasks to be processed by the arithmetic unit (Figure 5).
Regarding claim 9, Kim discloses the floating-point calculation method according to claim 1, wherein when the first exponent is smaller than the exponent threshold, at least one bit of the first mantissa is in a Don’t Care state (Figure 4, Truncated parts of 405 and 406).
Regarding claim 10, Patterson discloses the floating-point calculation method according to claim 1, wherein when the first exponent is smaller than the exponent threshold, the first floating point number is decoded into (-1)Sign1 × 2Exponent1, where Sign1 denotes the first sign, and Exponent1 denotes the first exponent (Page 246, paragraph 2, set Fraction to 0).
Regarding claim 11, Patterson discloses the floating-point calculation method according to claim 10, wherein when the second exponent is smaller than the exponent threshold, the second floating point number is decoded into (-1)Sign2 × 2Exponent2, where Sign2 denotes the second sign, and Exponent2 denotes the second exponent (Id.).
Regarding claims 13-19 and 20-22, they are unit claims that correspond to method claims 1-7 and 10-12, respectively, and are rejected for the same reasons.
Regarding claim 23, it is an apparatus claim that corresponds to method claim 1 and is rejected for the same reasons.
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Patterson and Kim as applied to claims 4 and 1, respectively, above, and further in view of Lo et al. (US 12,165,038), hereinafter Lo.
Regarding claim 7, the combination of Patterson and Kim does not disclose training a neural network and adjusting exponent criteria based on criteria.
Lo discloses the floating-point calculation method according to claim 4, wherein the exponent threshold is within a dynamically adjustable range, and the arithmetic unit starts training with an exponent threshold with a value of 1; the arithmetic unit determines a criteria whether an operation precision is higher than an precision threshold (Figure 20); if the criteria is met, the value of the exponent threshold is increased until the operation precision is not higher than an precision threshold, and the dynamically adjustable range comprises the exponent threshold(s) that meets the criteria (Figure 20, 2040, 2042).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to modify the floating-point multiplication disclosed by Patterson and Kim to train a neural network and adjust the threshold as disclosed by Lo because “[u]se of quantized formats can improve neural network processing by, for example, allowing for faster hardware, reduced memory overhead, simpler hardware design, reduced energy use, reduced integrated circuit area, cost savings and other technological improvements.” (Column 8, lines 27-30).
Regarding claim 8, Patterson discloses the floating-point calculation method according to claim 1, wherein the first register is coupled to a memory arranged to store the first exponent (Section 2.3, pp. 80-81), and Lo discloses when the first exponent is smaller than the exponent threshold, at least one bit of the first mantissa is discarded without being stored in the memory (Figure 18).
Claims 12 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Patterson and Kim as applied to claims 1 and 13, respectively, above, and further in view of El-Yaniv et al. (US 10,831,444), hereinafter El-Yaniv.
Regarding claim 12, Patterson discloses the floating-point calculation method according to claim 1, further comprising accessing a memory using the arithmetic unit (p. B-46, Figure B.10.1), and Kim discloses the exponent threshold is selected from a set of candidate thresholds (Figure 5). The combination of Patterson and Kim does not disclose using batch normalization coefficients.
El-Yaniv discloses a memory stores a plurality of groups of batch normalization coefficients corresponding to a plurality of candidate thresholds respectively (Column 4, rows 12-13). It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to modify the algorithm as disclosed by the combination of Patterson and Kim to include the batch normalization as disclosed by El-Yaniv because “[t]he B[atch ]N[ormalization] accelerates the training and reduces the overall impact of a weight scale” (Column 11, rows 5-6).
Regarding claim 22, it is an apparatus claim that corresponds to method claim 12 and is rejected for the same reasons.
Discussion of Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Xi et al. (US 11,651,228) discloses a gradient optimization process that truncates mantissas to save memory. Sivakumar (US 12,033,067) discloses using batch normalization per layer while training a neural network to increase performance. Dibrino (WO 2021/107995), Wegener (US 2013/0007076) and Powell (US 9,417,839) were cited by the International Search Authority as relevant in the corresponding PCT application published as WO 2023/147770 A1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Matthew Strapp whose telephone number is (571)272-9343. The examiner can normally be reached Monday-Friday 8:00 AM-4:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Caldwell can be reached at (571)272-3702. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/M.S./
Matthew StrappExaminer, Art Unit 2182 (571) 272-9343
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
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