DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/5/2026 has been entered.
Response to Amendment
Claims 1-6, 9-11, and 13-20 remain pending in the application, and claims 7-8 and 12 have been canceled. Applicant’s amendments to the Claims have overcome every claim objection previously set forth in the Final Office Action mailed 11/14/2025.
Response to Arguments
Applicant's arguments filed 1/5/2026 have been fully considered but they are not persuasive.
Applicant submits on page 8 of Remarks that there is no disclosure or suggestion in Zhu of performing an NVS operation in successive phases of operation of cell balancing circuitry, much less performing an NVS operation to detect the specific voltages recited in the amended claim. In fact, because the NVS operation of Zhu compares the voltage at the common node to a threshold, it can only detect when the voltage at the common node crosses the threshold, rather than detecting specific voltages in different phases of operation. Thus, the combination of Morita and Zhu would not lead to an arrangement configured to detect the specific voltages recited in the amended claims in successive phases of operation, and so the amended independent claims are not obvious over Morita in view of Zhu.
The examiner submits that Morita discloses circuit 60 which “is a circuit that detects voltage between polarities of each of the secondary batteries B1, B2, and B3” (¶0111). Circuit 60 has a common node (Fig. 5: connecting node N4) which is subject to alternating voltages as energy is transferred between capacitors and cells (Fig. 6).
Zhu discloses a fault detection device through neutral point unbalanced voltage detection by monitoring the voltage at a common node of parallel-connected capacitors (¶0006, abstract, Fig. 3). As evidenced by NEPSI on page 2, NVS, termed as “neutral voltage unbalance in NEPSI, is known to one of ordinary skill to compare voltage against a threshold, specifically, “the neutral voltage will shift in accordance with the impedance unbalance caused by the failing or failed capacitor. The neutral voltage sensor (either a resistive voltage divider or a transformer) output is monitored by an overvoltage-relay that trips when the voltage exceeds the relay trip value for a prescribed length of time.”
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the instant application to incorporate the fault detection device of Zhu into Morita to detect a faulty capacitor.
As noted in the 112b rejection of claims 1 and 13 below for indefiniteness, the specific voltages defined in claim language appear, under the broadest reasonable interpretation, to be any current voltage on a cell. The alternation between the different voltages during a balancing or voltage measuring operation at the common node appear to be read on by Morita (Figs. 5-6).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-6, 9-11, and 13-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 and 13 recite “alternation of the voltage at the common node between nVCell in the first phase and (n-1)VCell in the second phase, where n = 1 for a lowermost capacitor of the set of capacitors and VCell is an average voltage of a single cell of the set of cells.”
The claim language is unclear regarding the meaning of “n = 1 for a lowermost capacitor of the set of capacitors.” In paragraph 0085 of the PGPub of this application describes lowermost as capacitor 232. However, in the context of what is described in claim language, “lowermost” is not tied to any particular capacitor of a set of capacitors since their arrangement is not defined in terms of lower or higher. The term ‘lowermost” appears to be describing a capacitor position at an end of the set of capacitors that couple to a set of cells in series.
The claim language is not clear regarding the term “nVCell.” The claim recites “VCell is an average voltage of a single cell of the set of cells” but does not adequately describe “nVCell.”
In addition, the claim language is not clear regarding “average voltage of a single cell of the set of cells.” The average voltage of a single cell seems to imply the current voltage of the cell since not context is given with regards to what voltage values of the cell are being averaged.
If n is 1, as recited in the phrase, the examiner understands the terms “nVCell” and “(n-1)VCell” respectively become “1VCell” and “0VCell.” The best understanding the examiner can find, using Fig. 4 and paragraph 85 of the application’s PGPub, is that “1VCell” and “0VCell” respectively correspond to a voltage of the nth cell arranged at the end of the set of cells in series and a voltage of the cell adjacent to the nth cell.
For the purposes of compact prosecution, the examiner interprets the phrase in claim 1 as “alternation of the voltage at the common node between a voltage of the nth cell arranged at the end of the set of cells in series in the first phase and a voltage of the cell adjacent to the nth cell in the second phase
Claims 2-6, 9-11, and 14-20 inherit the deficiencies of claim 1 and are also rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 9-10, 13-15, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Morita (US 20040246635 A1, published 2004-12-09) in view of Zhu et al. (CN 101834064 A, published 2010-09-15), hereinafter referred to as Zhu, as evidenced by NEPSI "An alternative to neutral voltage unbalance protection systems in ungrounded wye capacitor banks,” published online Dec 12 2015.
Regarding independent claim 1, Morita discloses a cell balancing circuitry (Fig. 5: voltage detection circuit 60) for balancing a set of cells (B1-B3), the cell balancing circuitry comprising:
a switch network (61-66) configured for coupling to the cells;
a set of capacitors (67-69) coupled in parallel between the switch network and a common node (connecting node N4); and
a detection circuitry (voltage detection circuit 60 in Fig. 5 has similar structure as the circuit for cell balancing in Applicant’s Fig. 2a-2c such as the arrangement in Fig. 5 of cells B1-B3 in series, coupling switches S61-S66, and capacitors 67-69 with a common connection point).
wherein the cell balancing circuitry is operable in a first phase in which a first subset of the set of cells is coupled to the set of capacitors (Figs. 1 and 5 and ¶0015: examiner interprets phase one when capacitor 37 is coupled to cell B1, and capacitor 38 is coupled to cell B2 in balancing circuit 30 in Fig. 1 as applicable to the detection circuit 60 where phase 1 is when capacitors 67-68 are coupled to cell B1, and capacitors 68-69 are coupled to cell B2) and a second phase in which a second subset of the set of cells, different from the first subset, is coupled to the set of capacitors (the examiner interprets phase two as capacitor(s) (37 in Fig. 1 or 67-68 in Fig. 5) decouples from B1 and couples to B2, and capacitor(s) (38 in Fig. 1 or 68-69 in Fig. 5)decouples from B2 and couples to B3).
Morita does not disclose detection circuitry configured to detect a fault in a capacitor of the set of capacitors based on a voltage at the common node,
wherein the detection circuitry is configured to monitor a voltage at the common node during operation of the cell balancing circuitry and to identify that an nth capacitor of the set of capacitors is affected by a fault when a predetermined modulation of the voltage at the common node is detected in successive phases of operation.
Zhu discloses detection circuitry (¶0006 and abstract: fault detection device determines the specific capacitor that has failed) configured to detect a fault in a capacitor of the set of capacitors based on a voltage at a common node (Fig. 3: neutral point unbalanced voltage detection N.V.S is situated at the common node of parallel-connected capacitors),
wherein the detection circuitry is configured to monitor a voltage at the common node during operation of the cell balancing circuitry and to identify that an nth capacitor of the set of capacitors is affected by a fault (¶0006: the N.V.S detects a specific faulty capacitor).
Morita and Zhu both disclose circuits using capacitors in voltage detection circuits with similar design to applicant’s capacitors 230 and common node 240 of Fig. 2A. It would have been obvious for a person with ordinary skill in the art before the effective filing date to incorporate the fault detection device in the circuit of Zhu into the common node of the circuit of Morita to determine which capacitor has a fault because the output device is arranged in parallel capacitors with N.C.S (neutral wire unbalanced current detection) or N.V.S (neutral point unbalanced voltage detection) detection devices, the specific capacitor with an internal fault can be directly judged; and the output unit is electrically connected with the sensing unit and then arranged in the capacitor, so that the peripheral detecting elements of the capacitor can be reduced, convenience can be brought to the production and use and the potential safety hazard during the use of the equipment can be greatly reduced (Abstract and ¶0006: determining a specific capacitor has failed).
Morita modified by Zhu has voltage monitored at the common node to detect a faulty capacitor, the predetermined modulation of voltage at the common node during successive phases of cell balancing or cell voltage detection (Morita - Figs. 5-6 and ¶0119-0120: the phases illustrated in Fig. 6 and ¶0120 for the voltage detection circuit 60),
wherein the predetermined modulation comprises alternation of the voltage at the common node between nVCell in the first phase and (n-1)VCell in the second phase, where n = 1 for a lowermost capacitor of the set of capacitors and VCell is an average voltage of a single cell of the set of cells (See the 112b rejection above regarding the examiner’s interpretation of this segment. The examiner understands that as Morita balances or measures the voltage of the cells through successive phases as illustrated in Fig. 6 and ¶[120], voltages fed to the cells from the capacitors across the common node will alternate between higher and lower voltages).
Regarding independent claim 13, Morita discloses a cell balancing circuitry comprising a switch network and a set of capacitors in which each capacitor of the set of capacitors is coupled in parallel between the switch network and a common node and the cell balancing circuitry is operable in a first phase in which a first subset of the set of cells is coupled to the set of capacitors and a second phase in which a second subset of the set of cells, different from the first subset, is coupled to the set of capacitors (Figs. 5-6 and ¶0119-0120: the phases illustrated in Fig. 6 and ¶0120 for the voltage detection circuit 60 cause expected modulation in voltage at the common node N4 during normal operation), the method comprising:
monitoring a voltage at the common node during operation of the cell balancing circuitry (Figs. 5-7 and ¶0120).
Morita does not disclose identifying that an nth capacitor of the set of capacitors is affected by a fault if a predetermined modulation of the voltage at the common node is detected in successive phases of operation.
Zhu discloses identifying that an nth capacitor of the set of capacitors is affected by a fault if a predetermined modulation of the voltage at the common node is detected in successive phases of operation (Fig. 3 and ¶0006: neutral point unbalanced voltage detection N.V.S situated at the common node of parallel-connected capacitors).
Morita and Zhu both disclose methods of using capacitors in circuits. It would have been obvious for a person with ordinary skill in the art before the effective filing date to incorporate the capacitor fault detection in the circuit of Zhu into the common node of the circuit of Morita to determine which capacitor has a fault (¶0006: determining a specific capacitor has failed).
Morita discloses wherein the predetermined modulation comprises alternation of the voltage at the common node between nVCell in the first phase and (n-1)VCell in the second phase, where n = 1 for a lowermost capacitor of the set of capacitors and VCell is an average voltage of a single cell of the set of cells (See the 112b rejection above regarding the examiner’s interpretation of this segment. The examiner understands that as Morita balances or measures voltage the cells through successive phases as illustrated in Figs. 5-6 and ¶[120], voltages fed to the cells from the capacitors across the common node will alternate between higher and lower voltages).
Regarding claim 2, Morita in view of Zhu discloses the cell balancing circuitry according to claim 1, wherein Zhu discloses the detection circuitry is configured to output a signal indicative of a fault in a capacitor if the voltage at the common node differs from an expected voltage (¶0025: the output signal can directly determine which capacitor of the set of capacitors connected in parallel has an internal fault. It is well known in the art if a voltage differs from an expected voltage, there is a fault in the system; as evidenced by NEPSI page 2, NVS is known to one of ordinary skill in the art to compare a voltage against a threshold [over-voltage/relay-trip-value]).
Regarding claim 3, Morita in view of Zhu discloses the cell balancing circuitry according to claim 1, wherein Morita discloses the switch network comprises a plurality of switches configured to selectively couple a first terminal of each capacitor of the set of capacitors to a first terminal or a second terminal of a respective different cell of the set of cells (Figs. 1 and 5 and ¶0015).
Regarding claim 4, Morita in view of Zhu discloses the cell balancing circuitry according to claim 3, wherein Morita discloses the circuitry further comprising control circuitry (Figs. 1 and 5: control section 39) configured to control operation of the plurality of switches of the switch network (¶0055).
Regarding claim 5, Morita in view of Zhu discloses the cell balancing circuitry according to claim 4, wherein Morita discloses the control circuitry is configured to receive a clock signal and to synchronize operation of the switches to cycles of the clock signal (Figs. 2 and 6 and ¶0055: the examiner interprets the synchronous opening and closing of switches as following a clock signal).
Regarding claim 6, Morita in view of Zhu discloses the cell balancing circuitry according to claim 3, wherein the control circuitry is operable, when the switch network is coupled to a set of cells prior to operation of the cell balancing circuitry, or in response to detection of a fault in a capacitor during operation of the cell balancing circuitry, to: decouple the set of capacitors from the set of cells (Fig. 5: if any pair of switches [61, 62], [63, 64], or [65, 66] are both turned off, then the corresponding capacitor is decoupled))
Subsequently coupling a capacitor of the set of capacitors to the set of cells falls within the scope of Morita.
Detection circuitry to monitor the voltage at the common node and to identify the capacitor affected by the voltage if the voltage at the common node changes falls within the scope of Zhu.
Regarding claim 9, Morita in view of Zhu discloses the cell balancing circuitry according to claim 6, wherein the control circuitry is configured to decouple the identified capacitor from the set of cells (Fig. 5: when a pair of switches are opened, a capacitor is decoupled from a cell).
Regarding claim 10, Morita in view of Zhu discloses the cell balancing circuitry according to claim 9 wherein the control circuitry is configured to hold open switches associated with the identified capacitor (Fig. 5: holding switches open falls within the scope of the voltage detection circuit 60 of Morita).
Regarding independent claim 14, Morita in view of Zhu discloses an integrated circuit comprising cell balancing circuitry according to claim 1 (See rejection for claim 1).
Regarding independent claim 15, Morita in view of Zhu discloses a host device comprising cell balancing circuitry according to claim 1 (See rejection for claim 1).
Regarding independent claim 17, Morita in view of Zhu discloses a battery or battery pack (Morita - Fig. 5: voltage detection circuit 60 comprising batteries B1-B3) comprising cell balancing circuitry according to claim 1 (See rejection for claim 1).
Regarding independent claim 18, Morita in view of Zhu discloses an integrated circuit comprising a switch network for cell balancing circuitry according to claim 1 (See rejection for claim 1).
Regarding claim 19, Morita in view of Zhu discloses the integrated circuit according to claim 18 further comprising control circuitry (Morita - Fig. 5: control section 39) for controlling the switch network (See rejection for claim 1).
Regarding independent claim 20, Morita in view of Zhu discloses a module comprising an integrated circuit according to claim 19 and a set of capacitors (Fig. 5: 67-69).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Morita in view of Zhu, and further in view of Ferber (US 20110221398 A1).
Regarding claim 11, Morita in view of Zhu discloses the cell balancing circuitry according to claim 1.
Morita in view of Zhu does not disclose wherein the cell balancing circuitry further comprises a voltage source for supplying a bias voltage to the common node.
Ferber discloses a cell balancing circuitry comprising a voltage source for supplying a bias voltage (Fig. 8 and ¶0056: a reference voltage via reference source 705) to the common node (rail capacitor 230, which the examiner interprets as analogous to the common node).
Both Morita and Ferber disclose circuits for balancing batteries. It would have been obvious to a person with ordinary skill in the art before the effective filing date to incorporate the reference voltage source, rail capacitor, and their arrangement in the circuit of Ferber into the circuit of Morita to monitor the voltages at the common node (¶0055: monitoring rail capacitor voltage to provide status of energy system).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Morita in view of Zhu, and further in view of Lin (US 20140097787 A1).
Regarding claim 16, Morita in view of Zhu does not disclose a host device comprises an electric vehicle, an electric bicycle, a wheelchair, an electric scooter, a cordless power tool, a computing device, a laptop, notebook or tablet computer, a gaming device, a games console, a controller for a games console, a virtual reality (VR) or augmented reality (AR) device, a mobile telephone, a portable audio player, a portable device, an accessory device for use with a laptop, notebook, netbook or tablet computer, a gaming device, a games console a VR or AR device, a mobile telephone, a portable audio player or other portable device.
Lin discloses a host device (¶0006: electric vehicle) comprising of balancing circuitry (battery management system).
Both Lin and Morita, modified by Zhu, disclose circuits for balancing batteries. It would have been obvious for a person with ordinary skill in the art before the effective filing date to substitute the circuitry of Morita modified into the EV of Lin for the purpose of detecting faulty capacitors in a balancing circuit for an EV.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Ryu-Sung Peter Weinmann whose telephone number is (703)756-5964. The examiner can normally be reached Monday-Friday 9am-5pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julian Huffman, can be reached at (571) 272-2147. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/Ryu-Sung P. Weinmann/Examiner, Art Unit 2859 April 20, 2026
/JULIAN D HUFFMAN/Supervisory Patent Examiner, Art Unit 2859
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