DETAILED ACTION
This communication is in response to the after final amendment filed 8/20/26 in which claims 1, 5, 8, 15, and 17 were amended. Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8/20/26 has been entered.
Response to Arguments
Applicant’s arguments with respect to claims 1, 8, and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Allowable Subject Matter
Claim 17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claims 1, 4, 8, 11, 14-15, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Vemuri (US 11,704,535 B1; patented Jul. 18, 2023) in view of Schulzrinne (US 2004/0148395 A1; published Jul. 29, 2004).
Regarding claim 1, Vemuri discloses [a] non-transitory computer-readable medium that includes stored thereon computer-executable instructions for generating a stream of estimates from a stream of observations in real time that when executed by at least a processor of a computer cause the computer to: (see Vemuri 5:1-51 (“The DPE array 130 of the reconfigurable IC 120 has any number of DPEs (also referred to as kernel processors), and these DPEs of the DPE array 130 perform operations on the input data (e.g., data points of input feature maps) to generate output data (e.g., data points of output feature maps).”))
receive observations from the stream of observations; (see Vemuri 6:44-51 (“In embodiments where the neural network involves image processing, the input data comprises pixels of input feature maps and the output data comprises pixels of the output feature maps. In such embodiments, the input data points for processing by the NNUs of the DPE array are pixels from the input images, and the output data points are pixels of the output images.”))
load the observations in real time into a circular buffer, wherein the circular buffer includes a first buffer and a second buffer that are configured together in a circular write configuration; (see Vemuri 7:12-27 (“In the exemplary embodiment, the IO controller 406 of the reconfigurable IC 400 accesses and receives data, including input image data, IFMs, and/or activation outputs stored in external memory (e.g., DRAM) through the internal interconnect 402. The IO controller 406 stores the data from external memory in the IO buffers 408. The reconfigurable IC 400 partitions the IO buffers 408 into ping-pong buffers: iStage buffers, which hosts input data, and oStage buffers, which hosts output data from the reconfigurable IC 400. Ping-pong buffers (also referred herein as double-buffers) are discussed in further detail below. In the exemplary embodiment, once the IO controller 406 has stored data in the IO buffers 408, the feeding controller 410 reads the iStage buffers of the IO buffers 408 and populates the feeding buffers 414. The feeding buffers 414 feed the DPE array 430 with the input data.”)).
Vemuri does not expressly disclose:
wherein loading the observations comprises writing the observations into one buffer of the first buffer and the second buffer until the one buffer becomes full and, in response to the one buffer becoming full, switching to loading subsequently received observations into the other of the first buffer and the second buffer; (but see Schulzrinne ¶ 101 (“The A/D and D/A buffers can be divided into two parts, the upper buffer 2002a and lower buffer 2002b, respectively. Both buffers can be designed as circular buffers. In this way, when the current pointer reaches the buffer bottom, it wraps around to its beginning. However, from the encoder and decoder point of view, it is used as a two-frame ping-pong buffer (defined as upper frame and lower frame) scheme. The operation of this process is shown in FIGS. 20A and 20B. For A/D conversion, when the upper (or lower) is full, the data in the upper (or lower) buffer will be passed through ping pong switch 2004 and copied to the speech encode buffer, EncodeBuf, 2006. For D/A conversion, if the upper (or lower) buffer is completed, a new frame of data will be copied from the speech decode buffer, DecodeBuf, 2010 to the upper 2008a (or lower 2008b) buffer. This mechanism ensures that while the encoding (or decoding) algorithm reads(writes) from one part of the buffer, the A/D (or D/A) sampling ISR can write (read) the other part of the buffer without conflict.”)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Vemuri to incorporate the teachings of Schulzrinne to switch to writing to a second buffer when the first buffer is full, at least because doing so would ensure reading from one buffer while writing to the other.
Vemuri further discloses:
generate estimates by a machine learning model of what the observations are expected to be from the observations that are in the circular buffer, wherein the generation of estimates alternates between generating the estimates from the observations that are in the first buffer in parallel while the second buffer is being loaded, and generating the estimates from the observations that are in the second buffer in parallel while the first buffer is being loaded; and (see Vemuri 8:50-9:3 (“FIG. 6 illustrates example operations 600 performed by a reconfigurable IC, according to embodiments of the present disclosure. In one embodiment, the reconfigurable IC can be the reconfigurable IC 400 of FIG. 4. Operations 600 begin, at 602, by receiving first data into a ping buffer from a data controller. The data controller can be the IO controller 406, the feeding controller 410, the weight controller 412, or the output controller 420 of the reconfigurable IC 400 of FIG. 4. The data from the data controller can comprise input data, such as IFMs, or weight data. At 604, operations 600 continue by concurrently processing the first data in the ping buffer while receiving second data into a pong buffer. The ping buffers and the pong buffers are discussed in further detail below. At 606, operations 600 continue by transmitting the first processed data from step 604 into the ping buffer into a second data controller. At 608, operations 600 continue by concurrently processing the second data in the pong buffer while receiving a third data into the ping buffer from the data controller.”))
write the estimates to the stream of estimates in real time as the estimates are generated (see Vemuri 10:44-56 (“In one embodiment, because of ping-pong-buffering, the oStage buffers results in the oStage ping buffer 718 1 and oStage pong buffer 718 2. The reconfigurable IC multiplexes the output data in the oStage ping buffer 718 1 and oStage pong buffer 718 2 via an output multiplexer 726 to pass to the output controller 720. The output multiplexer 726 acts in a similar fashion as the feeding multiplexer 722 and the weight multiplexer 724 with the alternating multiplexer pattern in the PS state and the WO state. The output controller 720 transmits the accumulated output data to external memory via the internal interconnect 702. In some embodiments, the output controller 720 is implemented on programmable logic 122.”); 12:16-23 (“The DPE array 730 repeats the previous read-and-process operations on the contents of the feeding pong buffer 714 2 instance to generate the next 32 data points of the 16 OFMs. Also, while the DPE array 730 repeats the previous read-and-process operations, the output controller 720 reads the contents of the oStage ping buffer 718 1 instance and writes the contents out to external memory over the internal interconnect 702.”)).
Regarding claim 4, Vemuri, in view of Schulzrinne, discloses the invention of claim 1 as discussed above. Vemuri further discloses instantiate a primary compute instance, wherein the primary compute instance is configured to generate the estimates by the ML model; (see Vemuri 8:13-23 (“Operations 500 begin, at 502, when the reconfigurable IC receives configuration data. This configuration data can come from a host computer, such as the host computer 102 of FIG. 1 , and can include information about NNUs of DPEs of a DPE array of the reconfigurable IC, and about the DPEs of the DPE array. The configuration data can also include configurations of the various storage structures of the reconfigurable IC, such as the depths of the IO buffers 408, and the weight buffers 416 1-416 N. In some embodiments, receiving configuration data includes receiving a neural network model having a plurality of layers.”); 8:33-41 (“At 506, operations 500 continue with the reconfigurable IC configuring a subset of NNUs for each DPE of an array of DPEs using a host based on the configuration data to process a portion of the input data based on the layer of the neural network model. As mentioned, the reconfigurable IC can have any number of DPEs and any number of NNUs hardwired, and the configuration data allows for subset of the DPEs to be used and for a subset of the NNUs of the subset of DPEs to be used.”))
instantiate an ancillary compute instance, wherein the ancillary compute instance is configured to load the observations into the circular buffer and write the estimates to the stream of estimates; and (see Vemuri 8:55-9:3 (“Operations 600 begin, at 602, by receiving first data into a ping buffer from a data controller. The data controller can be the IO controller 406, the feeding controller 410, the weight controller 412, or the output controller 420 of the reconfigurable IC 400 of FIG. 4. The data from the data controller can comprise input data, such as IFMs, or weight data. At 604, operations 600 continue by concurrently processing the first data in the ping buffer while receiving second data into a pong buffer. The ping buffers and the pong buffers are discussed in further detail below. At 606, operations 600 continue by transmitting the first processed data from step 604 into the ping buffer into a second data controller. At 608, operations 600 continue by concurrently processing the second data in the pong buffer while receiving a third data into the ping buffer from the data controller.”))
place the circular buffer into a location in memory accessible to both the primary compute instance and the ancillary compute instance (see Vemuri 7:52-56 (“The output controller 420 writes the contents of the DPE output buffers 418 1-418 N to the oStage buffers of the IO buffers 408, and the IO controller 406 writes the contents of the oStage buffers of the IO buffers 408 to external memory (e.g., DRAM) through the internal interconnect 402.”)).
Claim 11 is a method claim corresponding to claim 4 and, therefore, is similarly rejected.
Claim 18 is a system claim corresponding to claim 4 and, therefore, is similarly rejected.
Regarding claim 8, Vemuri discloses [a] computer-implemented method for generating a stream of estimates from a stream of observations in real time, the method comprising: (see Vemuri 5:1-5 (“The DPE array 130 of the reconfigurable IC 120 has any number of DPEs (also referred to as kernel processors), and these DPEs of the DPE array 130 perform operations on the input data (e.g., data points of input feature maps) to generate output data (e.g., data points of output feature maps).”))
receiving observations from the stream of observations; (see Vemuri 6:44-51 (“In embodiments where the neural network involves image processing, the input data comprises pixels of input feature maps and the output data comprises pixels of the output feature maps. In such embodiments, the input data points for processing by the NNUs of the DPE array are pixels from the input images, and the output data points are pixels of the output images.”))
loading the observations in real time into a circular buffer, wherein the circular buffer is a composite buffer comprising a first buffer and a second buffer logically connected to form a circular write configuration; (see Vemuri 7:12-27 (“In the exemplary embodiment, the IO controller 406 of the reconfigurable IC 400 accesses and receives data, including input image data, IFMs, and/or activation outputs stored in external memory (e.g., DRAM) through the internal interconnect 402. The IO controller 406 stores the data from external memory in the IO buffers 408. The reconfigurable IC 400 partitions the IO buffers 408 into ping-pong buffers: iStage buffers, which hosts input data, and oStage buffers, which hosts output data from the reconfigurable IC 400. Ping-pong buffers (also referred herein as double-buffers) are discussed in further detail below. In the exemplary embodiment, once the IO controller 406 has stored data in the IO buffers 408, the feeding controller 410 reads the iStage buffers of the IO buffers 408 and populates the feeding buffers 414. The feeding buffers 414 feed the DPE array 430 with the input data.”)).
Vemuri does not expressly disclose:
wherein loading the observations comprises writing the observations to one buffer of the first buffer and the second buffer and, in response to reaching an end of the one buffer, transferring writing of subsequently received observations to the other of the first buffer and the second buffer in accordance with the circular write configuration; (but see Schulzrinne ¶ 101 (“The A/D and D/A buffers can be divided into two parts, the upper buffer 2002a and lower buffer 2002b, respectively. Both buffers can be designed as circular buffers. In this way, when the current pointer reaches the buffer bottom, it wraps around to its beginning. However, from the encoder and decoder point of view, it is used as a two-frame ping-pong buffer (defined as upper frame and lower frame) scheme. The operation of this process is shown in FIGS. 20A and 20B. For A/D conversion, when the upper (or lower) is full, the data in the upper (or lower) buffer will be passed through ping pong switch 2004 and copied to the speech encode buffer, EncodeBuf, 2006. For D/A conversion, if the upper (or lower) buffer is completed, a new frame of data will be copied from the speech decode buffer, DecodeBuf, 2010 to the upper 2008a (or lower 2008b) buffer. This mechanism ensures that while the encoding (or decoding) algorithm reads(writes) from one part of the buffer, the A/D (or D/A) sampling ISR can write (read) the other part of the buffer without conflict.”)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Vemuri to incorporate the teachings of Schulzrinne to switch to writing to a second buffer when the first buffer is full, at least because doing so would ensure reading from one buffer while writing to the other.
Vemuri further discloses:
generating estimates by a machine learning model of what the observations are expected to be from the observations that are in the circular buffer, wherein the generation of estimates alternates between generating the estimates from the observations stored in the first buffer concurrently with loading observations into the second buffer, and generating the estimates from the observations stored in the second buffer concurrently with loading observations into the first buffer; and (see Vemuri 8:50-9:3 (“FIG. 6 illustrates example operations 600 performed by a reconfigurable IC, according to embodiments of the present disclosure. In one embodiment, the reconfigurable IC can be the reconfigurable IC 400 of FIG. 4. Operations 600 begin, at 602, by receiving first data into a ping buffer from a data controller. The data controller can be the IO controller 406, the feeding controller 410, the weight controller 412, or the output controller 420 of the reconfigurable IC 400 of FIG. 4. The data from the data controller can comprise input data, such as IFMs, or weight data. At 604, operations 600 continue by concurrently processing the first data in the ping buffer while receiving second data into a pong buffer. The ping buffers and the pong buffers are discussed in further detail below. At 606, operations 600 continue by transmitting the first processed data from step 604 into the ping buffer into a second data controller. At 608, operations 600 continue by concurrently processing the second data in the pong buffer while receiving a third data into the ping buffer from the data controller.”))
writing the estimates to the stream of estimates in real time as the estimates are generated (see Vemuri 10:44-56 (“In one embodiment, because of ping-pong-buffering, the oStage buffers results in the oStage ping buffer 718 1 and oStage pong buffer 718 2. The reconfigurable IC multiplexes the output data in the oStage ping buffer 718 1 and oStage pong buffer 718 2 via an output multiplexer 726 to pass to the output controller 720. The output multiplexer 726 acts in a similar fashion as the feeding multiplexer 722 and the weight multiplexer 724 with the alternating multiplexer pattern in the PS state and the WO state. The output controller 720 transmits the accumulated output data to external memory via the internal interconnect 702. In some embodiments, the output controller 720 is implemented on programmable logic 122.”); 12:16-23 (“The DPE array 730 repeats the previous read-and-process operations on the contents of the feeding pong buffer 714 2 instance to generate the next 32 data points of the 16 OFMs. Also, while the DPE array 730 repeats the previous read-and-process operations, the output controller 720 reads the contents of the oStage ping buffer 718 1 instance and writes the contents out to external memory over the internal interconnect 702.”)).
Regarding claim 14, Vemuri, in view of Schulzrinne, discloses the invention of claim 8 as discussed above. Vemuri further discloses accepting an input of a buffer length; and (see Vemuri 7:57-63 (“In a further embodiment, the reconfigurable IC 400 comprises two features to optimize fetches by the DPEs. With one feature, the reconfigurable IC 400 decides the burst length of the fetch requests from the weight controller 412 based on the available storage in the weight buffer (both the weight ping buffer 412 1 and the weight pong buffer 412 2) and the size of the filters of the DPEs.”))
configuring the first buffer and the second buffer to accept as many of the observations as the buffer length before becoming full (see Vemuri 7:63-67 (“The reconfigurable IC 400 calibrates the number of filters of the DPEs that can be pre-fetched with each request from the weight controller 412. The reconfigurable IC 400 then uses the parameters to decide on the burst length of the fetch requests by the DPE. The burst length decides the efficiency of the memory subsystem.”)).
Claim 20 is a system claim corresponding to claim 14 and, therefore, is similarly rejected.
Regarding claim 15, Vemuri discloses [a] computing system, comprising:
at least one processor connected to at least one memory; (Vemuri 4:34-38 (“FIG. 1 is a block diagram of the architecture of a reconfigurable integrated circuit (IC) in use with a host computer, in accordance with the embodiment disclosed. The host computer 102 (also referred herein as a host) comprises a processor 104 and memory 106.”))
a non-transitory computer-readable medium including instructions stored thereon for generating a stream of estimates from a stream of observations in real time that when executed by at least the processor cause the computing system to: (Vemuri 19:63-67 (“In the context of this document, a computer readable storage medium is any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus or device.”))
receive observations from the stream of observations; (see Vemuri 6:44-51 (“In embodiments where the neural network involves image processing, the input data comprises pixels of input feature maps and the output data comprises pixels of the output feature maps. In such embodiments, the input data points for processing by the NNUs of the DPE array are pixels from the input images, and the output data points are pixels of the output images.”))
load the observations in real time into a circular buffer based on a position pointer, wherein the circular buffer includes a first buffer and a second buffer that are logically connected to form a circular configuration; (see Vemuri 7:12-27 (“In the exemplary embodiment, the IO controller 406 of the reconfigurable IC 400 accesses and receives data, including input image data, IFMs, and/or activation outputs stored in external memory (e.g., DRAM) through the internal interconnect 402. The IO controller 406 stores the data from external memory in the IO buffers 408. The reconfigurable IC 400 partitions the IO buffers 408 into ping-pong buffers: iStage buffers, which hosts input data, and oStage buffers, which hosts output data from the reconfigurable IC 400. Ping-pong buffers (also referred herein as double-buffers) are discussed in further detail below. In the exemplary embodiment, once the IO controller 406 has stored data in the IO buffers 408, the feeding controller 410 reads the iStage buffers of the IO buffers 408 and populates the feeding buffers 414. The feeding buffers 414 feed the DPE array 430 with the input data.”)).
Vemuri does not expressly disclose:
wherein loading the observations comprises:
writing the observations to successive available positions of one buffer of the first buffer and the second buffer until the one buffer becomes full,
advancing the position pointer to indicate a next available position as the observations are written and,
after a final available position of the one buffer is reached, advancing the position pointer to the other buffer and continuing writing in the other buffer, overwriting oldest observations previously stored in the other buffer;
(but see Schulzrinne ¶ 101 (“The A/D and D/A buffers can be divided into two parts, the upper buffer 2002a and lower buffer 2002b, respectively. Both buffers can be designed as circular buffers. In this way, when the current pointer reaches the buffer bottom, it wraps around to its beginning. However, from the encoder and decoder point of view, it is used as a two-frame ping-pong buffer (defined as upper frame and lower frame) scheme. The operation of this process is shown in FIGS. 20A and 20B. For A/D conversion, when the upper (or lower) is full, the data in the upper (or lower) buffer will be passed through ping pong switch 2004 and copied to the speech encode buffer, EncodeBuf, 2006. For D/A conversion, if the upper (or lower) buffer is completed, a new frame of data will be copied from the speech decode buffer, DecodeBuf, 2010 to the upper 2008a (or lower 2008b) buffer. This mechanism ensures that while the encoding (or decoding) algorithm reads(writes) from one part of the buffer, the A/D (or D/A) sampling ISR can write (read) the other part of the buffer without conflict.”)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Vemuri to incorporate the teachings of Schulzrinne to switch to writing to a second buffer when the first buffer is full, at least because doing so would ensure reading from one buffer while writing to the other.
Vemuri further discloses:
generate estimates by a machine learning model of what the observations are expected to be from the observations that are in the circular buffer, wherein the generation of estimates alternates between generating the estimates from the observations stored in the first buffer concurrently with loading observations into the second buffer, and generating the estimates from the observations stored in the second buffer concurrently with loading observations into the first buffer; and (see Vemuri 8:50-9:3 (“FIG. 6 illustrates example operations 600 performed by a reconfigurable IC, according to embodiments of the present disclosure. In one embodiment, the reconfigurable IC can be the reconfigurable IC 400 of FIG. 4. Operations 600 begin, at 602, by receiving first data into a ping buffer from a data controller. The data controller can be the IO controller 406, the feeding controller 410, the weight controller 412, or the output controller 420 of the reconfigurable IC 400 of FIG. 4. The data from the data controller can comprise input data, such as IFMs, or weight data. At 604, operations 600 continue by concurrently processing the first data in the ping buffer while receiving second data into a pong buffer. The ping buffers and the pong buffers are discussed in further detail below. At 606, operations 600 continue by transmitting the first processed data from step 604 into the ping buffer into a second data controller. At 608, operations 600 continue by concurrently processing the second data in the pong buffer while receiving a third data into the ping buffer from the data controller.”))
write the estimates to the stream of estimates in real time as the estimates are generated (see Vemuri 10:44-56 (“In one embodiment, because of ping-pong-buffering, the oStage buffers results in the oStage ping buffer 718 1 and oStage pong buffer 718 2. The reconfigurable IC multiplexes the output data in the oStage ping buffer 718 1 and oStage pong buffer 718 2 via an output multiplexer 726 to pass to the output controller 720. The output multiplexer 726 acts in a similar fashion as the feeding multiplexer 722 and the weight multiplexer 724 with the alternating multiplexer pattern in the PS state and the WO state. The output controller 720 transmits the accumulated output data to external memory via the internal interconnect 702. In some embodiments, the output controller 720 is implemented on programmable logic 122.”); 12:16-23 (“The DPE array 730 repeats the previous read-and-process operations on the contents of the feeding pong buffer 714 2 instance to generate the next 32 data points of the 16 OFMs. Also, while the DPE array 730 repeats the previous read-and-process operations, the output controller 720 reads the contents of the oStage ping buffer 718 1 instance and writes the contents out to external memory over the internal interconnect 702.”)).
Claims 2, 9, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Vemuri and Schulzrinne as applied to claims 1, 8, and 15 above, and further in view of Zhang (US 2022/0292074 A1; published Sep. 15, 2022).
Regarding claim 2, Vemuri, in view of Schulzrinne, discloses the invention of claim 1 as discussed above. Vemuri does not expressly disclose instructions that when executed by at least the processor cause the processor to generate an alert that an anomaly is detected in response to one or more residuals between one of the observations and one of the estimates for the one of the observations satisfying a threshold (but see Zhang, ¶ 60 (“In embodiments, the anomaly detector 114 uses an anomaly threshold to identify whether the observed value is an anomaly. An anomaly threshold may be of any value and may be a default value or customized (e.g., by a user). In some embodiments, an anomaly threshold is three times the standard deviation from the predicted value. As such, if an observed value is outside of three times the standard deviation from the predicted value, the observed value is designated as an anomaly. Stated differently, if an observed value is within three standard deviations from a predicted value, the observed value is deemed a natural variation. As can be appreciated, other anomaly thresholds may be used to detect anomalies and examples provided herein are not intended to limit the scope of the present technology.”); ¶ 61 (“As can be appreciated, in accordance with determining a data point is an anomaly, an alert or notification can be provided to indicate the identified anomaly. By way of example only, an alert or notification identifying the data anomaly may be provided to a user device, such as user device 106, to notify a user of a detected anomaly. One example of an anomaly alert 200 is illustrated in FIG. 2. The anomaly alert 200 includes a time 202 associated with the anomaly. The anomaly alert 200 also includes anomaly data 204 associated with the anomaly. Anomaly data can include any data that may indicate the anomaly. In this example, the anomaly data 204 includes an indication of the metric “Jobs Count,” an expected value of “20963.68,” an observed value “66972,” and an anomaly measure of “4.98” (indicating spike severity). As can be appreciated, other types of anomaly data may alternative or additionally be provided to indicate the anomaly. In addition, the anomaly data 204 includes alert feedback indicator. An alert feedback indicator generally refers to a mechanism or tool that enables a user to provide feedback related to the anomaly alert. In this case, the alert feedback indicator includes a link to be selected in cases that the user believes the detected anomaly is not actually anomalous. In this regard, if the user views the alert data and, for any reason, does not believe that the data is anomalous, the user may select the link to provide such an indication. Although this example includes an alert feedback indicator intended to be used when the data is believed to be inaccurate, in other cases the feedback indicator may be used to confirm the accuracy of the alert. In yet other cases, one feedback indicator may be used to confirm the accuracy of the alert, while another feedback indicator is used to indicate an inaccurate anomaly detection. Further, a feedback indicator may be in any of a number of formats, such as, for example, a link, a button, an icon (e.g., thumbs up or thumbs down), etc.”)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Vemuri to incorporate the teachings of Zhang to train a model to transmit an alert that an anomaly is detected when the anomaly exceeds a threshold, at least because doing so would enable efficient and effective detection of anomalies without manually reviewing and setting thresholds. See Zhang ¶ 1.
Claim 9 is a method claim corresponding to claim 2 and, therefore, is similarly rejected.
Claim 16 is a system claim corresponding to claim 2 and, therefore, is similarly rejected.
Claims 3 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Vemuri and Schulzrinne as applied to claims 1, 8, and 15 above, and further in view of Wang, Hao, et al. "Alloy: Parallel-serial memory channel architecture for single-chip heterogeneous processor systems." 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA). IEEE, 2015 (“Wang”).
Regarding claim 3, Vemuri, in view of Schulzrinne, discloses the invention of claim 1 as discussed above. Vemuri does not expressly disclose measure an end-to-end latency for serially loading the observations, generating the estimates from the observations, and writing the estimates to the stream of estimates; compare the end-to-end latency to a threshold for a maximum acceptable latency, and switch to loading the observations into the circular buffer in response to satisfying the threshold (but see Wang, Section 3.2 (“To service a write request, MC first issues a column write command (WR) and then it places the write data on the DIMM data bus after tCWL (i.e., 11 DIMM cycles for DDR3), following the DDR3 timing protocol. However, the latency of transporting a write data packet through 6-lane (3-lane) WLNK is up to 7 (11) DIMM clock cycles longer than that of transferring the WR command packet through ALNK (Table 2). Thus, the bridge chip cannot place the write data on the DIMM data bus on time. One solution for this problem is buffering the WR command at the bridge chip until the write data arrives at the bridge chip. However, this requires us to modify the MC's timing control for all the subsequent commands due to the delay. Alternatively, MC can simultaneously send both the write data and WR command packets to the bridge chip, overlapping their latency difference with tCWL (Figure 5). This is achieved by re-programming the MC's timing parameter corresponding to tCWL with 0.”); Section 4.1 (“Exploiting both parallel and serial channels, we propose hybrid memory channel architecture-Alloy comprised of parallel and serial channels (Figure 6). Alloy can provide lower latency than using only serial channels and higher bandwidth than using only parallel channels under a package pin constraint. Assume that the baseline is comprised of two parallel channels denoted by 2p-ch. Using the same or fewer pins than 2p-ch, Alloy can be architected to provide one parallel and four serial channels (1p-4s-ch). Alternatively, we may consider replacing ALNK in each serial channel with the parallel address/command bus to nearly halve the latency added to the serial channel (the sum of ALNK and RLNK latency values). Since this increases the number of pins for one serial channel from 24 to 59, we can replace one parallel channel with two of such parallel-serial channels (1p-2ps-ch). This parallel-serial channel still provides 2× higher bandwidth than one parallel channel with 10% fewer pins.”); Section 4.2 (“Specifically in our context, leveraging a standard physical page mapping technique, OS can obliviously allocate physical pages of latency-sensitive (CPU) applications (e.g., App-0 in Figure 7) to a serial channel (Figure 7(a)). This may notably degrade the performance of CPU running such applications due to longer latency of servicing memory requests sent to the serial channels. To minimize such performance degradation, we propose an adaptive memory channel partitioning technique optimized for Alloy. This technique maps the physical pages of latency-sensitive (CPU) and bandwidth-consuming (GPU) applications (e.g., App-1 in Figure 7) preferably to low-latency parallel and high-bandwidth serial channels, respectively (Figure 7(b)).”)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Vemuri to incorporate the teachings of Wang to employ an adaptive memory channel partitioning technique to map latency-sensitive and bandwidth-consuming applications to low-latency parallel and high-bandwidth serial channels, at least because doing so would enable “lower overall latency than using only serial channels.” See Wang, Section 1, Key Contributions.
Claim 10 is a method claim corresponding to claim 3 and, therefore, is similarly rejected.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Vemuri and Schulzrinne as applied to claim 1 above, and further in view of Roever (US 2003/00464498 A1; published Mar. 6, 2003).
Regarding claim 5, Vemuri, in view of Schulzrinne, discloses the invention of claim 1 as discussed above. Vemuri does not expressly disclose instructions that when executed by at least the processor cause the processor to:
write the observations to successive available positions in the one buffer being loaded based on a position pointer; and (but see Roever ¶ 7 (“Generally, the buffer 100 is finite in size, and substantially smaller than the total number of data items that may be received by the buffer 100. To allow for continued use of the buffer, the buffer is generally configured to be "circular", such that when a pointer reaches the end of the buffer, it is reset to the beginning of the buffer. Algorithms are commonly available for enforcing the aforementioned limit 130 within a circular buffer. Depending upon the particular embodiment, the write pointer 110 may also be constrained so as not to track beyond a limit corresponding to the read pointer 120 after it loops around the circular buffer. That is, the transmitting system will be prevented from storing data into the buffer 100 if the prior data has not yet been read by the receiving system. Alternatively, the read pointer 120 can be forced to advance, to keep ahead of the write pointer as new data arrives, the unread data being overwritten by the newly arriving data. For ease of reference and understanding, the invention is presented hereinafter with regard to the enforcement of a limit on the read pointer, the enforcement of a limit on the write pointer 110 being substantially equivalent.”)).
in response to an observation being written to a final available position of the one buffer, advance the position pointer to the other buffer and switch to writing subsequently received observations to successive available positions in the other buffer (but see Roever ¶ 7 (“Generally, the buffer 100 is finite in size, and substantially smaller than the total number of data items that may be received by the buffer 100. To allow for continued use of the buffer, the buffer is generally configured to be "circular", such that when a pointer reaches the end of the buffer, it is reset to the beginning of the buffer. Algorithms are commonly available for enforcing the aforementioned limit 130 within a circular buffer. Depending upon the particular embodiment, the write pointer 110 may also be constrained so as not to track beyond a limit corresponding to the read pointer 120 after it loops around the circular buffer. That is, the transmitting system will be prevented from storing data into the buffer 100 if the prior data has not yet been read by the receiving system. Alternatively, the read pointer 120 can be forced to advance, to keep ahead of the write pointer as new data arrives, the unread data being overwritten by the newly arriving data. For ease of reference and understanding, the invention is presented hereinafter with regard to the enforcement of a limit on the read pointer, the enforcement of a limit on the write pointer 110 being substantially equivalent.”)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Vemuri to incorporate the teachings of Roever to read or write from the two buffers in “circular” fashion such that when a pointer reaches the end of one buffer, it is reset to the beginning of the other buffer, at least because doing so would prevent the system from writing to a buffer if the prior data has not yet been read by the system.
Claims 12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Vemuri and Schulzrinne as applied to claims 1, 8, and 15 above, and further in view of Guo (US 2022/0058345 A1; published Feb. 24, 2022).
Regarding claim 12, Vemuri, in view of Schulzrinne, discloses the invention of claim 8 as discussed above. Vemuri does not expressly disclose instructions that when executed by at least the processor cause the processor to write the observations that correspond to the estimates to the stream of estimates along with the estimates (but see Guo, Abstract (“A current observation expressed in natural language is received. Entities in the current observation are extracted. A relevant historical observation is retrieved, which has at least one of the entities in common with the current observation. The current observation and the relevant historical observation are combined as observations. The observations and a template list specifying a list of verb phrases to be filled-in with at least some of the entities are input to a neural network, which can output the template list of the verb phrases filled-in with said at least some of the entities. The neural network can include attention mechanism. A reward associated with the neural network's output can be received and fed back to the neural network for retraining the neural network.”)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Vemuri to incorporate the teachings of Guo to combine the current observation with the relevant historic observation, at least because doing so would enhance the current observations with potentially relevant history and predicting actions over the enhanced observation. See Guo ¶ 25.
Claim 19 is a system claim corresponding to claim 12 and, therefore, is similarly rejected.
Claims 6, 7, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Vemuri and Schulzrinne as applied to claims 1, 8, and 15 above, and further in view of Srinivasan (US 2013/0226613 A1; published Aug. 29, 2013).
Regarding claim 6, Vemuri, in view of Schulzrinne, discloses the invention of claim 1 as discussed above. Vemuri does not expressly disclose wherein the observations are vectors that include an observed value for each signal in a set of signals, wherein the estimates are vectors that include an estimated value for each signal in the set of signals, wherein the machine learning model is a multivariate machine learning model, and wherein the instructions to generate the estimates further comprise instructions that when executed by at least the processor cause the processor to generate an estimated value for one signal in the set of signals based on observed values for signals in the set other than the one signal (but see Srinivasan ¶ 35 (“Process 200 generates the estimated covariance matrix for the random variables that takes into account the changes in medical condition that the patient 102 experiences over time and changes in the covariance of different medical data that the patient experiences. As described in more detail below, the generated covariance estimate enables more accurate estimation of missing medical data values based on the condition of the patient 102 when the partial medical data are generated. Referring to FIG. 3A and FIG. 3B, the random variable vectors y.sub.0-y.sub.4 correspond to the time periods 0-4 when data are collected from the patient. More generally, one of the N random vectors is denoted as y.sub.n. Each of the random variable vectors y.sub.0-y.sub.4 further includes random variables representing each of the variables measured by the telehealth device. In the example of FIG. 3B, each of the vectors y.sub.0-y.sub.4 includes two random variables, T.sub.n and HR.sub.n that correspond to the temperature and heart rate of the patient 102, respectively, during each of the N time periods. In different sets of medical data for different patients, the number of random variable vectors y is selected based on the number of multivariate observations in the health data collected for the patient. Each of the random vectors y includes at least two random variables, which are exemplified as random variables corresponding to temperature and heart rate in FIG. 3A and FIG. 3B. A population of patients with telehealth devices answers a variety of different questions to provide sets of medical data to the telehealth analysis system 112 based on the medical condition of each patient and treatment. Thus, each vector of random variables y.sub.n can include a wide range of variables corresponding to the responses for each patient over time. Some embodiments that include a large number of medical data samples use a limited number of random variable vectors corresponding to the earlier samples to generate the covariance matrix. For example, if a series of 1,000 samples precedes the most current set of medical data, then one embodiment of process 200 uses the random variables from the 100 most recent medical data samples to generate a 100.times.100 matrix.”)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Vemuri to incorporate the teachings of Srinivasan to generate an estimated covariance matrix for random variables relating to changes in medical condition that a patient experiences, at least because doing so would enable more accurate estimate of missing medical data values based on the condition of the patient.
Claim 13 is a method claim corresponding to claim 6 and, therefore, is similarly rejected.
Regarding claim 7, Vemuri, in view of Schulzrinne, discloses the invention of claim 1 as discussed above. Vemuri does not expressly disclose training the machine learning model to generate estimates of what the observations are expected to be based on training observations that represent a normal operation (but see Srinivasan ¶ 35 (“Process 200 generates the estimated covariance matrix for the random variables that takes into account the changes in medical condition that the patient 102 experiences over time and changes in the covariance of different medical data that the patient experiences. As described in more detail below, the generated covariance estimate enables more accurate estimation of missing medical data values based on the condition of the patient 102 when the partial medical data are generated. Referring to FIG. 3A and FIG. 3B, the random variable vectors y.sub.0-y.sub.4 correspond to the time periods 0-4 when data are collected from the patient. More generally, one of the N random vectors is denoted as y.sub.n. Each of the random variable vectors y.sub.0-y.sub.4 further includes random variables representing each of the variables measured by the telehealth device. In the example of FIG. 3B, each of the vectors y.sub.0-y.sub.4 includes two random variables, T.sub.n and HR.sub.n that correspond to the temperature and heart rate of the patient 102, respectively, during each of the N time periods. In different sets of medical data for different patients, the number of random variable vectors y is selected based on the number of multivariate observations in the health data collected for the patient. Each of the random vectors y includes at least two random variables, which are exemplified as random variables corresponding to temperature and heart rate in FIG. 3A and FIG. 3B. A population of patients with telehealth devices answers a variety of different questions to provide sets of medical data to the telehealth analysis system 112 based on the medical condition of each patient and treatment. Thus, each vector of random variables y.sub.n can include a wide range of variables corresponding to the responses for each patient over time. Some embodiments that include a large number of medical data samples use a limited number of random variable vectors corresponding to the earlier samples to generate the covariance matrix. For example, if a series of 1,000 samples precedes the most current set of medical data, then one embodiment of process 200 uses the random variables from the 100 most recent medical data samples to generate a 100.times.100 matrix.”)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Vemuri to incorporate the teachings of Srinivasan to generate an estimated covariance matrix for random variables relating to changes in medical condition that a patient experiences, at least because doing so would enable more accurate estimate of missing medical data values based on the condition of the patient.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAHID KHAN whose telephone number is (571)270-0419. The examiner can normally be reached M-F, 9-5 est.
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/SHAHID K KHAN/Primary Examiner, Art Unit 2146
1 The citation format <column:lines> refers to the column and line numbers of the patent reference.
