DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is non-final and is in response to the claims filed February 1st, 2023. Claims 1-12 are pending, of which claims 1-12 are currently rejected.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Germany on 02/03/2022. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/01/2023 is in compliance with the provisions of 37 CFR 1.97. It has been placed in the application file, and the information referred to therein has been considered as to the merits.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “the result” on line 7. There is lack of antecedent basis for this limitation.
Because claims 2-9 depend upon claim 1, claims 2-9 are also are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite.
Claim 10 recites the limitation “the result” on line 6. There is lack of antecedent basis for this limitation.
Because claims 11-12 depend upon claim 10, claims 11-12 are also are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite.
Claim 12 recites the limitation “the result” on lines 2 and 4. It is unclear if this result is the same as the result recited in claim 10 or other results. For examination purposes, each mention of result will be construed to be a separate result from other recitations of “the result”. Appropriate correction required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-12 are rejected under 35 U.S.C. 103 as being unpatentable over H. Kokubo et al. ("Evaluation of ASIC Implementation of Physical Random Number Generators Using RS Latches", 2014) (hereinafter “Kokubo”), further in view of H. Zhou et al. ("Linear Transformations for Randomness Extraction", 2012) (hereinafter “Zhou”), further in view of Gammel et al. (US 2016/0210121 A1) (hereinafter “Gammel”).
Regarding claim 1, Kokubo teaches:
An integrated circuit, comprising:
multiple noise sources, each noise source being configured to output a respective set of noise bits for a random vector (Kokubo: Pg. 9 Fig. 3 multiple sets of noise bits from various noise sources are concatenated at XOR and MUX),
a combinational logic circuit configured to process a noise bit vector (Kokubo: Pg. 9 Fig. 3 xor circuit),
corresponding to a concatenation of the bits of the sets of noise bits (Kokubo: Pg. 9 Fig. 3 xor circuit carries out processing of noise bit vector)
a post-processing logic circuit configured to generate the random vector from the processed noise bit vector (Kokubo: Pg. 9 Fig. 3 2-1 multiplexer for generation of random output i.e., random vector).
Kokubo does not explicitly teach concatenation of bits of the sets being carried out through a multiplication by a matrix or the output processed noise bit vector having fewer bits than the original noise bit vector (compression).
However, Zhou teaches random binary sequence i.e., random noise vector taken from natural phenomenon sources i.e., noise sources (Zhou: Pg. 4 Col. 1 Section B further described in Pg. 4 Col. 2 Section Theorem 3), the random noise vectors taken in to be processed by multiplying with matrix for extracting randomness, combinatorial logic is carried out so the circuit would be required for hardware purposes (Zhou: Pg. 4 Col. 2 Section Theorem 3). The output of random vector is a result of multiplication by matrix, which as is known in the art would yield in more bits than original noise bits (Zhou: Pg. 4 Col. 2 Section Theorem 3).
It would be obvious before the effective filing date of the claimed invention to combine the processing of the random noise bit vectors as taught by Zhou with the integrated circuit as taught by Kokubo because both references are directed towards the generation of random numbers. One with ordinary skill in the art would be motivated to combine the teachings because this would allow for the system to have good capabilities or local correlation and increased information efficiency (Zhou: Pg. 4 Col. 2 paragraph after Theorem 4).
Kokubo in view of Zhou does not explicitly teach the processed noise bit vector having fewer bits than the noise bit vector.
However, Gammel teaches the final output random vector having less bits than the intermediate values i.e., processed random noise vector (Gammel: Claim 4).
It would be obvious before the effective filing date of the claimed invention to combine the compression of final values as taught by Gammel with the integrated circuit as taught by Kokubo in view of Zhou because all references are directed towards the generation of random numbers. One with ordinary skill in the art would be motivated to combine the teachings because this would allow for good diffusion properties and can be realized in hardware in a cost-effective way. (Gammel: ¶ 0046).
Therefore, Kokubo in view of Zhou in view of Kokubo teaches:
An integrated circuit, comprising:
multiple noise sources, each noise source being configured to output a respective set of noise bits for a random vector,
a combinational logic circuit configured to process a noise bit vector,
corresponding to a concatenation of the bits of the sets of noise bits, in accordance with a multiplication by a matrix to produce a processed noise bit vector, with the result that the processed noise bit vector comprises more bits than each of the sets of noise bits and comprises fewer bits than the noise bit vector; and
a post-processing logic circuit configured to generate the random vector from the processed noise bit vector.
Regarding claim 2, Kokubo in view of Zhou in view of Gammel further teaches:
The integrated circuit of claim 1, wherein the post-processing logic circuit is configured to generate the random vector by compressing the processed noise bit vector (Gammel: Claim 4 output random vector has less bits than intermediate value i.e., processed random noise vector).
The motivation to combine with respect to claim 1 applies equally to claim 2.
Regarding claim 3, Kokubo in view of Zhou in view of Gammel teaches:
The integrated circuit of claim 1, comprising a concatenation circuit configured to generate the noise bit vector by concatenating the bits of the sets of noise bits (Kokubo: Pg. 9 Fig. 3 multiple sets of noise bits from various noise sources are concatenated at XOR and MUX).
Regarding claim 4, Kokubo in view of Zhou in view of Gammel teaches:
The integrated circuit of claim 1, wherein the multiplication by the matrix is the multiplication of the noise bit vector from the right by a generator matrix of a linear code having a code length equal to the number of bits of the noise bit vector and a code dimension equal to the number of bits of the processed noise bit vector (Zhou: Pg. 4 Col. 2 Theorem 4 linear code C having dimension m and codeword length n (length of random noise bits), matrix has this linear code, and random noise vector is multiplied by this matrix).
The motivation to combine with respect to claim 1 applies equally to claim 4.
Regarding claim 5, Kokubo in view of Zhou in view of Gammel teaches:
The integrated circuit of claim 4, wherein the linear code is a linear code with the greatest possible minimum distance among the linear codes having the code length and the code dimension (Zhou: Pg. 12 Col. 1 first paragraph greatest possible minimum distance chosen to increase efficiency of randomness extraction based on linear code transforming for randomness extraction).
The motivation to combine with respect to claim 1 applies equally to claim 5.
Regarding claim 6, Kokubo in view of Zhou in view of Gammel teaches:
The integrated circuit of claim 1, comprising at least one further combinational logic circuit, each combinational logic circuit from the combinational logic circuit and the at least one further combinational logic circuit being configured so as, when supplied with the noise bit vector, to process the noise bit vector to produce a respective processed noise bit vector (Kokubo: Pg. 9 Fig. 3 combinational logic circuit as XOR circuit and further combinational logic circuit as 256-1 multiplexer each receiving a random bit vector and further processing it), and a selection logic circuit configured to select one combinational logic circuit from the combinational logic circuit and the at least one further combinational logic circuit and to supply the selected combinational logic circuit with the noise bit vector (Kokubo: Pg. 9 Fig. 3 interconnections between latches i.e., noise sources and combinatorial circuits show various routes of data passing through the overall circuit, data may be supplied from latches to XOR circuit or 256-1 MUX, selection circuitry would be needed in order for routing through circuit to be possible), the post-processing logic circuit being configured to generate the random vector from the noise bit vector processed by the selected combinational logic circuit (Kokubo: Pg. 9 Fig. 3 2-1 multiplexer for generation of random output i.e., random vector).
Regarding claim 7, Kokubo in view of Zhou in view of Gammel teaches interconnections between latches i.e., noise sources and combinatorial circuits show various routes of data passing through the overall circuit, data may be supplied from latches to XOR circuit or 256-1 MUX (Kokubo: Pg. 9 Fig. 3). Selection circuitry would be needed in order for routing through circuit to be possible, and as is known in the art selection circuitry (i.e., multiplexers for example) would need a selector signal (predefined parameter) in order to carry out selection and routing.
Regarding claim 8, Kokubo in view of Zhou in view of Gammel teaches:
The integrated circuit of claim 1, further comprising a processor configured to take the random vector as a basis for performing a cryptographic operation (Kokubo: Pg. 8 first paragraph, the random number generator as shown in Fig. 3 on Pg. 9 can be used for the generation of cryptographic keys).
Regarding claim 9, Kokubo in view of Zhou in view of Gammel teaches:
The integrated circuit of claim 1, wherein at least some of the noise sources are of different designs (Zhou: Pg. 3 Col. 2 Section III the random noise sources can be one of many types).
The motivation to combine with respect to claim 1 applies equally to claim 9.
Claims 10 and 11 recite the method practiced by the apparatus of claims 1 and 4 respectively and are therefore rejected for the same reasons therein.
Regarding claim 12, Kokubo in view of Zhou in view of Gammel teaches:
The method of claim 11, comprising stipulating a robustness of the generation of the random vector and ascertaining the code dimension, with the result that a linear code having a code length equal to the number of bits of the noise bit vector and the ascertained code dimension exists that has a minimum distance (Zhou: Pg. 12 Col. 1 first paragraph minimum distance i.e., robustness criteria is determined based on linear code given code dimension and length), with the result that the stipulated robustness is fulfilled (Zhou: Pg. 3 Col. 2 before Section III, fulfilling statistical distance of Y determines robustness of random numbers), and processing the noise bit vector to produce the processed noise bit vector in accordance with a multiplication of the noise bit vector from the right by a generator matrix of the linear code (Zhou: Pg. 4 Col. 2 Theorem 4 linear code C having dimension m and codeword length n (length of random noise bits), matrix has this linear code, and random noise vector is multiplied by this matrix).
The motivation to combine with respect to claim 1 applies equally to claim 12.
Prior Art Made of Record
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Matsubara et al. (US 2019/0012409 A1) teaches generation of random numbers based on energy change and thermal excitation energy, using selectors and a noise table in order to generate the random numbers.
Felix et al. (11294653) teaches a pseudo random number generator having various combinatorial logic circuits for processing pairs of bits and therethrough generating a random number.
Conclusion
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/M.D.R./Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
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