DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on October 21, 2025 has been entered.
Response to Amendment
The amendment filed on October 21, 2025 in response to the previous Office Action (05/21/2025) is acknowledged and has been entered.
Claims 1, 3 – 9 and 20 – 22, 24 – 32 are currently pending.
Claims 2, 10 – 19 and 23 are cancelled.
Response to Arguments
Applicant's arguments filed October 21, 2025 have been fully considered but they are not persuasive.
Applicant submits that based on the amendments, the claims thus now each require that at least three distinct "pixel blocks," each of which includes at least a "photoelectric conversion unit" and a "transfer transistor" or "reset transistor," be arranged on the "first semiconductor substrate." And, as noted in Applicant's prior replies, each recited "transfer transistor" or "reset transistor" is required to be connected to different control wiring” (see Remarks p. 12).
Examiner respectfully disagrees.
The amended claims do specify different wirings and the specification discloses (although not explicitly shown in the Drawings) different wirings for pixels in different unit pixels blocks that each having multiple pixels arranged in an array. Applicant’s claims do not specify multiple unit pixels, each with multiple pixels arranged in an array, wherein each unit pixel has separate and different transfer control lines from the other unit pixels. As currently written, claims only require first, second and third pixel blocks (block not defined), each with one PD, and transfer transistor. Iwane teaches (see figure 2) PD and Tx combinations D11/M111, D12/M112, D13/M113 (first block) connected to transfer control PTX1, PD and Tx combinations D21/M121, D22/M122, D23/M123 (second block) connected to transfer control PTX2, PD and Tx combinations D31/M131, D32/M132, D33/M133 (third block) connected to transfer control PTX3. Thus, Iwane reads on the current claims.
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
Claim 1, 3 – 4, 6 – 7, 9, 20 – 28 and 30 – 32 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Iwane et al. (US 2013/0222631) in view of Iwabuchi et al. (US 2010/0276572).
Regarding claim 1, Iwane et al. disclose an image sensor in which a plurality of semiconductor substrates are stacked, the plurality of semiconductor substrates comprising: a first pixel block having a first photoelectric conversion unit (D11) that converts light into an electric charge (¶26: pixel unit PU on the first row and first column includes at least one photoelectric conversion element D11) and a first transfer transistor (M111) for transferring the electric charge converted by the first photoelectric conversion unit (¶26: pixel unit PU on the first row and first column includes at least one photoelectric conversion element D11, a transfer transistor M111, a reset transistor M211, a source follower transistor M311, and a selection transistor M411); a second pixel block having a second photoelectric conversion unit (D21) that converts light into an electric charge (¶26) and a second transfer transistor (M121) for transferring the electric charge converted by the second photoelectric conversion unit (¶26); and a third pixel block having a third conversion unit (D31) that converts light into an electric charge (¶26) and a third transfer transistor (M131) for transferring the electric charge converted by the third photoelectric conversion unit (¶26); and a first conversion unit that converts a first signal that is based on the electric charge converted by the first photoelectric conversion unit into a digital signal; a second conversion unit that converts a second signal that is based on the electric charge converted by the second photoelectric conversion unit into a digital signal; and a third conversion unit that converts a third signal that is based on the electric charge converted by the third photoelectric conversion unit into a digital signal (¶25-27, 79: a plurality of processing portions 18 each of which corresponds to each of the plurality of columns of the pixel array 10… processing portion can include, for example, an A/D converter, and a processor for processing digital data output from the A/D converter), wherein: the first photoelectric conversion unit, the second photoelectric conversion unit, and the third photoelectric conversion unit are arranged along a row direction in the first semiconductor substrate (fig. 2); the first transfer transistor is provided with a gate electrically connected to a first transfer control wiring to which a first transfer control signal for controlling the first transfer operation is output (connected to PTX1); the second transfer transistor is provided with a gate electrically connected to a second transfer control wiring that is different from the first transfer control wiring and to which a second transfer control signal for controlling the second transfer operation is output (connected to PTX2); and the third transfer transistor is provided with a gate electrically connected to a third transfer control wiring that is different from the first and second transfer control wiring and to which a third transfer control signal for controlling the third transfer operation is output (connected to PTX3). Iwane fails to explicitly disclose a plurality of semiconductor substrates stacked including a first semiconductor substrate; and a second substrate.
In the same field of endeavor, Iwabuchi teaches a semiconductor image sensor module is provided by stacking a first semiconductor chip, which has an image sensor wherein a plurality of pixels composed of a photoelectric conversion element and a transistor are arranged, and a second semiconductor chip, which has an A/D converter array. Preferably, the semiconductor image sensor module is provided by stacking a third semiconductor chip having a memory element array (abstract; fig. 1) Iwabuchi also teaches in CMOS image sensor 60 pixel separation regions 62 are formed in an imaging region 59 of a thinned semiconductor substrate and a plurality of MOS transistors Tr, each of which is composed of an n-type source-drain region 64, a gate insulation film 65, and a gate electrode 66, are formed in a p-type semiconductor well region 63 of each pixel region wherein these MOS transistors Tr may be constituted by, for example, 3 transistors, i.e., a readout transistor having a source-drain region, which becomes a floating diffusion region FD, a reset transistor, and an amplifier transistor, or 4 transistors, i.e., the aforementioned 3 transistors and a vertical selection transistor (¶90). In light of the teaching of Iwabuchi, it would have been obvious to one of ordinary skill in the art, before the invention was made, to use Iwabuchi’s teachings in Iwane’s system because an artisan of ordinarily skill would recognize that this would result in an increase of chip use efficiency, higher sensitivity and cost reduction.
Regarding claim 3, Iwane et al. in view of Iwabuchi et al. disclose all of the aforementioned limitations of claim 1. Iwane also teaches wherein: a first reset transistor (M211) is used for discharging the electric charge converted by the first photoelectric conversion unit to a supply wiring to which a predetermined voltage is supplied; a second reset transistor (M212) is used for discharging the electric charge converted by the second photoelectric conversion unit to a supply wiring; and a third reset transistor (M213) is used for discharging the electric charge converted by the third photoelectric conversion unit to a supply wiring (¶26: A control signal PRES1 is supplied to the gate terminal of the reset transistor M211. When the control signal PRES1 is activated, the reset transistor M211 can reset the potential of the gate terminal of the source follower transistor M311. This also applies to the remaining pixel units PU); wherein: the first reset transistor is connected to a first reset control wiring to which a first reset control signal is output (connected to PRES1); the second reset transistor is connected to a second reset control wiring to which a second reset control signal is output (connected to PRES1); and the third reset transistor is connected to a third reset control wiring to which a third reset control signal is output (connected to PRES1).
Regarding claim 4, Iwane et al. in view of Iwabuchi et al. disclose all of the aforementioned limitations of claim 3. Iwane fails to explicitly disclose wherein: a timing at which the first transfer control signal is output to the first transfer control wiring is different from a timing at which the second transfer control signal is output to the second transfer control wiring; and a timing at which the first reset control signal is output to the first reset control wiring is different from a timing at which the second reset control signal is output to the second reset control wiring.
In the same field of endeavor, Iwabuchi teaches signals are inputted sequentially to the analog/digital converter 165 corresponding to the pixel array block 164 starting from the head memory cell according to readout control signals, and digital signals are outputted (¶125). In light of the teaching of Iwabuchi, it would have been obvious to one of ordinary skill in the art, before the invention was made, to use Iwabuchi’s teachings in Iwane’s system because an artisan of ordinarily skill would recognize that this would result in an increase of chip use efficiency, higher sensitivity and cost reduction.
Regarding claim 6, Iwane et al. in view of Iwabuchi et al. disclose all of the aforementioned limitations of claim 4. Iwane also teaches further comprising: a first output wiring for outputting the first signal to the first conversion unit (fig. 2; ¶27); a second output wiring for outputting the second signal to the second conversion unit (fig. 2; ¶27 and a second output wiring for outputting the second signal to the second conversion unit (fig. 2; ¶27).
Regarding claim 7, Iwane et al. in view of Iwabuchi et al. disclose all of the aforementioned limitations of claim 1. Iwane fails to explicitly disclose wherein: a timing at which the first transfer control signal is output to the first transfer control wiring is different from a timing at which the second transfer control signal is output to the second transfer control wiring.
In the same field of endeavor, Iwabuchi teaches signals are inputted sequentially to the analog/digital converter 165 corresponding to the pixel array block 164 starting from the head memory cell according to readout control signals, and digital signals are outputted (¶125). In light of the teaching of Iwabuchi, it would have been obvious to one of ordinary skill in the art, before the invention was made, to use Iwabuchi’s teachings in Iwane’s system because an artisan of ordinarily skill would recognize that this would result in an increase of chip use efficiency, higher sensitivity and cost reduction.
Regarding claim 9, Iwane et al. in view of Iwabuchi et al. disclose all of the aforementioned limitations of claim 7. Iwane also teaches further comprising: a first output wiring for outputting the first signal to the first conversion unit (fig. 2; ¶27); a second output wiring for outputting the second signal to the second conversion unit (fig. 2; ¶27 and a second output wiring for outputting the second signal to the second conversion unit (fig. 2; ¶27).
Regarding claim 20, Iwane et al. in view of Iwabuchi et al. disclose all of the aforementioned limitations of claim 1. Iwane fails to explicitly disclose a control unit connected to the image sensor.
In the same field of endeavor, Iwabuchi teaches Each of the pixel array 121, the analog/digital converter array 122, the memory array 123, and the digital signal processing device 124 is controlled by a control circuit 125 (fig. 5; ¶101). In light of the teaching of Iwabuchi, it would have been obvious to one of ordinary skill in the art, before the invention was made, to use Iwabuchi’s teachings in Iwane’s system because an artisan of ordinarily skill would recognize that this would result in an increase of chip use efficiency, higher sensitivity and cost reduction.
Regarding claim 21, Iwane et al. in view of Iwabuchi et al. disclose all of the aforementioned limitations of claim 3. Iwabuchi also teaches wherein: the first reset transistor, the second reset transistor, and the third reset transistor are arranged on the first semiconductor substrate (fig. 1; ¶89-90: image sensor of the first semiconductor chip 52 in this example is constituted by a so-called back-illuminated type CMOS image sensor in which a transistor forming region 56, in which transistors constituting a unit pixel are formed…Tr may be constituted by, for example, 3 transistors, i.e., a readout transistor having a source-drain region, which becomes a floating diffusion region FD, a reset transistor, and an amplifier transistor, or 4 transistors, i.e., the aforementioned 3 transistors and a vertical selection transistor).
Regarding claim 22, Iwane et al. in view of Iwabuchi et al. disclose all of the aforementioned limitations of claim 4. Iwabuchi also teaches wherein: a timing at which the second transfer control signal is output to the second transfer control wiring is different from a timing at which the third transfer control signal is output to the third transfer control wiring; and a timing at which the second reset control signal is output to the second reset control wiring is different from a timing at which the third reset control signal is output to the third reset control wiring (¶25: signals are inputted sequentially to the analog/digital converter 165 corresponding to the pixel array block 164 starting from the head memory cell according to readout control signals, and digital signals are outputted).
Regarding claim 24, Iwane et al. in view of Iwabuchi et al. disclose all of the aforementioned limitations of claim 7. Iwane fails to explicitly disclose wherein: a timing at which the second transfer control signal is output to the second transfer control wiring is different from a timing at which the third transfer control signal is output to the third transfer control wiring.
In the same field of endeavor, Iwabuchi teaches signals are inputted sequentially to the analog/digital converter 165 corresponding to the pixel array block 164 starting from the head memory cell according to readout control signals, and digital signals are outputted (¶125). In light of the teaching of Iwabuchi, it would have been obvious to one of ordinary skill in the art, before the invention was made, to use Iwabuchi’s teachings in Iwane’s system because an artisan of ordinarily skill would recognize that this would result in an increase of chip use efficiency, higher sensitivity and cost reduction.
Regarding claim 25, Iwane et al. in view of Iwabuchi et al. disclose all of the aforementioned limitations of claim . Iwane also teaches wherein: the second semiconductor substrate has arranged thereon (i) a first load current source (Ib11/Ib21) that supplies a current to the first output wiring (fig. 3; ¶27, 29); (ii) a second load current source (Ib/11Ib21) that supplies a current to the second output wiring (fig. 3; ¶27, 29); and (iii) a third load current source (Ib11/Ib21) that supplies a current to the third output wiring (fig. 3; ¶27, 29: for convenience only 2x2 pixels shown).
Claim 26 is rejected for the same reasons as to claims 3 (and all claims from which it depends) above.
Regarding claim 27, Iwane et al. in view of Iwabuchi et al. disclose all of the aforementioned limitations of claim 26. Iwabuchi also teaches a timing at which the first reset control signal is output to the first reset control wiring is different from a timing at which the second reset control signal is output to the second reset control wiring (¶25: signals are inputted sequentially to the analog/digital converter 165 corresponding to the pixel array block 164 starting from the head memory cell according to readout control signals, and digital signals are outputted).
Regarding claim 28, Iwane et al. in view of Iwabuchi et al. disclose all of the aforementioned limitations of claim 27. Iwabuchi also teaches wherein: a timing at which the second reset control signal is output to the second reset control wiring is different from a timing at which the third reset control signal is output to the third reset control wiring (¶25: signals are inputted sequentially to the analog/digital converter 165 corresponding to the pixel array block 164 starting from the head memory cell according to readout control signals, and digital signals are outputted).
Regarding claim 30, Iwane et al. in view of Iwabuchi et al. disclose all of the aforementioned limitations of claim 26. Iwane also teaches further comprising: a first output wiring for outputting the first signal to the first conversion unit (fig. 2; ¶27); a second output wiring for outputting the second signal to the second conversion unit (fig. 2; ¶27 and a second output wiring for outputting the second signal to the second conversion unit (fig. 2; ¶27).
Regarding claim 31, Iwane et al. in view of Iwabuchi et al. disclose all of the aforementioned limitations of claim 30. Iwane also teaches wherein: the second semiconductor substrate has arranged thereon (i) a first load current source (Ib11/Ib21) that supplies a current to the first output wiring (fig. 3; ¶27, 29); (ii) a second load current source (Ib/11Ib21) that supplies a current to the second output wiring (fig. 3; ¶27, 29); and (iii) a third load current source (Ib11/Ib21) that supplies a current to the third output wiring (fig. 3; ¶27, 29: for convenience only 2x2 pixels shown).
Regarding claim 32, Iwane et al. in view of Iwabuchi et al. disclose all of the aforementioned limitations of claim 26. Iwane fails to explicitly disclose a control unit connected to the image sensor.
In the same field of endeavor, Iwabuchi teaches Each of the pixel array 121, the analog/digital converter array 122, the memory array 123, and the digital signal processing device 124 is controlled by a control circuit 125 (fig. 5; ¶101). In light of the teaching of Iwabuchi, it would have been obvious to one of ordinary skill in the art, before the invention was made, to use Iwabuchi’s teachings in Iwane’s system because an artisan of ordinarily skill would recognize that this would result in an increase of chip use efficiency, higher sensitivity and cost reduction.
Claims 5, 8 and 29 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Iwane et al. (US 2013/0222631) in view of Iwabuchi et al. (US 2010/0276572) in view of Hirama et al. (US 2013/0002936).
Regarding claim 5, Iwane et al. in view of Iwabuchi et al. disclose all of the aforementioned limitations of claim 4. The combination fails to explicitly disclose wherein: the first signal converted to the digital signal in the first conversion unit is used for focus detection of an optical system; and the second signal converted to the digital signal in the second conversion unit is used for image generation.
In the same field of endeavor, Hirama teaches each of the AF pixels 41 outputs a pupil-divided detection signal of the left side or the right side in accordance with a brightness of white light and a semiconductor image sensor of CCD or CMOS in which the primary color transmission filter 19 of any one of R (red), G (green), and B (blue) is arranged, in a Bayer pattern, on each of a plurality of imaging pixels which are provided on a light-receiving surface of the semiconductor image sensor wherein the imaging element 17 can individually read pixel signals from the imaging pixel group, and the AF pixel group (¶39-41). In light of the teaching of Hirama, it would have been obvious to one of ordinary skill in the art, before the invention was made, to use Hirama’s teachings in Iwane’s system because an artisan of ordinarily skill would recognize that this would result in images that do not give a sense of strangeness to the eyes of a user.
Regarding claim 8, Iwane et al. in view of Iwabuchi et al. disclose all of the aforementioned limitations of claim 7. The combination fails to explicitly disclose wherein: the first signal converted to the digital signal in the first conversion unit is used for focus detection of an optical system; and the second signal converted to the digital signal in the second conversion unit is used for image generation.
In the same field of endeavor, Hirama teaches each of the AF pixels 41 outputs a pupil-divided detection signal of the left side or the right side in accordance with a brightness of white light and a semiconductor image sensor of CCD or CMOS in which the primary color transmission filter 19 of any one of R (red), G (green), and B (blue) is arranged, in a Bayer pattern, on each of a plurality of imaging pixels which are provided on a light-receiving surface of the semiconductor image sensor wherein the imaging element 17 can individually read pixel signals from the imaging pixel group, and the AF pixel group (¶39-41). In light of the teaching of Hirama, it would have been obvious to one of ordinary skill in the art, before the invention was made, to use Hirama’s teachings in Iwane’s system because an artisan of ordinarily skill would recognize that this would result in images that do not give a sense of strangeness to the eyes of a user.
Regarding claim 29, Iwane et al. in view of Iwabuchi et al. disclose all of the aforementioned limitations of claim 26. The combination fails to explicitly disclose wherein: the first signal converted to the digital signal in the first conversion unit is used for focus detection of an optical system; and the second signal converted to the digital signal in the second conversion unit is used for image generation.
In the same field of endeavor, Hirama teaches each of the AF pixels 41 outputs a pupil-divided detection signal of the left side or the right side in accordance with a brightness of white light and a semiconductor image sensor of CCD or CMOS in which the primary color transmission filter 19 of any one of R (red), G (green), and B (blue) is arranged, in a Bayer pattern, on each of a plurality of imaging pixels which are provided on a light-receiving surface of the semiconductor image sensor wherein the imaging element 17 can individually read pixel signals from the imaging pixel group, and the AF pixel group (¶39-41). In light of the teaching of Hirama, it would have been obvious to one of ordinary skill in the art, before the invention was made, to use Hirama’s teachings in Iwane’s system because an artisan of ordinarily skill would recognize that this would result in images that do not give a sense of strangeness to the eyes of a user.
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/ANTOINETTE T SPINKS/ Primary Examiner, Art Unit 2639