DETAILED ACTION
This office action is in response to the amendment filed on 15 October, 2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 15 October, 2025 have been fully considered but they are not persuasive.
Regarding the rejection of claim 1 under 35 U.S.C. 102, Applicant argues that “Terry and Tu at least fail to disclose a voltage regulation integrated circuit in which a first capacitor configured to extract the AC component so as to generate the coupling voltage, a value of the AC component extracted by the first capacitor is determined by an impedance of the first capacitor; the bias circuit generates the first bias voltage at a first node, the amplifier circuit receives the first bias voltage from a second node.” (Remarks, pg. 2). The Examiner respectfully disagrees.
Terry disclose a voltage regulation integrated circuit comprises a first capacitor (e.g. capacitor 385) (fig. 4a) configured to extract the AC component so as to generate the coupling voltage, a value of the AC component extracted by the first capacitor is determined by an impedance of the first capacitor (describes a fundamental electrical property impedance (Z) of a capacitor is given by the formula Z = 1/(jωC), where j is the imaginary unit, ω is the angular frequency, and C is the capacitance), the bias circuit (e.g. current source 314 connected to transistor 398 sends bias voltage from the gate of transistor 398)(fig. 4a) generates the first bias voltage at a first node (e.g. current source 314 connected to transistor 398 sends bias voltage from the gate of transistor 398) (fig. 4a), the amplifier circuit (e.g. differential input pair 372, 378 and subsequent gain stage including transistors 352, 358) (fig. 4a) receives the first bias voltage from a second node (e.g. explicitly shown by the bias line coming from the gate of transistor 298 to the gate of transistor 362) (fig. 4a), and the transient coupling circuit (e.g. high speed feedback path including capacitor 385) (fig. 4a) assists the change of the voltage at the second node (e.g. the gate of transistor 362) (fig. 4a). In figure 4a of Terry’s linear regulator with improved transient response, capacitor 385 is coupled to the gate of transistor 362, thereby assisting the change of the voltage at the second node. Tu was not utilized to disclose these features.
Applicant argues that “the present application does not need to wait for another capacitor to perform integration, and is thus capable of responding to load variations more rapidly.” (Remarks, pg. 6). In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Applicant argues that “Terry does not disclose that, when an AC input is applied, the feedback capacitor 385 can accelerate the integration of capacitor 325 according to the frequency of the AC signal (the AC component) and output a voltage to the gate of transistor 332” (Remarks, pg. 7.). In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Examiner does note that, as stated in the previous office action, the capacitor’s capability to extract the AC component of the output depending on the frequency of the AC signal is an inherent electrical property of a capacitor (inferred by the impedance formula Z = 1/(jωC), where j is the imaginary unit, ω is the angular frequency, and C is the capacitance). As said in Terry, paragraph [0038], a change in the output of capacitor 385 causes a change in transistors 338 and 362 which causes a change in capacitor 325. Combining the inherent electrical property of a capacitor and paragraph [0038], the feedback capacitor 385 can accelerate the integration of capacitor 325 according to the frequency of the AC signal.
Claim Objections
Claim 1 objected to because of the following informalities: “[[the]]a” should read “[[the]]a”. Appropriate correction is required.
Claim Rejections - 35 USC§ 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 5-9, and 19-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Terry (US20080180080A1).
Regarding claim 1, Terry teaches a voltage regulation integrated circuit (IC) (e.g. linear voltage regulator 300) (fig. 4a) comprising: a first transistor (e.g. pass transistor 332) (fig. 4a) configured to generate an output voltage (e.g. voltage output 320) (fig. 4a) according to an input voltage (e.g. VDD 304) (fig. 4a) and a control voltage (e.g. voltage at the gate of transistor 332) (fig. 4a0; a feedback circuit (e.g. the direct electrical connection from voltage output 320 to the gate of transistor 372) (fig. 4a) configured to generate a feedback voltage (e.g. voltage at the gate of transistor 372) (fig. 4a) according to the output voltage, wherein the output voltage comprises an AC component ( paragraph 0008, “a variable load is electrically coupled to the regulated voltage output node”; a variable load will lead to fluctuations in the regulated voltage output, which means the output voltage will comprise an AC component.); a bias circuit (e.g. current source 314 connected to transistor 398 sends bias voltage from the gate of transistor 398 to implicitly shown node 1) (fig. 4a) and configured to generate a first bias voltage (e.g. voltage at the gate or transistor 398) (fig. 4a); an amplifier circuit (e.g. differential input pair 372, 378 and subsequent gain stage including transistors 352, 358) (fig. 4a) configured to generate a control voltage (e.g. voltage at the gate of transistor 332) (fig. 4a) according to the first bias voltage (e.g. voltage from the gate of transistor 398 moving toward transistor 362) (fig. 4a) and the feedback voltage (e.g. voltage from VOUT 320) (fig. 4a); and a transient coupling circuit (e.g. high speed feedback path including capacitor 385) (fig. 4a) configured to generate a coupling voltage (e.g. voltage generated by capacitor 385) (fig. 4a) according to the AC component and to assist the change of the first bias voltage according to the coupling voltage, so that the output voltage is maintained at a voltage level; wherein the transient coupling circuit (e.g. high speed feedback path including capacitor 385) (fig. 4a) comprises a first capacitor (e.g. capacitor 385) (fig. 4a) configured to extract the AC component so as to generate the coupling voltage, a value of the AC component extracted by the first capacitor is determined by an impedance of the first capacitor (describes a fundamental electrical property impedance (Z) of a capacitor is given by the formula Z = 1/(jωC), where j is the imaginary unit, ω is the angular frequency, and C is the capacitance), the bias circuit (e.g. current source 314 connected to transistor 398 sends bias voltage from the gate of transistor 398)(fig. 4a) generates the first bias voltage at a first node (e.g. current source 314 connected to transistor 398 sends bias voltage from the gate of transistor 398) (fig. 4a), the amplifier circuit (e.g. differential input pair 372, 378 and subsequent gain stage including transistors 352, 358) (fig. 4a) receives the first bias voltage from a second node (e.g. explicitly shown by the bias line coming from the gate of transistor 298 to the gate of transistor 362) (fig. 4a), and the transient coupling circuit (e.g. high speed feedback path including capacitor 385) (fig. 4a) assists the change of the voltage at the second node (e.g. the gate of transistor 362) (fig. 4a). In figure 4a of Terry’s linear regulator with improved transient response, capacitor 385 is coupled to the gate of transistor 362, thereby assisting the change of the voltage at the second node.
The capacitor 385 in Terry’s figure 4a is connected between the voltage output 320 and the gate of transistor 338, which is coupled to the gate of transistor 362. Therefore, the capacitor 385 is configured to generate a coupling voltage from the AC component of the output voltage and apply it to the bias node for transistor 362. Thus, directly “assists the change of the first bias voltage” to provide a rapid response to load changes.
Regarding claim 5, Terry teaches the voltage regulation integrated circuit according to claim 1 (e.g. linear voltage regulator 300) (fig. 4a) further comprising a cut-off impedance (e.g. resistor 369) (fig. 4a) between a first node (e.g. implicitly shown after the gate of transistor 398) (fig. 4a) and a second node (implicitly shown after resistor 369).
Regarding claim 6, Terry teaches the voltage regulation integrated circuit according to claim 1 (e.g. linear voltage regulator 300) (fig. 4a), wherein the amplifier circuit (e.g. differential input pair 372, 378 and subsequent gain stage) (fig. 4a) comprises: an input circuit (e.g. the differential input pair 372, 378 and its associated load circuitry including transistors 362, 368, 342, 348) (fig. 4a) configured to generate a pre-voltage (e.g. the voltage at the drain of transistor 378) (fig. 4a) according to the feedback voltage (e.g. voltage output 320 applied to the gate of transistor 372) (fig. 4a) and a reference voltage (e.g. voltage reference 310 applied to the gate of transistor 378) (fig. 4a); and a gain circuit (e.g. the output stage including current mirror 354 with transistors 352, 358) (fig. 4a) ([0035]) configured to generate the control voltage (e.g. the voltage at the gate of pass transistor 332) (fig. 4a) according to the pre-voltage (e.g. the voltage at the drain of transistor 378) (fig. 4a) and the first bias voltage (e.g. the bias voltage at the gate of the transistor 398, which controls transistor 362) (fig. 4a).
Regarding claim 7, Terry teaches the voltage regulation integrated circuit according to claim 6 (e.g. linear voltage regulator 300) (fig. 4a), wherein the input circuit (e.g. the differential input pair 372, 378 and its associated load circuitry) (fig. 4a) comprises: a differential transistor pair (e.g. transistors 372 and 378) (fig. 4a) configured to generate a feedback current (e.g. the drain current of transistor 372) (fig. 4a) according to the feedback voltage (e.g. voltage output 320 applied to the gate of transistor 372) (fig. 4a); and a first current mirror circuit (e.g. current mirror 354, comprising transistors 352, 358) (fig. 4a) configured to generate a mirrored current (e.g. the drain current of transistor 352) (fig. 4a) according to the feedback current (e.g. the drain current of transistor 372), wherein the differential transistor pair generates the pre-voltage (e.g. the voltage at the drain of transistor 378) (fig. 4a) according to the reference voltage (e.g. voltage reference 310) fig. 4a) and the mirrored current (e.g. the drain current of transistor 352) (fig. 4a).
Regarding claim 8, Terry teaches the voltage regulation integrated circuit according to claim 7 (e.g. linear voltage regulator 300) (fig. 4a), wherein the differential transistor pair (e.g. transistors 372 and 378) (fig. 4a) comprises: a second transistor (e.g. transistor 372) (fig. 4a) comprising: a second output end (e.g. the drain of transistor 372) (fig. 4a) electrically connected to the first current mirror circuit (e.g. current mirror 354, transistors 358 and 352) (fig. 4a) ([0035]); and a second control end (e.g. the gate of transistor 372) (fig. 4a) configured to receive the feedback voltage (e.g. voltage output 320) (fig. 4a), wherein the second transistor is configured to generate the feedback current (e.g. the drain current of transistor 372) at the second output end according to the feedback voltage; and a third transistor (e.g. transistor 378) (fig. 4a) comprising: a third output end (e.g. the drain of transistor 378) (fig. 4a) electrically connected to the first current mirror circuit (e.g. current mirror 354) (fig. 4a) and the gain circuit (e.g. the output stage including transistors 352, 358) (fig. 4a); and a third control end (e.g. the gate of transistor 378) (fig. 4a) configured to receive the reference voltage (e.g. voltage reference 310) (fig. 4a), wherein the third transistor (e.g. transistor 378) (fig. 4a) is configured to generate the pre-voltage (e.g. the voltage at the drain of transistor 378) (fig. 4a) at the third output end (e.g. the drain of transistor 378) (fig. 4a) according to the reference voltage (e.g. voltage reference 310) fig. 4a) and the mirrored current (e.g. the drain current of transistor 352) (fig. 4a).
Regarding claim 9, Terry teaches the voltage regulation integrated circuit according to claim 8 (e.g. linear voltage regulator 300) (fig. 4a), wherein the bias circuit (e.g. the biasing circuitry including current source 314) (fig. 4a) further generates a second bias voltage (e.g. the voltage at the gate of transistor 388) (fig. 4a), and the input circuit ( e.g. the differential input pair 372, 378) (fig. 4a) further comprises a first current source circuit (e.g. current mirror 384 comprising transistors 382 and 388) (fig. 4a) ([0034]) configured to generate a first bias current (e.g. the drain current of transistor 372) (fig. 4a) and a second bias current (e.g. the drain current of transistor 378) (fig. 4a) according to the second bias voltage (e.g. the voltage at the gate of transistor 388) (fig. 4a); wherein the second transistor (e.g. transistor 372) (fig. 4a) generates the feedback current (e.g. the drain current of transistor 372) (fig. 4a) at the second output end (e.g. the drain of transistor 372) (fig. 4a) according to the feedback voltage (e.g. voltage output 320) (fig. 4a) and the first bias current (e.g. the drain current of transistor 372) (fig. 4a), and the third transistor (e.g. transistor 378) (fig. 4a) generates the pre-voltage (e.g. the voltage at the drain of transistor 378) (fig. 4a) at the third output end (e.g. the drain of transistor 378) (fig. 4a) according to the reference voltage (e.g. voltage reference 310) (fig. 4a), the mirrored current (e.g. the drain current of transistor 352) (fig. 4a), and the second bias current (e.g. the drain current of transistor 378) (fig. 4a).
Regarding claim 13, Terry teaches the voltage regulation integrated circuit according to claim 6 (e.g. linear voltage regulator 300) (fig. 4a), wherein the gain circuit (e.g. the output stage including transistors 352, 358) (fig. 4a) comprises: a second current source circuit (e.g. transistor 362) (fig. 4a) configured to generate a fourth bias current (e.g. the drain current of transistor 362) (fig. 4a) according to the first bias voltage (e.g. the bias voltage at the gate of transistor 398) (fig. 4a); and a gain sub circuit (e.g. the combination of transistors 342 and 352) (fig. 4a) configured to generate the control voltage (e.g. the voltage at the gate of transistor 332) (fig. 4a) according to the pre-voltage (e.g. the voltage at the drain of transistor 378) (fig. 4a) and the fourth bias current (the drain current of transistor 362) (fig. 4a).
Regarding claim 14, Terry teaches the voltage regulation integrated circuit according to claim 13 (e.g. linear voltage regulator 300) (fig. 4a), wherein the second current source circuit (e.g. transistor 362) (fig. 4a) comprises a sixth transistor (e.g. transistor 362) (fig. 4a), and the sixth transistor comprises: a sixth control end (e.g. the gate of transistor 362) (fig. 4a) configured to receive the first bias voltage (e.g. the bias voltage at the gate of transistor 398 connected to the cut-off impedance 369, which is connected to the gate of transistor 362) (fig. 4a), wherein the sixth transistor is configured to generate the fourth bias current (e.g. the current at the drain of transistor 362) (fig. 4a) according to the first bias voltage; and a sixth output end (e.g. the drain of transistor 362) (fig. 4a) electrically connected to the gain sub circuit (e.g. transistor 342) (fig. 4a) and the first transistor (e.g. transistor 332) (fig. 4a) so as to transmit the fourth bias current to the gain sub circuit.
Regarding claim 15, Terry teaches the voltage regulation integrated circuit according to claim 14 (e.g. linear voltage regulator 300) (fig. 4a), wherein the gain sub circuit (e.g. transistors 342 and 352) (fig. 4a) comprises: a seventh transistor (e.g. transistor 352) (fig. 4a) comprising: a seventh control end (e.g. the gate of transistor 352) (fig. 4a) configured to receive the pre-voltage (e.g. the voltage at the drain of transistor 378) (fig. 4a); and a seventh output end (e.g. the drain of transistor 352) (fig. 4a) electrically connected to the sixth output end (e.g. the drain of transistor 362) (fig. 4a) and the first transistor (e.g. transistor 332) (fig. 4a), wherein the seventh transistor (e.g. transistor 352) (fig. 4a) is configured to generate the control voltage (e.g. voltage at the gate of transistor 332) (fig. 4a) at the seventh output end (e.g. the drain of transistor 352) (fig. 4a) according to the pre-voltage (e.g. the voltage at the drain of transistor 378) (fig. 4a) and the fourth bias current (e.g. the current at the drain of transistor 362) (fig. 4a).
Regarding claim 20, Terry teaches the voltage regulation integrated circuit according to claim 1 (e.g. linear voltage regulator 300) (fig. 4a), wherein the bias circuit (e.g. the biasing circuitry including current source 314 and transistor 398) (fig. 4a) comprises: a third current source circuit (e.g. current source 314) (fig. 4a) configured to output a pre-set current; and a fifteenth transistor (e.g. transistor 398) (fig. 4a) configured to generate the first bias voltage (e.g. the bias voltage at the gate of transistor 398) (fig. 4a) according to the pre-set current.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Terry (US20080180080A1) in view of Tu (CN116257115A).
Regarding claim 19, Terry teaches the voltage regulation integrated circuit according to claim 1 (e.g. linear voltage regulator 300) (fig. 4a),
Terry does not teach wherein the feedback circuit comprises a first divider impedance, a second divider impedance, and a fifth node, the fifth node is between the first divider impedance and the second divider impedance, and the first divider impedance and the second divider impedance generate the feedback voltage at the fifth node according to the output voltage. Tu teaches, in a similar field of endeavor, a voltage regulator and transient enhancement circuit, wherein the feedback circuit (e.g. feedback circuit made of two resistors R3 and R4 connected to VOUT and connected to the drain of transistor MPA) (fig. 6 and 8) comprises a first divider impedance (e.g. feedback resistor R3) (fig. 6 and 8), a second divider impedance (e.g. feedback resistor R4) (fig. 6 and 8), and a fifth node, the fifth node (e.g. connection between the two feedback resistors and generates feedback voltage VFB) (fig. 6 and 8) is between the first divider impedance and the second divider impedance, and the first divider impedance and the second divider impedance generate the feedback voltage ( e.g. feedback voltage VFB) (fig. 6 and 8) at the fifth node according to the output voltage (e.g. output voltage VOUT) (fig. 6 and 8). It would have been obvious to a person of ordinary skill I the art, before the effective filing date, to modify the voltage regulator taught by Terry to further include wherein the feedback circuit comprises a first divider impedance, a second divider impedance, and a fifth node, the fifth node is between the first divider impedance and the second divider impedance, and the first divider impedance and the second divider impedance generate the feedback voltage at the fifth node according to the output voltage as taught by Tu to improve adjustability of the feedback path.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MONICA LEWIS/Supervisory Patent Examiner, Art Unit 2838
/JARED RAYMOND HAUSMAN/Examiner, Art Unit 2838