Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, it is unclear because there is no antecedent basis for “the 1-hot path signature accelerator” at lines 5-6. Claims 2-20 are rejected because they depend on claim 1 and therefore include the same issue. Claim 9 also includes path signature accelerator language that lacks antecedent basis.
Claim 9 is also unclear because it refers to a logarithm of a path signature. Based on the specification, both the first accumulator and the second accumulator appear to both output a path signature when interpreted in view of the disclosure and figures. It is unclear which accumulator is providing the path signature for which the log signature is calculated.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-6 and 9 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Claim 1:
As to step 1, claim 1 falls into one of the four statutory categories because it is directed to an apparatus/machine. It is noted that dependent claims 2-6 and 8-9 also fall into one of the four statutory categories because they depend on claim 1.
At step (2)(a) prong 2, claim 1 recites an abstract idea as follows (with the abstract idea shown as italicized language):
a register for storing a 1-hot signal, the 1-hot signal having, at most, one bit of each element set of an input frame;
Mathematical Relationship – the italicized language describes in words the mathematical characteristics of the binary numbers stored in the register
a first accumulator for calculating a present summation by adding the input frame to a previous sum, wherein the previous sum is the sum of all previous input frames inputted to the 1- hot path signature accelerator within a timeframe;
Mathematical
Calculation
an outer product circuit that receives each element of the present summation from the first accumulator and each element of the 1-hot signal stored in the register to output a present outer product, wherein the outer product circuit is reduced to a logical operation by the 1-hot signal of the input frame having at most one bit of each element set; and
Mathematical
Calculation
a second accumulator that outputs a present second-layer summation by adding the present outer product to a previous second-layer sum of outputs from the outer product circuit within the timeframe.
Mathematical
Calculation
At step 2(a) prong 2, the judicial exception recited in claim 1 is not integrated into a practical application. Although claim 1 recites the additional element of a “register” for storing the 1-hot signal, this limitation amounts to necessary data gathering for subsequent mathematical operations using a type of extra-solution limitation that is well known. Moreover, the use of a register to store the 1-hot binary values representing the signal imposes no meaningful limits on the claim such that it is not nominally or tangentially related to the invention. As a consequence, this register is not significant. Although claim 1 does recite the additional elements of a first accumulator, an outer product circuit, and a second accumulator, these circuit elements are recited at a high level of generality and amount to mere instructions to “apply it” by using the type of circuit element normally used to perform that type of mathematical function. The circuit elements are merely a direct consequence of the abstract idea and merely serve to perform the mathematical calculation of the abstract idea recited in the claim. Even when viewed in combination, these additional elements do not integrate the recited judicial into a practical application exception.
At step 2(b), the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. The additional element of a “register” for storing the 1-hot signal, this limitation amounts to necessary data gathering for subsequent mathematical operations using a type of extra-solution limitation that is well known. Kaeslin Fig. 6.2(a) shows synchronous clocking (i.e., registers prior to circuitry operating on data) and Fig. 6.1 shows that synchronous edge triggered one phase single edged clocking is “standard practice.” The additional elements of a first accumulator, an outer product circuit, and a second accumulator, these circuit elements are recited at a high level of generality and amount to mere instructions to “apply it” for the reasons given above. Mere instructions to apply an exception cannot provide an inventive concept. Even when considered in combination, these additional elements represent mere instructions to apply an exception and insignificant extra-solution activity, which do not provide an inventive concept. The claim is not eligible.
Claim 2:
At step (2)(a) prong 2, claim 2 recites an abstract idea as follows (with the abstract idea shown as italicized language):
a second register for storing a second 1-hot signal, the second 1-hot signal representing a portion of the input frame
Mathematical Relationship – the italicized language describes in words the mathematical characteristics of the binary numbers stored in the register
a second outer product circuit that receives each element of the present summation from the first accumulator and each element of the second 1-hot signal stored in the second register to output a second present outer product
Mathematical
Calculation
and an adder that combines the present outer product and the second present outer product before the second accumulator receives the present outer product, wherein the second accumulator outputs the present second-layer summation by adding the combined present outer product and the second present outer product to a previous second-layer sum of outputs from the adder within the timeframe.
Mathematical
Calculation
At step 2(a) prong 2, the judicial exception recited in claim 2 is not integrated into a practical application. Although claim 2 recites the additional element of a “second register” for storing a second 1-hot signal, this limitation amounts to necessary data gathering for subsequent mathematical operations using a type of extra-solution limitation that is well known. Moreover, the use of a second register to store the 1-hot binary values representing the signal imposes no meaningful limits on the claim such that it is not nominally or tangentially related to the invention. The second register is a necessary consequence of the mathematical algorithm that defines time stages. As a consequence, this register is not significant. Although claim 2 does recite the additional elements of a second outer product circuit and an adder, these circuit elements are recited at a high level of generality and amount to mere instructions to “apply it” by using the type of circuit element normally used to perform that type of mathematical function. The circuit elements and their interconnection are merely a direct consequence of the abstract idea and merely serve to perform the mathematical calculation of the abstract idea recited in the claim. Although claim 2 does refer to the second accumulator of claim 1, the claim merely adds additional mathematical functions by explaining how the accumulator uses the output of the adder of claim 2. The analysis for the second accumulator is therefore essentially the same as what is set forth in the analysis of claim 1. Even when viewed in combination, these additional elements (in combination with the additional elements of parent claim 1) do not integrate the recited judicial into a practical application exception.
At step 2(b), the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. The additional element of a “second register” for storing the second 1-hot signal, this limitation amounts to necessary data gathering for subsequent mathematical operations using a type of extra-solution limitation that is well known. Kaeslin Fig. 6.2(a) shows synchronous clocking (i.e., registers prior to circuitry operating on data) and Fig. 6.1 shows that synchronous edge triggered one phase single edged clocking is “standard practice.” The additional elements of a second outer product circuit and an adder, these circuit elements are recited at a high level of generality and amount to mere instructions to “apply it” for the reasons given above. Mere instructions to apply an exception cannot provide an inventive concept. Although claim 2 does refer to the second accumulator of claim 1, the claim merely adds additional mathematical functions by explaining how the accumulator uses the output of the adder of claim 2. The analysis for the second accumulator is therefore essentially the same as what is set forth in the analysis of claim 1. Even when considered in combination with the additional elements of parent claim 1, these additional elements represent mere instructions to apply an exception and insignificant extra-solution activity, which do not provide an inventive concept. The claim is not eligible.
As to claim 3, it is directed to the transformation of the m-hot input into 2 separate 1-hot vectors as shown in the left part of Figure 6A. The circuitry transforms the m-hot input into the form needed to perform the mathematical calculations shown in the remainder of the figure and claimed in parent claim 2. The transformation of binary numbers from one format to another is considered a mathematical relationship. See Gottschalk v. Benson.
Although claim 3 does recite the additional elements of the 1-hot encoders and the exclusive or gate, they are recited at a high level of generality and are at best the equivalent of merely adding the words “apply it” to the judicial exception. Mere instructions to apply an exception cannot provide an inventive concept. Even when viewed in combination with the additional elements of parent claims, they do not integrate the recited judicial into a practical application exception.
At step 2B, the analysis for claim 3 is the same as for step 2A prong 2. The additional elements do not, alone or in combination, provide an inventive concept. The claim is not eligible.
As to claim 4, it recites an abstract idea because it recites adding the two different 1-hot signals of claim 3 and providing their sum to the accumulator. This is a mathematical calculation or a mathematical relationship.
Although claim 4 does recite the additional element of an adder, it is recited at a high level of generality and is at best the equivalent of merely adding the words “apply it” to the judicial exception. Mere instructions to apply an exception cannot provide an inventive concept. Even when viewed in combination with the additional elements of parent claims, it does not integrate the recited judicial into a practical application exception.
At step 2B, the analysis for claim 3 is the same as for step 2A prong 2. The additional element does not, alone or in combination, provide an inventive concept. The claim is not eligible.
Regarding claim 5, it is directed to additional n-depth signature stages where n is 3 or more. This arrangement is shown in Figures 2 and 7 elem. 230 and described at least at Spec. [0022]. The claim introduces a new additional element, the higher-layer calculator circuit but then goes on to specify internal components of the higher-layer calculation circuit (i.e., an outer product circuit and an accumulator). The internal components perform essentially the same function as the second outer product circuit and second accumulator that perform the two-depth signature function of claim 2. The functional language is essentially the same except for fact that their functional language reflects the inputs and the outputs appropriate for n>2.
As a consequence, the step 2 A prong 1 and prong 2 analysis for claim 2 applies, mutandis mutatis, to these elements. The higher-layer calculation circuit is recited at a high level of generality and is at best the equivalent of merely adding the words “apply it” to the judicial exception. Even when viewed in combination, these additional elements (in combination with the additional elements of parent claim 1) do not integrate the recited judicial into a practical application exception.
At step 2B, the analysis for claim 2 applies, mutandis mutatis, to the analysis for claim 5The additional elements do not, alone or in combination, provide an inventive concept. The claim is not eligible.
Regarding claim 6, it merely recites additional abstract idea because the claim merely specifies in more detail the mathematical function of the outer product circuit of claim 1. The analysis for claim 6 is therefore the same as for claim 1.
Regarding claim 9, the claim recites a mathematical relationship or calculation, which is converting a path signature generated by the path signature accelerator into a log signature.
Although claim 9 does recite the additional element of a logarithmic function circuit, it is recited at a high level of generality and is at best the equivalent of merely adding the words “apply it” to the judicial exception. Mere instructions to apply an exception cannot provide an inventive concept. Even when viewed in combination with the additional elements of parent claim, it does not integrate the recited judicial into a practical application exception.
At step 2B, the analysis for claim 3 is the same as for step 2A prong 2. The additional element does not, alone or in combination, provide an inventive concept. The claim is not eligible.
Allowable Subject Matter
Claims 1-20 would be allowable over the prior art of record if the other rejections are overcome.
Claims 7-8 and 10-20 would also be allowable if rewritten in independent form and if the rejection under 35 U.S.C. 112 is overcome.
The following is a statement of reasons for the indication of allowable subject matter:
Nobile teaches a system for monitoring computer performance by tracking API calls and statistical information associated with the API calls and then converting that information into vector representations that are fed into a neural network. See Fig. 1 and p. 22 lines 19-22. The vectors may be converted into a 1-hot representation. P. 16 lines 4-6. Nobile however fails to teach or suggest a combination as in claim 1 that calculates one and two-depth signatures using a register, first accumulator, outer product circuit, and a second accumulator.
Bartling, U.S. Patent 11,249,515 (filed by Applicant) teaches a processing system that captures events associated with software and generates path signatures for the events. See Fig. 1. While Bartling teaches that circuitry generates a path signature, Bartling is silent as to any details of how the path signature is generated. Bartling therefore fails to teach or suggest a combination as in claim 1 that calculates one and two-depth signatures using a register, first accumulator, outer product circuit, and a second accumulator. In addition, Bartling does not teach or suggest path signatures calculated from 1-hot signals.
Moran, U.S. Patent 12,147,326 (filed by Applicant) teaches an event monitoring system that generates alerts based on information from a classifier. See Fig. 5. Moran does not teach or suggest that path signatures are used. Moran therefore fails to teach or suggest a combination as in claim 1 that calculates one and two-depth signatures using a register, first accumulator, outer product circuit, and a second accumulator.
Conclusion
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/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
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