DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This communication is in response to the claim’s amendment dated 8/8/2025.
Response to Arguments
Applicant's arguments filed 8/8/2025 have been fully considered but they are not persuasive.
Arguments raised by Applicant:
On pages 6-7 of the Remarks, Applicant asserts “Ong fails to teach or suggest "each spacer of the plurality of spacers has an electric field of a creepage distance greater than 0.4kV/mm." The Office Action acknowledges this deficiency but argues it would have been obvious to "derive such claimed creepage distance...to prevent short circuit or malfunction." Applicant submits this reasoning is conclusory and lacks proper support because Arens merely defines voltage thresholds for high and low voltage circuits and discusses general spacing requirements between components. Neither reference (nor the combination of references) provides any teaching that would lead one of ordinary skill to specifically configure spacers to have "an electric field of a creepage distance greater than 0.4kV/mm" as recited by claim 9.
Independent claim 14 recites similar limitations regarding the creepage distance requirement and is allowable for at least the same reasons as claim 9. Dependent claims 10-13 and 15-20 are allowable at least by virtue of their dependency from allowable independent claims 9 and 14 respectively.
Additionally, regarding the specific value of "2kV/mm" recited in claims 11 and 15, the Office Action has provided no explanation for why one of ordinary skill would arrive at this specific value. While Arens provides equations relating to discharge prevention distances, these equations do not suggest the specific claimed creepage distance values. The Office Action's general statement that it would be obvious to derive such values "to prevent short circuit or malfunction" is insufficient to establish obviousness of these specific numerical limitations.”.
The Examiner’s position:
The Examiner respectfully disagrees with the Applicant for the following reason:
Claim 9 recites: “each spacer of the plurality of spacers has an electric field of a creepage distance greater than 0.4kV/mm”.
Claim 11 recites “the electric field of the creepage distance is 2kV/mm.
It appears that the electric field of creepage distance does not need to be at any critical value. The specification does not show support for such criticalities.
As indicated in the previous Office Action, Ong et al. U.S. Patent 12,051,581 (D1) does show an equation relating how creepage distance can be calculated and derived.
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It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to derive different values of creepage distance for each spacer of electronic system of D1, since there is no criticalities shown and required by the specification of the current application as to why said values must be 0.4kV/mm and 2kV/mm.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ong et al. U.S. Patent 12,051,581 (hereinafter D1) in view of Arens et al. U.S. Pub. 2015/0092376 (hereinafter D2).
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Regarding claim 9, D1 teaches an electronic system (figures 1 and 13; four coupled power supply modules) comprising:
one or more power supply modules (1; figure 1), wherein each power supply module comprises:
a housing (housing of 1; figure 1) comprising at least two planes, wherein a first plane defines an upper surface (see above annotated figure 1), and a second plane defines a lower surface (see above annotated figure 1) of the housing;
a printed circuit board (2, figure 1) positioned between at least the upper surface and the lower surface (see figure 1);
a plurality of spacers (9; figure 1) positioned on at least a high voltage end of the PCB (2; figure 1) and configured to engage with at least one plane of the at least two planes (see figure 1).
However, D1 does not specifically teach wherein each spacer of the plurality of spacers has an electric field of a creepage distance greater than 0.4kV/mm.
Note:
Creepage distance is the minimum separation between two conductive parts measured along the surface of an insulating material (e.g., the PCB, a plastic housing, or a ceramic insulator). It helps prevent electric discharges or "tracking," where a conductive path forms on the surface of the insulation, potentially leading to a short circuit or malfunction.
D1, however, does show an equation relating how creepage distance can be calculated and derived.
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It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to derive such claimed creepage distance for each spacer of electronic system of D1, as also suggested by D1 in the above equation, to prevent short circuit or malfunction.
However, D1 does not specifically teach an encapsulant comprised of an insulating material and configured to encapsulate the PCB and the plurality of spacers.
D2, in the same field of endeavor, teaches an electronic system, which suggests an encapsulant (see par[0030]) comprises an insulating material and configured to encapsulate a PCB.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to further provide the power supply module of D1 with an encapsulant comprised of an insulating material, as suggested by D2, to encapsulate the PCB and the plurality of spacers of D1, to improve isolation against humidity.
Regarding claim 10, D1/D2 teaches the electronic system of claim 9, wherein each spacer of the plurality of spacers comprises:
a plurality of disks (see above annotated figure 1 of D1) having a disk diameter (see above figure 1) defining the creepage distance (see explanation in above rejection of claim 9) along a surface of each disk, a core (implicitly taught in above figure 1 of D1) having a core diameter (see above figure 1 of D1) less than the disk diameter, a first end (see above figure 1 of D1) configured to engage with the upper surface of the housing, and a second end (see figure 14 of D1) configured to engage with the lower surface of the housing.
Regarding claim 11, D1/D2 teaches the electronic system of claim 10.
However, D1 does not specifically teach wherein the electric field of the creepage distance is 2kV/mm.
D1, however, does show an equation relating how creepage distance can be calculated and derived.
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It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to derive such claimed creepage distance for each spacer of electronic system of D1, as also suggested by D1 in the above equation, to prevent short circuit or malfunction.
Regarding claim 12, D1/D2 teaches the electronic system of claim 10, wherein the housing further comprises
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an interior (see figure 1 of D1) comprised of the first plane, the second plane, and a plurality of side planes (see figure 1 of D1), wherein the plurality of side planes comprise: a first side plane (implicitly taught in figure 1 of D1) of the housing, a second side plane (implicitly taught in figure 1 of D1) of the housing, a third side plane (implicitly taught in figure 1 of D1) of the housing, and a fourth side plane (implicitly taught in figure 1 of D1) of the housing.
Regarding claim 13, as mentioned above, D1/D2 teaches the electronic system of claim 12.
Even though, D1/D2 does not specifically teach that the plurality of spacers further comprise a ratio of hardening agent greater than the ratio of hardening agent in the electrical insulating material of the encapsulant to prevent warping of the PCB at least at the high voltage end, however, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to derive such ratio, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 14, D1/D2 teaches a power supply module of claim 14 for the same reasons stated in the above rejection of claims 9 and 10. D1 also teaches an electronic assembly (7; figure 1 of D1) comprising one or more electrical component (14 and/or 15; figure 1 of D1) coupled to at least one surface of the electronic assembly.
Regarding claim 15, D1/D2 teaches the power supply module of claim 15 for the same reasons stated in the above rejection of claim 11.
Regarding claim 16, D1/D2 teaches the power supply module of claim 16 for the same reasons stated in the above rejection of claim 13.
Regarding claim 17, D1/D2 teaches the power supply module of claim 16, wherein the plurality of spacers are affixed (indirectly) to the one or more electrical components (see figures 1, 9, and 14 of D1) of the electronic assembly.
Regarding claim 18, D1/D2 teaches the power supply module of claim 14, further comprising one or more coupling members (implicitly taught in figure 13 of D1; figure 13 shows multiple power supply modules coupled together) configured to detachably couple the power supply module to one or more second power supply modules.
Regarding claim 19, the modification of D1, as suggested by D2, would result in the power supply module of claim 14, wherein the insulating material is configured to prevent (implicitly taught) breakdown of the encapsulant at a contact surface of the plurality of spacers and the encapsulant when a voltage is introduced across the contact surface of the plurality of spacers.
Regarding claim 20, the modification of D1, as suggested by D1, would result in the power supply module of claim 19, wherein the electronic assembly (2; figure 1 of D1) is a printed circuit board (PCB) (see figure 1 of D1) and the plurality of spacers (see above annotated figure 1 of D1) are positioned on the PCB at least at a high voltage (see column 5, lines 31-36) end of the PCB, wherein the plurality of spacers are further configured to prevent (implicitly taught) warping of the PCB during assembly and curing of the encapsulant.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUNG Q DANG whose telephone number is (571)272-3069. The examiner can normally be reached M-F 10-6PM..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Imani N Hayman can be reached at 571-270-5528. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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HUNG Q. DANG
Examiner
Art Unit 2835
/IMANI N HAYMAN/Supervisory Patent Examiner, Art Unit 2841