DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/9/2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ong et al. U.S. Patent 12,051,581 (hereinafter D1) in view of Arens et al. U.S. Pub. 2015/0092376 (hereinafter D2).
PNG
media_image1.png
460
737
media_image1.png
Greyscale
Regarding claim 9, D1 teaches an electronic system (figures 1 and 13; four coupled power supply modules) comprising:
one or more power supply modules (1; figure 1), wherein each power supply module comprises:
a housing (housing of 1; figure 1) comprising a first surface (see above annotated figure 1), and a second surface (see above annotated figure 1); wherein the first surface is parallel to the second surface;
a printed circuit board (2, figure 1) positioned between the first surface and the second surface (see figure 1);
a plurality of spacers (9; figure 1), each of the spacers coupled to the first surface and the second surface (see figure 1).
However, D1 does not specifically teach wherein each spacer of the plurality of spacers has an electric field of a creepage distance greater than 0.4kV/mm.
Note:
Creepage distance is the minimum separation between two conductive parts measured along the surface of an insulating material (e.g., the PCB, a plastic housing, or a ceramic insulator). It helps prevent electric discharges or "tracking," where a conductive path forms on the surface of the insulation, potentially leading to a short circuit or malfunction.
D1, however, does show an equation relating how creepage distance can be calculated and derived.
PNG
media_image2.png
218
368
media_image2.png
Greyscale
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to derive such claimed creepage distance for each spacer of electronic system of D1, as also suggested by D1 in the above equation, to prevent short circuit or malfunction.
However, D1 does not specifically teach an encapsulant comprised of an insulating material and configured to encapsulate the PCB and the plurality of spacers.
D2, in the same field of endeavor, teaches an electronic system, which suggests an encapsulant (see par[0030]) comprises an insulating material and configured to encapsulate a PCB.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to further provide the power supply module of D1 with an encapsulant comprised of an insulating material, as suggested by D2, to encapsulate the PCB and the plurality of spacers of D1, to improve isolation against humidity.
Regarding claim 10, D1/D2 teaches the electronic system of claim 9, wherein each spacer of the plurality of spacers comprises:
a plurality of disks (see above annotated figure 1 of D1) having a disk diameter (see above figure 1) defining the creepage distance (see explanation in above rejection of claim 9) along a surface of each disk, a core (implicitly taught in above figure 1 of D1) having a core diameter (see above figure 1 of D1) less than the disk diameter, a first end (top end of 9; see above figure 1 of D1) configured to engage with the first surface of the housing, and a second end (bottom end of 9; see figure 14 of D1) configured to engage with the second surface of the housing.
Regarding claim 11, D1/D2 teaches the electronic system of claim 10.
However, D1 does not specifically teach wherein the electric field of the creepage distance is 2kV/mm.
D1, however, does show an equation relating how creepage distance can be calculated and derived.
PNG
media_image2.png
218
368
media_image2.png
Greyscale
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to derive such claimed creepage distance for each spacer of electronic system of D1, as also suggested by D1 in the above equation, to prevent short circuit or malfunction.
Regarding claim 12, as mentioned above, D1/D2 teaches the electronic system of claim 10.
Even though, D1/D2 does not specifically teach that the first end comprises a diameter that is less than the diameter of the second end, however, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to change the diameter sizes of the first/second ends such that the first end would comprise a diameter that is less than the diameter of the second end, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Regarding claim 13, as mentioned above, D1/D2 teaches the electronic system of claim 12.
Even though, D1/D2 does not specifically teach that the plurality of spacers further comprise a ratio of hardening agent greater than the ratio of hardening agent in the electrical insulating material of the encapsulant to prevent warping of the PCB, however, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to derive such ratio, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
PNG
media_image1.png
460
737
media_image1.png
Greyscale
Regarding claim 14, D1 teaches a power supply module comprising:
a housing (housing of 1; figure 1) comprising a first surface (see above annotated figure 1) and a second surface (see above annotated figure 1) of the housing;
an electronic assembly (assembly inside housing 1; see figure 1) comprising electrical components (components inside housing 1) coupled to at least one surface (surface of substrate 2; figure 1) of the electronic assembly;
a plurality of spacers (9; figure 1), each of the spacers comprising:
a plurality of disks (see above annotated figure 1) having a disk diameter (see figure 1) defining a creepage distance (implicitly taught) along a surface of each disk,
a core (central portion of 9) having a core diameter (diameter of core of 9) less than (see figure 1) the disk diameter, wherein the core is coupled (see figure 1) to the electronic assembly,
a first end (top end of 9; figure 1) configured to engage with the first surface of the housing,
a second end (bottom end of 9; figure 1) configured to engage with the second surface of the housing.
However, D1 does not specifically teach wherein each spacer of the plurality of spacers has an electric field of a creepage distance greater than 0.4kV/mm.
Note:
Creepage distance is the minimum separation between two conductive parts measured along the surface of an insulating material (e.g., the PCB, a plastic housing, or a ceramic insulator). It helps prevent electric discharges or "tracking," where a conductive path forms on the surface of the insulation, potentially leading to a short circuit or malfunction.
D1, however, does show an equation relating how creepage distance can be calculated and derived.
PNG
media_image2.png
218
368
media_image2.png
Greyscale
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to derive such claimed creepage distance for each spacer of electronic system of D1, as also suggested by D1 in the above equation, to prevent short circuit or malfunction.
However, D1 does not specifically teach an encapsulant comprised of an insulating material and configured to encapsulate the PCB and the plurality of spacers.
D2, in the same field of endeavor, teaches an electronic system, which suggests an encapsulant (see par[0030]) comprises an insulating material and configured to encapsulate a PCB.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to further provide the power supply module of D1 with an encapsulant comprised of an insulating material, as suggested by D2, to encapsulate the PCB and the plurality of spacers of D1, to improve isolation against humidity.
Regarding claim 15, D1/D2 teaches the power supply module of claim 15 for the same reasons stated in the above rejection of claim 11.
Regarding claim 16, D1/D2 teaches the power supply module of claim 16 for the same reasons stated in the above rejection of claim 13.
Regarding claim 17, D1/D2 teaches the power supply module of claim 16, wherein the plurality of spacers are affixed (indirectly) to one or more electrical components (see figures 1, 9, and 14 of D1) of the electronic assembly.
Regarding claim 18, D1/D2 teaches the power supply module of claim 14, further comprising one or more coupling members (implicitly taught in figure 13 of D1; figure 13 shows multiple power supply modules coupled together) configured to detachably couple the power supply module to one or more second power supply modules.
Regarding claim 19, the modification of D1, as suggested by D2, would result in the power supply module of claim 14, wherein the insulating material is configured to prevent (implicitly taught) breakdown of the encapsulant at a contact surface of the plurality of spacers and the encapsulant when a voltage is introduced across the contact surface of the plurality of spacers.
Regarding claim 20, the modification of D1, as suggested by D1, would result in the power supply module of claim 19, wherein the electronic assembly (2; figure 1 of D1) is a printed circuit board (PCB) (see figure 1 of D1), wherein the plurality of spacers are further configured to prevent (implicitly taught) warping of the PCB during assembly and curing of the encapsulant.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUNG Q DANG whose telephone number is (571)272-3069. The examiner can normally be reached M-F 10-6PM..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Imani N Hayman can be reached at 571-270-5528. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
HUNG Q. DANG
Examiner
Art Unit 2835
/IMANI N HAYMAN/Supervisory Patent Examiner, Art Unit 2841
Prosecution Insights