Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claim s 1 – 11, 13, and 16 – 20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Li et al. (US Patent Application Publication 2015/0278004) , hereinafter Li . Regarding claim 1, Li teaches an electronic apparatus, comprising: one or more substrates (Paragraph 0016, the memory chips) ; and a controller coupled to the one or more substrates (Abstract) , the controller including circuitry ( Paragraph 0058 ) to: control access to a memory for a range of addresses within a memory address space (Paragraph 0036, access to the memory is performed via page tables and a translation lookaside buffer; The ordinary meaning of these components in the art involve the translation of physical and virtual memory address spaces) ; configure a first region of the memory within a first sub-range of addresses within the memory address space to be accessed with a first protection level of two or more memory fault protection levels (Abstract, the controller configured a type of error protection for a memory page ; Paragraph 0031, the memory controllers have 3 levels of ECC logic , also referred to as access granularity, and at least 4 memory modes , also referred to as ECC schemes, including SECDED, chipkill , double chipkill , and quad chipkill . Each of these levels or memory modes or a combination can be considered a first protection level ) ; configure a second region of the memory within a second sub-range of addresses within the memory address space that is non-overlapping with the first sub-range to be accessed with a second protection level of the two or more memory fault protection levels (Paragraph 0012, the systems can select different access granularities on a per-memory page basis; Paragraph 0031, the memory controllers have 3 levels of ECC logic, also referred to as access granularity, and at least 4 memory modes, also referred to as ECC schemes, including SECDED, chipkill , double chipkill , and quad chipkill . Each of these levels or memory modes or a combination can be considered a second protection level as long; Paragraph 0036, different pages have different access granularities and ECC schemes . The pages are physical, so they do not overlap with one another ) . Regarding claim 2, Li teaches the apparatus of claim 1, wherein the circuitry is further to: reconfigure one or more of the first and second regions of the memory with a different s u b-range of addresses (Paragraph 0038, selections of memory modes can be changed. In modifying the pages and their respective protection levels, any change in a page’s protection level would be reconfiguring a region of memory to either include or not include that page) at runtime in response to a request from a software agent (Paragraph 0037, selection of memory modes may be dynamic, during execution of a runtime environment of the operating system ). Regarding claim 3, Li teaches the apparatus of claim 1, wherein the circuitry is further to: reconfigure one or more of the first and second regions of the memory with a different memory fault protection level (Paragraph 0038, selections of memory modes can be changed) at runtime in response to a request from a software agent (Paragraph 0037, selection of memory modes may be dynamic, during execution of a runtime environment of the operating system). Regarding claim 4, Li teaches the apparatus of claim 1, wherein the circuitry is further to: determine respective protection levels associated with respective regions of the memory based on information to be stored in a data structure that is accessible to the controller (Paragraph 0036, the information is stored in a page table) . Regarding claim 5, Li teaches the apparatus of claim 4, wherein the circuitry is further to: access the data structure from one or more page tables to be stored in the memory (Paragraph 0036, the page table is stored in the memory 112) . Regarding claim 6, Li teaches the apparatus of claim 1, wherein the circuitry is further to: interleave respective regions of the memory with respective memory fault protection levels (Paragraph 0021, chipkill -correct is implemented by interleaving other ECCs; Paragraph 0034, the data block with specific access levels are interleaved in a similar manner to have a dynamic layout that can easily switch levels ) . Regarding claim 7, Li teaches the apparatus of claim 1, wherein the circuitry is further to: configure respective cache line sizes for the first and second regions of memory in accordance with the respective first and second protection levels (Paragraph 0038, the cache line size corresponds to the access granularity; Paragraph 0024, the access granularity corresponds with the protection level) . Regarding claim 8, Li teaches the apparatus of claim 1, wherein the first protection level corresponds to a full chip-fail level of memory fault protection (Paragraph 0031, one of the memory modes can be chipkill ) and wherein the second protection level corresponds to a bounded fault level of memory fault protection (Paragraph 0031, one of the modes can be SECDED) . Regarding claim 9, Li teaches an electronic system comprising: memory (Abstract) ; and a controller communicatively coupled to the memory (Abstract) , the controller including circuitry (Paragraph 0058) . Claim 9 otherwise recites similar language to claim 1, and is similarly rejected. Claim 10 recites similar language to claims 2 and 3, and is similarly rejected. Claim 11 recites similar language to claim 4, and is similarly rejected. Claim 13 recite s similar language to claim 7, and is similarly rejected. Claim 16 recites similar language to claim 1, and is similarly rejected. Regarding claim 17, Li teaches the method of claim 16, further comprising: reconfiguring one or more of the respective regions of the memory at runtime in response to a request from an operating system (Paragraph 0037, selection of memory modes may be dynamic, during execution of a runtime environment of the operating system ) . Claim 18 recites similar language to claim 4, and is similarly rejected. Claim 19 recites similar language to claim 5, and is similarly rejected. Claim 20 recites similar language to claim 7, and is similarly rejected. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Li in view of the Wikipedia article for Translation lookaside buffer (NPL, archived from revision before effective filing date) , hereinafter Wikipedia TLB . Li teaches the system of claim 11. Li does not explicitly teach that the data structure (in this case the page table) is accessed from one or more registers. Li does, however, teach that the data structure is accessed from a translation lookaside buffer (Paragraph 0036) . Wikipedia TLB teaches that x86 CPUs access page tables via TLB by using the CR3 register ( TLB-miss handling ) . It alternatively teaches that process ID registers or enable flags in a CR4 register are used ( Address-space switch ) . It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention that Li accesses the page table in a manner similar to that taught by Wikipedia TLB. As shown by Wikipedia TLB’s multiple examples, using a register with the TLB and page tables is well-known. Furthermore , x86 CPUs are well-known, widely used processors, which are used in products manufactured by Hewlitt Packard , the assignee of Li. It would be obvious to one of ordinary skill in the art that the processor of Li would likely be an x86 processor which accesses the page tables using the CR3 register. Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Li in view of the Wikipedia article for DIMM (NPL, archived from revision before effective filing date) , hereinafter Wikipedia DIMM . Li teaches the system of claim 9. Li does not explicitly teach that the memory corresponds to an external memory system. Li does, however, teach that the memory corresponds to DRAM implemented with physical DIMM modules (Paragraph 0017) , similarly to the external DRAM noted in the present application’s Specification. Wikipedia DIMM teaches that DRAM DIMMs are commonly external, and mounted onto motherboard via slots (See images, header, and Form factors ) . It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention that the DRAM memory of Li corresponds to an external memory system. It would be obvious because DRAM DIMMs are commonly external as taught by Wikipedia. It would be clear to a person of ordinary skill in the art that the system of Li would be compatible with common forms of DRAM such as external DRAM. Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Li in view of the Wikipedia article for Compute Express Link (NPL, archived from revision before effective filing date) , hereinafter Wikipedia CXL. Li teaches the system of claim 9, further comprising a processor communicatively coupled to the memory ( Paragraph 0029, a multi-core processor that communicates with multiple caches ) . Li does not explicitly teach that the processor is coupled to the memory via a cache-coherent interconnect. Wikipedia CXL teaches that a processor communicatively coupled to memory via a cache-coherent interconnect (Header) . It would be obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the system of Li to have its multi-core processor communicate with a cache coherent interconnect such as CXL. It would be obvious because there is a market motivation for the assignee of Lee, Hewlitt Packard, to implement CXL . According to Wikipedia CXL, CXL was a founding member of the CXL Consortium (Wikipedia CXL History ) . Furthermore, because Li teaches a multi-core processor with multiple caches accessing the same memory, it especially benefits from coherency between these caches. It would be clear to one of ordinary skill in the art before the effective filing date of the invention that implementing the system described by Li may include the use of a cache coherent interconnect. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Mogul et al. (US Patent Application Publication 2015/ 0248316 ) teaches a system for selecting between error detection and correction. Zhao et al. (US Patent Application Publication 2016/0196179) teaches configurable ECC for memory. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT BRYAN PAI SONG HUANG whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-0510 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday - Friday 11:30 AM - 8:30 PM . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /B.P.H./ Examiner, Art Unit 2114 /ASHISH THOMAS/ Supervisory Patent Examiner, Art Unit 2114