Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This communication is responsive to the amendment and remarks filed 08/07/2026 in reply to the non-final Office Action mailed 05/20/2026. The amendment has been entered. The specification has been amended, and claims 15-17 have been amended. Claims 1-20 are pending and are examined herein.
2. Applicant’s summary of the telephone interview of June 22, 2026 (Remarks, p. 8) is acknowledged. For the reasons given under “Priority” and “Response to Arguments” below, upon further review of the benefit applications the examiner has determined that claims 1-20 are not entitled to the benefit dates on which Applicant’s arguments rely. This action therefore sets forth new grounds of rejection that were not necessitated by amendment, and is made NON-FINAL.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046 (Fed. Cir. 1993); In re Longi, 759 F.2d 887 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937 (CCPA 1982); In re Vogel, 422 F.2d 438 (CCPA 1970); and In re Thorington, 418 F.2d 528 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP 717.02 for applications subject to examination under the first inventor to file provisions of the AIA . A registered attorney or agent of record may sign a terminal disclaimer. The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection; a complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action.
3. Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-17 of U.S. Patent No. 12,271,322 B2 (“the ’322 patent,” App. No. 17/669,351, commonly assigned to Samsung Electronics Co., Ltd.), alone or in view of Mesnier, SNIA, and/or Kachare as indicated. Although the claims at issue are not identical, they are not patentably distinct from each other for the following reasons.
Regarding claim 1, claim 1 of the ’322 patent recites a multi-function device comprising “a first port to communicate with a host processor” (the claimed fourth connector), “a second port to communicate with a storage device” (the claimed first connector), and “a third port to communicate with a computational storage unit” (the claimed second connector), and a first circuit to “route a message from the host processor to at least one of the storage device or the computational storage unit.” Claims 4-5 of the ’322 patent further recite that the first port includes an endpoint that is “configured to expose at least the first exposed function [of the storage device] and the second exposed function [of the computational storage unit],” i.e., exposing the storage device and the first computational storage unit to the host processor via the host connector. The ’322 claims do not recite a further connector for communicating with a second computational storage unit. Adding a second port of the same kind for a second computational storage unit is a mere duplication of parts that would have been obvious (In re Harza, 274 F.2d 669 (CCPA 1960); MPEP 2144.04(VI)(B)), and Mesnier teaches a plurality of FPGAs attached to the same PCIe switch as NVMe storage (FIG. 58C; [0665]). It would have been obvious to provide such a further port to increase the compute resources available to the attached storage. Claim 1 of the ’322 patent is otherwise narrower than, and thus encompasses the remaining subject matter of, instant claim 1.
Regarding claims 2-3, ’322 claim 1 recites “a second circuit connected to the second port and the third port to support peer-to-peer communication between the storage device and the computational storage unit,” and ’322 claims 12 and 15-17 recite identifying a second device from a second request received from the first device and transmitting that request to the second device, including peer-to-peer communication; these render obvious an attached device invoking a capability of another attached device (instant claim 2) and the multi-function device receiving a request from one device and sending it to another (instant claim 3).
Regarding claims 4-6, ’322 claim 1 recites “a buffer to store a first data and a second data,” the storage device and computational storage unit writing to and reading from the buffer, and “a data processor to process the first data in the buffer to generate the second data,” which anticipates instant claims 4-6 except for the second computational storage unit, obvious for the reasons given for claim 1.
Regarding claim 7 (as interpreted above), ’322 claims 2-3 recite a multiplexer/demultiplexer and “a first bridge connected to the second port” and “a second bridge connected to the third port,” with the first circuit (connected to the host port) routing messages through the bridges, and ’322 claim 1 recites the attached devices writing data into the buffer of the multi-function device. A third bridge for the duplicated third port would have been obvious for the reasons given for claim 1, and a bridge receiving a request from an attached device and directing it to the buffer is rendered obvious by the devices of ’322 claim 1 writing to and reading from the buffer through their ports.
Regarding claims 8-9, the ’322 claims do not recite a list of device configurations. Kachare teaches a configuration table with entries for each attached device, selective exposure based on it, and enumerating newly connected devices to update it ([0042], [0067], [0073], [0101]-[0102]). It would have been obvious to add Kachare’s table to the device of the ’322 claims for the reasons given in the § 103 rejection of claims 8-9.
Regarding claims 10-17, instant claim 10 differs from ’322 claims 1 and 4-5 in reciting that the first computational storage unit is integrated into the multi-function device and in reciting a connector for a second computational storage unit. Making the computational storage unit integral is an obvious design choice (MPEP 2144.04(V)(B)), and SNIA teaches a computational storage array containing centrally located computational storage engines (§ 3.1.3, p. 16; § 4.1, p. 22); the second connector is obvious for the reasons given for claim 1. Claims 11-17 are rejected for the reasons given for claims 2-9, respectively as they correspond (claim 11/claim 2; claims 12-14/claims 4-6; claim 15/claim 7; claims 16-17/claims 8-9).
Regarding claims 18-20, ’322 claims 8-10 recite a method performed by a multi-function device that identifies devices attached to its ports and, per claim 10, “identifying at least a first exposed function of the first device over the root port; identifying at least a second exposed function of the second device over the second root port; and exposing at least the first exposed function and the second exposed function to the host processor,” where the devices are drawn from “a storage device or a computational storage unit” (’322 claim 8). A second computational storage unit is obvious for the reasons given for claim 1, and selectively exposing the computational storage units and maintaining/updating a list of device configurations (claims 18 and 20) is taught by Kachare ([0067], [0101]-[0103]) and obvious for the reasons given for claims 8-9. Claim 19 is rejected for the reasons given for claim 10.
Claim Rejections - 35 USC § 112
4. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
5. Claim 7 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. Claim 7 recites “a third bridge connecting the fourth connector and the fourth connector.” A bridge connecting a connector to itself is not reasonably ascertainable, and it is unclear whether the third bridge is intended to connect the fourth (host) connector and the third connector (the connector for the second computational storage unit of claim 1). Applicant corrected the identical informality in claim 15 but not in claim 7. For purposes of examination, the limitation is interpreted as “a third bridge connecting the fourth connector and the third connector.”
Claim Rejections - 35 USC § 103
6. The following is a quotation of 35 U.S.C. § 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
7. Claims 1-6 and 10-14 are rejected under 35 U.S.C. 103 as being unpatentable over Mesnier et al. (US 2022/0188028 A1) (“Mesnier”) in view of SNIA, “Computational Storage Architecture and Programming Model,” Version 1.0, SNIA Standard (August 30, 2022) (“SNIA”).
Regarding claim 1, Mesnier discloses a multi-function device (PCIe switch 5846 of the Rack Scale Design (RSD) architecture, Mesnier FIG. 58C; [0665] “the processors are connected using PCIe x16 bifurcation port to a PCIe switch 5846 providing access to the target resources (FPGA or NVME in the RSD 5848)”), comprising: a first connector for communicating with a storage device (the port of PCIe switch 5846 connected to an NVMe drive of RSD 5848, FIG. 58C; [0665]-[0666]; the architecture “disaggregat[es] … non volatile memory express (NVMe) … resources,” [0662]); a second connector for communicating with a first computational unit and a third connector for communicating with a second computational unit (FIG. 58C shows a plurality of FPGAs connected to PCIe switch 5846; [0662] “disaggregating field programmable gate array (FPGA) … resources. The FPGA and NVMe resources provide elements that may be used for any type of edge services”; [0665]); and a fourth connector for communicating with a host processor (“the processors are connected using PCIe x16 bifurcation port to a PCIe switch 5846,” [0665]); wherein the multi-function device is configured to expose the storage device and the first computational unit to the host processor via the fourth connector (switch 5846 “provid[es] access to the target resources (FPGA or NVME in the RSD 5848),” [0665]; services on the compute sled “use client software libraries or drivers to provide transparent access to the disaggregated FPGAS and NVME in the RSD 5848,” [0666]). Mesnier is itself directed to computational storage (“Computational storage is an oft-attempted approach to addressing the data movement problem,” [0110]; see also [0106]).
Mesnier does not expressly disclose that the FPGAs attached to PCIe switch 5846 are computational storage units, i.e., compute resources associated with the storage that execute computational storage functions, or that the storage device and a computational storage unit are each presented to the host as a separately exposed device.
In the same field of endeavor, SNIA teaches a Computational Storage Processor (CSP), a “component that contains one or more CSEs for an associated storage system without providing persistent data storage” (SNIA § 3.1.9, p. 16; § 4.1, p. 22), where a Computational Storage Engine (CSE) is a component able to execute computational storage functions, “Examples are: CPU, FPGA” (§ 3.1.6, p. 16). SNIA teaches integrating compute resources “either directly with storage or between the host and the storage” (§ 4.1, p. 19), with each computational storage device coupled to hosts over a “Fabric (PCIe, Ethernet, etc)” (Figure 4.1, p. 20). SNIA further teaches that an NVMe controller and an accelerator (CSE) “appear as two separate PCI physical functions (PF) on the host” (Annex A.4.1, p. 58), and that this arrangement “also applies to a case with two discrete PCIe devices connected to the same PCIe fabric” (Annex A.4.2, p. 59). Thus SNIA teaches FPGA-based computational storage units that are associated with a storage device and are exposed, together with the storage device, to the host over a PCIe fabric.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the disaggregated FPGAs attached to Mesnier’s PCIe switch 5846 as SNIA computational storage processors associated with the NVMe storage on the same switch, and to expose the NVMe storage device and the FPGA-based computational storage unit to the host as separate PCIe functions through the host-side port, as SNIA teaches. Mesnier and SNIA are analogous art in the same field (computational storage over PCIe/NVMe), and Mesnier expressly seeks to place computation close to storage ([0106], [0110]). Applying SNIA’s standardized computational storage architecture to Mesnier’s FPGA and NVMe resources is the use of a known technique to improve a similar device in the same way, yielding the predictable result of FPGA resources usable as computational storage by standard host drivers (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007); MPEP 2143(I)(A), (C)). A person of ordinary skill would have had a reasonable expectation of success because both references use PCIe-attached NVMe devices and FPGAs, and SNIA states its model applies to discrete PCIe devices on the same PCIe fabric (p. 59).
Regarding claim 2, Mesnier in view of SNIA teaches the multi-function device of claim 1. Mesnier teaches that storage targets may “read from or write to other targets” using a target-to-target communication protocol ([0281]). Mesnier does not expressly teach a storage device invoking a capability of a computational storage unit. SNIA teaches that the storage controller “instructs the CSE to perform the indicated computation on the data in the FDM” (§ 4.5.1.2, Figure 4.4, step (4), p. 30), i.e., the storage device invokes a capability of the computational storage unit, and that the arrangement applies to discrete PCIe devices on the same fabric (p. 59). It would have been obvious to so configure the storage device and computational storage units on Mesnier’s switch, for the reasons given for claim 1, to perform computation on stored data without host involvement (SNIA p. 58, data moved “while bypassing the host system memory entirely”).
Regarding claim 3, Mesnier in view of SNIA teaches the multi-function device of claim 2. SNIA teaches PCIe peer-to-peer (P2P) transfer, i.e., a direct transfer mechanism between the NVMe controller and the accelerator (Annex A.4.1, p. 58), applicable to two discrete PCIe devices on the same PCIe fabric (p. 59). Mesnier’s PCIe switch 5846 is the fabric element connecting those devices ([0665]; FIG. 58C), so in the combination the multi-function device receives a request from one attached device (e.g., the storage device) and sends it to another attached device (e.g., a computational storage unit). Mesnier alone does not expressly describe the switch forwarding device-originated requests; SNIA supplies the peer-to-peer transfer, and the motivation of claim 2 applies.
Regarding claim 4, Mesnier in view of SNIA teaches the multi-function device of claim 1. Mesnier teaches buffers 128 used by the compute offload logic ([0076]) but does not teach a buffer in the multi-function device connected to the storage device and both computational storage units. SNIA teaches Function Data Memory (FDM), “device memory that is available for CSFs to use for data that is used or generated as part of the operation of a CSF” (§ 4.1, p. 21), exposed over PCIe so that data moves “between the NVMe controller and the OpenCL accelerator directly” through an “AFDM buffer” (Annex A.4.1-A.4.2, pp. 58-59), and teaches that in a Computational Storage Array the computational storage resources (which include the FDM, Figure 4.1, p. 20) “may be centrally located or distributed across CSDs/CSPs within the array” (§ 4.1, p. 22). It would have been obvious to locate the shared FDM buffer centrally in Mesnier’s multi-function device, connected to each of the storage device and computational storage units, because SNIA expressly teaches centrally located computational storage resources and because relocating the buffer to the common interconnect is an obvious rearrangement of parts that does not change its operation (MPEP 2144.04(VI)(C)), yielding the predictable benefit of peer-to-peer data sharing without host memory.
Regarding claim 5, Mesnier in view of SNIA teaches claim 4. SNIA teaches that input data on the device storage “can be directly transferred (using P2P transfer mechanism) to an AFDM buffer” and output data “is able to be directly transferred from the P2P AFDM buffer” (Annex A.4.2, p. 59), i.e., the storage device and computational storage units access data in the buffer. The motivation of claim 4 applies.
Regarding claim 6, Mesnier in view of SNIA teaches claim 4. SNIA teaches that “[t]he Storage Controller moves data from storage into the FDM” and “instructs the CSE to perform the indicated computation on the data in the FDM” (§ 4.5.1.2, Figure 4.4, steps (3)-(4), p. 30), i.e., a data processor (CSE) connected to the buffer that processes data in the buffer; SNIA further teaches CSRs, including CSEs, centrally located in the array (p. 22). The motivation of claim 4 applies.
Regarding claim 10, Mesnier discloses a multi-function device (PCIe switch 5846, FIG. 58C; [0665]) comprising a first connector for communicating with a storage device (NVMe of RSD 5848, [0665]-[0666]), a second connector for communicating with a second computational unit (FPGA of RSD 5848, FIG. 58C; [0662], [0665]), and a third connector for communicating with a host processor (PCIe x16 bifurcation port, [0665]), wherein the multi-function device is configured to expose the storage device and a computational unit to the host processor via the host connector ([0665]-[0666]), as set forth for claim 1. Mesnier does not disclose a first computational storage unit integrated into the multi-function device. SNIA teaches a Computational Storage Array (CSA), a “storage array that contains one or more CSEs” (§ 3.1.3, p. 16), containing array control and computational storage resources together with attached “Storage Device or CSD” units (Figure 4.1, p. 20), where the computational storage resources “may be centrally located” within the array (§ 4.1, p. 22); and teaches FPGA-based computational storage units exposed to the host over PCIe as set forth for claim 1 (pp. 16, 58-59). It would have been obvious to integrate a computational storage engine into Mesnier’s multi-function device, as SNIA’s CSA contains centrally located CSEs, while retaining a connector for a further (second) FPGA-based computational storage unit, and to expose the storage device and at least one computational storage unit to the host, for the reasons given for claim 1 and to reduce data movement by placing computation in the device that already interconnects the host and the storage (SNIA p. 19; Mesnier [0110]). Making an attached component integral is also an obvious design choice (MPEP 2144.04(V)(B)). A reasonable expectation of success exists for the reasons given for claim 1.
Regarding claims 11-14, Mesnier in view of SNIA teaches the multi-function device of claim 10, and claims 11, 12, 13 and 14 recite limitations corresponding to claims 2, 4, 5 and 6, respectively. They are rejected for the reasons given for claims 2, 4, 5 and 6, which apply equally with the first computational storage unit integrated into the device (SNIA CSA, pp. 16, 20, 22).
8. Claims 8-9 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Mesnier in view of SNIA, and further in view of Kachare et al. (US 2020/0401751 A1) (“Kachare”).
Regarding claim 8, Mesnier in view of SNIA teaches the multi-function device of claim 1. Mesnier teaches a POD Manager responsible for “discovery of resources in the POD, configuring and managing the resources, and composing a logical server,” including “scaling up or down the amount of pooled resources 5848 connected to a particular compute sled 5840” ([0663]), i.e., selectively making FPGA and NVMe resources available to a host.
Mesnier does not teach that the multi-function device comprises a storage for a list of device configurations including an entry for the storage device and for each computational storage unit, or selectively exposing devices based on that list.
In the same field of endeavor (a PCIe bridge that exposes, through a single host-side endpoint, functions of devices attached to its downstream ports), Kachare teaches a configuration table 435 storing configuration information including “the mapping between the PFs exposed by endpoint 405 and the PFs/VFs offered by SSD 125 (and determined via enumeration through root port 420)” ([0067]); a bridge with separate root ports 420-1, 420-2 and APP-RP 415-1, 415-2 for each attached device, all exposed from a single endpoint ([0073]); and that “certain functions exposed by SSD 125 of FIG. 1 might not get corresponding PFs exposed by LWB 135” ([0101]), i.e., selective exposure based on the stored mapping.
It would have been obvious to include in Mesnier’s multi-function device a storage holding Kachare’s configuration table with an entry for each attached device (the storage device and each computational storage unit), and to expose the computational storage units to the host selectively based on that table, to implement Mesnier’s composition of which pooled resources are connected to a given host ([0663]) and to aggregate the functions of multiple attached devices behind one host endpoint (Kachare [0073], [0102]). This is the combination of known elements by known methods with predictable results (MPEP 2143(I)(A)); a reasonable expectation of success exists because Kachare’s table operates on PCIe functions of attached devices, the same interface used by Mesnier and SNIA.
Regarding claim 9, Mesnier in view of SNIA and Kachare teaches claim 8. Kachare teaches that the configuration manager “may enumerate the functions (both PF and VF) offered by the endpoint of the SSD controller” and use that information to “define” the exposed functions and “help construct the configuration space translation table” ([0042]); that the LWB enumerates the functions of each connected device and “may check to see if there are any other connected devices to enumerate” ([0101]); and that configuration manager 440 determines information about functions exposed by the attached device and stores configuration information in configuration table 435 ([0067]); i.e., detecting a device connected to a downstream connector, determining its configuration, and updating the list. Mesnier likewise teaches “discovery of resources” and “configuring and managing the resources” ([0663]), and SNIA teaches discovery of each CSx and its resources (§ 4.2.2, p. 22). The motivation of claim 8 applies.
Regarding claims 16-17, Mesnier in view of SNIA teaches the multi-function device of claim 10, as set forth above. Claims 16 and 17 recite limitations corresponding to claims 8 and 9 and are rejected for the same reasons, the list entries covering the storage device, the integrated first computational storage unit, and the second computational storage unit (Kachare [0067], [0073], [0101]).
Regarding claim 18, Mesnier discloses a method comprising: determining that a storage device is connected to a multi-function device and determining that first and second computational units are connected to the multi-function device (POD Manager “is responsible for discovery of resources in the POD,” [0663]; FPGA and NVMe resources of RSD 5848 connected to PCIe switch 5846, [0665], FIG. 58C); exposing the storage device to a host processor connected to the multi-function device (switch 5846 “provid[es] access to the target resources (FPGA or NVME in the RSD 5848),” [0665]; [0666]); and selectively making the computational units available to the host (“scaling up or down the amount of pooled resources 5848 connected to a particular compute sled 5840,” [0663]). Mesnier does not expressly teach that the computational units are computational storage units exposed to the host, or selectively exposing them at the multi-function device. SNIA teaches FPGA-based computational storage units exposed to the host as PCIe functions and discovery of each computational storage device and its resources (§§ 3.1.6, 3.1.9, p. 16; § 4.2.2, p. 22; Annex A.4.1, p. 58), and Kachare teaches enumerating each connected device and, in response to host enumeration, exposing functions at the endpoint, where “certain functions … might not get corresponding PFs exposed” ([0101], [0103]). It would have been obvious to combine these teachings with Mesnier for the reasons given for claims 1 and 8.
Regarding claim 19, Mesnier in view of SNIA and Kachare teaches claim 18. SNIA teaches a CSA containing centrally located CSEs (§ 3.1.3, p. 16; § 4.1, p. 22), which renders obvious the first computational storage unit being integrated into the multi-function device for the reasons given for claim 10.
Regarding claim 20, Mesnier in view of SNIA and Kachare teaches claim 18. Kachare teaches determining that a device is connected (enumerating each connected device, [0101]), determining a configuration of the device (enumerating its PFs/VFs, [0042], [0101]), and updating a list of device configurations based on that configuration (configuration manager 440 storing information in configuration table 435, [0067]). The motivation of claim 8 applies.
Allowable Subject Matter
9. Claims 7 and 15 are not rejected over prior art. Claim 15 would be allowable, and claim 7 would be allowable if the rejection under 35 U.S.C. 112(b) set forth above is overcome, if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if the nonstatutory double patenting rejection is overcome.
10. The following is a statement of reasons for the indication of allowable subject matter: the prior art of record does not teach or reasonably suggest, in combination with the other limitations of the claims, a multi-function device comprising bridges that each connect the host connector to a respective device connector, a buffer in the multi-function device connected to the bridges (claim 7) or to the bridges and the integrated computational storage unit (claim 15), wherein a bridge is configured to receive a request from the storage device or a computational storage unit and to direct that request to the buffer. Kachare teaches per-device bridges (APP-EP/APP-RP pairs) between a host endpoint and each attached device ([0073]) but no buffer to which device requests are directed; SNIA teaches peer-to-peer transfer through FDM located in the accelerator (pp. 58-59) rather than a buffer to which bridges of an interposed device route device-originated requests; and Mesnier’s PCIe switch 5846 ([0665]) is not described as including such bridges or buffer.
Examiner's note:
Applicant is reminded that the Examiner has cited particular columns, line numbers, and paragraphs in the applied references for the convenience of the Applicant; other passages and figures of Man and Blaine may apply as well, and Applicant is encouraged to consider the references in their entirety.
Priority
11. Acknowledgment is made of Applicant’s claims for benefit of (a) U.S. Provisional Application Nos. 63/403,679 and 63/403,682, each filed September 2, 2022; (b) U.S. Application No. 18/074,360, filed December 2, 2022 (continuation-in-part relationship), and its U.S. Provisional Application No. 63/292,421, filed December 21, 2021; and (c) U.S. Application No. 16/846,271, filed April 10, 2020 (now U.S. Patent No. 11,809,799), and its U.S. Provisional Application No. 62/865,962, filed June 24, 2019.
12. A claim in a later-filed application, including a continuation-in-part, is entitled to the filing date of an earlier application only if the earlier application (and each intermediate application in the chain) provides written description support under 35 U.S.C. 112(a) for the claimed subject matter. 35 U.S.C. 100(i)(1)(B), 119(e), 120; MPEP 211.05, 2152.01; Studiengesellschaft Kohle m.b.H. v. Shell Oil Co., 112 F.3d 1561, 1564 (Fed. Cir. 1997); Lockwood v. American Airlines, Inc., 107 F.3d 1565, 1571-72 (Fed. Cir. 1997). The claims are not so supported, as follows.
13. Application 16/846,271 / Provisional 62/865,962. Application 16/846,271 (published as US 2020/0401751 A1) discloses a Lightweight Bridge (LWB) 135 whose endpoint 405 exposes physical functions (PFs) to a host, and whose root port(s) 420 connect to one or more SSDs 125 whose PFs and virtual functions (VFs) are mapped to the PFs exposed by the LWB (US 2020/0401751, [0058], [0065], [0067], [0072]-[0073]). The only devices disclosed as connected to the LWB are SSDs (FIGS. 4A-4C; [0072]-[0073]). The application does not describe a computational storage unit connected to or integrated into the bridge, a first and a second computational storage unit, a buffer shared among a storage device and computational storage units, or a data processor operating on such a buffer. The present specification itself relies on 16/846,271 only for “[m]ore information about how exposed functions of the devices attached to connectors 315 and 320 may be exposed by multi-function device 135” (US 2023/0195320, [0071]), and originally identified 16/846,271 only as a related application ([0003]). Because the benefit of provisional 62/865,962 is claimed through 16/846,271, a claim not supported by 16/846,271 cannot obtain the benefit of 62/865,962. Accordingly, none of claims 1-20 is entitled to the April 10, 2020 or June 24, 2019 dates.
14. Application 18/074,360 / Provisional 63/292,421. Application 18/074,360 (published as US 2023/0195372 A1) discloses a device 120 that includes a storage device 305, a network interface device 310, a buffer 340, and a circuit 345 that processes (e.g., transcodes) data in buffer 340 and that “may also be referred to as an accelerator” (US 2023/0195372, [0057], [0059], [0061]). Device 120 may include root ports 1005 connecting multiple storage devices 305 and/or network interface devices 310 ([0109]-[0111]); the root ports may be replaced with FPGAs, ASICs, GPUs, etc., “for example, for protocol translation” ([0112]). The application does not describe (i) a second connector for a first computational storage unit and a third connector for a second computational storage unit, as recited in claim 1; (ii) in addition to an integrated computational storage unit, a connector for communicating with a second computational storage unit, as recited in claim 10 (a network interface device is not a computational storage unit, and the FPGA of [0112] replaces a root port for protocol translation rather than being a computational storage unit attached through a connector); (iii) determining that a second computational storage unit is connected and selectively exposing first and second computational storage units, as recited in claim 18; or (iv) a list of device configurations having entries for the storage device and each computational storage unit, as recited in claims 8-9, 16-17 and 20. Accordingly, none of claims 1-20 is entitled to the December 2, 2022 or December 21, 2021 dates.
15. Claims 1-20 are therefore accorded an effective filing date no earlier than September 2, 2022. All prior art applied above is available under 35 U.S.C. 102(a)(1) as of that date. Should Applicant disagree, Applicant is requested to identify, for each claim, the specific pages and lines of each earlier application that provide written description support for each limitation of that claim.
Response to Arguments
16. Applicant’s arguments filed 08/07/2026] (Remarks, pp. 7-8) that Mesnier and SNIA are not available as prior art have been fully considered but are not persuasive. The arguments are premised on the claims being entitled to the June 24, 2019 date of provisional 62/865,962 or the December 21, 2021 date of provisional 63/292,421. As explained under “Priority” above, claims 1-20 are not entitled to either date. With an effective filing date no earlier than September 2, 2022, Mesnier (US 2022/0188028 A1, published June 16, 2022; also published as WO 2020/186081 on September 17, 2020) and SNIA (published August 30, 2022) are each prior art under 35 U.S.C. 102(a)(1). No named inventor is identified as an author or editor of SNIA, and no exception under 35 U.S.C. 102(b)(1) is apparent on this record. The rejections above are restated with the benefit analysis, updated citations, and a new secondary reference (Kachare, US 2020/0401751 A1) for claims 8-9 and 16-20.
Conclusion
17. All claims remain rejected.
18. The prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure:
US 2018/0181518 A1 (ATI Technologies; US 10,268,620) teaches graphics card with a local PCIe switch connecting NVM controllers and one or more GPUs to a host-side switch, with direct NVM-GPU transfers.
US 2018/0322081 A1 (Liqid) teaches storage enclosure with PCIe switch circuitry coupling bay-mounted storage and graphics modules to a PCIe fabric, with management-processor assignment of resources to hosts.
US 10,509,758 B1 (Amazon) teaches configurable peripheral with emulated switch storing per-device configurations and supporting hot-plug of new endpoints.
US 2013/0024595 A1 (PLX; US 9,141,571) teaches PCIe switch presenting a logical/synthetic endpoint to the host while hiding underlying functions.
US 10,261,936 B2 (Exten/OVH) teaches PCIe switch with a data-path processing array between a host uplink and NVMe/GPU downlinks.
US 2019/0272240 A1 (Samsung; US 10,585,819) and US 2019/0310953 A1 (Samsung) teach FPGA+SSD computational storage with an FPGA/embedded PCIe switch between host and SSD.
SNIA Swordfish Scalable Storage Management API Specification v1.2.2a (June 14, 2021) teaches StorageGroups by which volumes “are collectively exposed or hidden to a set of clients” (§ 5.5.1.6, p. 36).
19. Any inquiry concerning this communication or earlier communications from the examiner should be directed to examiner Raymond Phan, whose telephone number is (571) 272-3630. The examiner can normally be reached on Monday-Friday from 6:30AM- 3:00PM. The Group Fax No. (571) 273-8300.
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/RAYMOND N PHAN/
Primary Examiner, Art Unit 2175
