Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: amendment filed on January 2, 2026.
This application has been examined. Claims 1-20 are pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art t which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under AIA 35 U.S.C. § 103 as being unpatentable over Mesnier et al. (“Mesnier”) (US Pub No. 2020/0188028) in view of SNIA Computational Storage Architecture and Programming Model Ver 1.0 (SNIA, August 30, 2022) (“SNIA”).
In order to expedite and avoid piecemeal prosecution, the following rejection is made to the extent that the claims are understood, by considering those elements which are understood and interpreting their function in a manner which is consistent with the recited goals of the claims, and then applying the best available art.
The examiner relies on the entire teachings of Mesnier and SNIA references; the applicant should carefully consider the entire teachings of the above-mentioned references to better understand the examiner’s position.
In regard to claims 1, 10, 18-19, Mesnier discloses a method, a multi-function device comprising: a first connector for communicating with a storage device (as shown in Fig. 4, which is reproduced below for ease of reference and convenience, Mesnier discloses ports for regular storage devices. See ¶ 95-97: computing device 400 may include a block storage device 452 that may include a compute offload controller 454 and/or a NVM 456. In some embodiments, the block storage device 452 or components thereof may be coupled with other components of the computing device 400. In some embodiments, the block storage device 452 may include a different number of components (e.g., NVM 456 may be located in mass storage 406) or may include additional components of computing device 400 (e.g., processor 402 and/or memory 404 may be a part of block storage device 452). In some embodiments, the compute offload controller 454 may be configured in similar fashion to the compute offload controller 122 described with respect to FIG. 1. In some embodiments, for example, compute offload controller 454 may include a hardware accelerator designed to perform certain compute operations on the data stored on non-volatile memory 456);
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a second connector for communicating with a first computational storage unit (in Mesnier, ports for computational storage units. See ¶ 95-97: computing device 400 may include a block storage device 452 that may include a compute offload controller 454 and/or a NVM 456. In some embodiments, the block storage device 452 or components thereof may be coupled with other components of the computing device 400. In some embodiments, the block storage device 452 may include a different number of components (e.g., NVM 456 may be located in mass storage 406) or may include additional components of computing device 400 (e.g., processor 402 and/or memory 404 may be a part of block storage device 452). In some embodiments, the compute offload controller 454 may be configured in similar fashion to the compute offload controller 122 described with respect to FIG. 1. In some embodiments, for example, compute offload controller 454 may include a hardware accelerator designed to perform certain compute operations on the data stored on non-volatile memory 456); a third connector for communicating with a second computational storage unit (in Mesnier, multiple computational storage units. See ¶ 95-97: computing device 400 may include a block storage device 452 that may include a compute offload controller 454 and/or a NVM 456. In some embodiments, the block storage device 452 or components thereof may be coupled with other components of the computing device 400. In some embodiments, the block storage device 452 may include a different number of components (e.g., NVM 456 may be located in mass storage 406) or may include additional components of computing device 400 (e.g., processor 402 and/or memory 404 may be a part of block storage device 452). In some embodiments, the compute offload controller 454 may be configured in similar fashion to the compute offload controller 122 described with respect to FIG. 1. In some embodiments, for example, compute offload controller 454 may include a hardware accelerator designed to perform certain compute operations on the data stored on non-volatile memory 456); and a fourth connector for communicating with a host processor (in Mesnier, host-facing connector. See ¶ 95-97: computing device 400 may include a block storage device 452 that may include a compute offload controller 454 and/or a NVM 456. In some embodiments, the block storage device 452 or components thereof may be coupled with other components of the computing device 400. In some embodiments, the block storage device 452 may include a different number of components (e.g., NVM 456 may be located in mass storage 406) or may include additional components of computing device 400 (e.g., processor 402 and/or memory 404 may be a part of block storage device 452). In some embodiments, the compute offload controller 454 may be configured in similar fashion to the compute offload controller 122 described with respect to FIG. 1. In some embodiments, for example, compute offload controller 454 may include a hardware accelerator designed to perform certain compute operations on the data stored on non-volatile memory 456). But Mesnier does not expressly disclose wherein the multi-function device is configured to expose the storage device and the first computational storage unit to the host processor via the fourth connector. In the same field of endeavor, SNIA discloses the computational Storage switch or fabric with multiple ports connecting regular storage and Computational Storage Devices (CSDs/CSxes) to the host. The fabric/switch exposes both storage and CSD resources to the host processor. Request routing and forwarding between host, storage, and CSDs via the fabric (as shown in Fig. 4.1, which is reproduced below for ease of reference and convenience, SNIA discloses the computational Storage switch or fabric with multiple ports connecting regular storage and Computational Storage Devices (CSDs/CSxes) to the host. The fabric/switch exposes both storage and CSD resources to the host processor. Request routing and forwarding between host, storage, and CSDs via the fabric. See pages 12-18, 22-28, 35-38: Activation is the process of associating a CSEE with a CSE or associating a CSF with a CSEE. As part of activation of a CSEE, any resources that are necessary for that CSEE to be used on the CSE are assigned. As part of activation of a CSF, any resources that are necessary for that CSF to be used on the CSEE are assigned to the. When a CSEE association with a CSE or a CSF association with a CSEE is no longer required, the CSEE or CSF may be deactivated. This deactivation process releases any assigned resources.
A CSE is required to have a CSEE activated to be able to have a CSF activated. A CSE has FDM associated with it. A CSE is able to have one or more CSEEs and one or more CSFs activated at the time of manufacture that are usable by the host via management and I/O interfaces, or it is able to have one or more CSEEs and one or more CSFs downloaded by the host and activated. A CSE may have CSFs that have been programmed at the time of manufacture that are not changeable (i.e,. not stored in the Resource Repository) (e.g., compression, RAID, erasure coding, regular expression, encryption). CSFs that are stored in the Resource Repository may be activated in a CSEE in a CSE).
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It would have been obvious to a person of ordinary skill in the art (POSITA) before the effective filling date of the claimed invention to a person having ordinary skill in the art to modify the teaching of Mesnier to provide the industry-standard architecture and programming model for computational storage, including the standardized definitions for fabrics/switches, as taught by SNIA, in order to allow better interoperability, easier device enumeration, more reliable selective exposure, and standardized request handling.
In regard to claims 2-3, 11, SNIA discloses wherein the storage device, the first computational storage unit, or the second computational storage unit is configured to invoke a capability of the storage device, the first computational storage unit, or the second computational storage unit (in SNIA, computational storage units invoking capabilities and the fabric forwarding request. See pages 28-32, 40-45: Activation is the process of associating a CSEE with a CSE or associating a CSF with a CSEE. As part of activation of a CSEE, any resources that are necessary for that CSEE to be used on the CSE are assigned. As part of activation of a CSF, any resources that are necessary for that CSF to be used on the CSEE are assigned to the. When a CSEE association with a CSE or a CSF association with a CSEE is no longer required, the CSEE or CSF may be deactivated. This deactivation process releases any assigned resources. A CSE is required to have a CSEE activated to be able to have a CSF activated. A CSE has FDM associated with it. A CSE is able to have one or more CSEEs and one or more CSFs activated at the time of manufacture that are usable by the host via management and I/O interfaces, or it is able to have one or more CSEEs and one or more CSFs downloaded by the host and activated. A CSE may have CSFs that have been programmed at the time of manufacture that are not changeable (i.e,. not stored in the Resource Repository) (e.g., compression, RAID, erasure coding, regular expression, encryption). CSFs that are stored in the Resource Repository may be activated in a CSEE in a CSE). It would have been obvious to a person of ordinary skill in the art (POSITA) before the effective filling date of the claimed invention to a person having ordinary skill in the art to modify the teaching of Mesnier to provide the industry-standard architecture and programming model for computational storage, including the standardized definitions for fabrics/switches, as taught by SNIA, in order to allow better interoperability, easier device enumeration, more reliable selective exposure, and standardized request handling.
In regard to claims 4, 12, SNIA discloses further a buffer connected to the storage device, the first computational storage unit, and the second computational storage unit (in SNIA, shared buffers (AFDM/FDM) that storage devices and computational storage units can access. See pages 42-48: once the configuration process has completed and both CSEE1 and CSEE2 are activated and the CSF1 is ready to process data, the usage process steps (as shown in Figure B.2.8) can occur: 1) The CSF1 is told by the host to execute the function on data; 2) Input Data is pulled from Device Storage into Device Memory, in the Allocated Function Data Memory (AFDM) space of the Function Data Memory (FDM); 3) The data is operated on by the CSF1 and is then stored as Output Data in the Device Storage at the location specified by the function; and 4) The host can then access both the original Input Data and the new Output Data as required to complete the process steps). It would have been obvious to a person of ordinary skill in the art (POSITA) before the effective filling date of the claimed invention to a person having ordinary skill in the art to modify the teaching of Mesnier to provide the industry-standard architecture and programming model for computational storage, including shared buffers, as taught by SNIA, in order to allow better interoperability, easier device enumeration, more reliable selective exposure, and standardized request handling.
In regard to claims 5, 13, SNIA discloses wherein the storage device, the first computational storage unit, and the second computational storage unit are configured to access a data in the buffer (in SNIA, computational storage engine (CSE)/processor that accesses data in the shared buffer. See pages 42-55: See pages 42-48: once the configuration process has completed and both CSEE1 and CSEE2 are activated and the CSF1 is ready to process data, the usage process steps (as shown in Figure B.2.8) can occur: 1) The CSF1 is told by the host to execute the function on data; 2) Input Data is pulled from Device Storage into Device Memory, in the Allocated Function Data Memory (AFDM) space of the Function Data Memory (FDM); 3) The data is operated on by the CSF1 and is then stored as Output Data in the Device Storage at the location specified by the function; and 4) The host can then access both the original Input Data and the new Output Data as required to complete the process steps). It would have been obvious to a person of ordinary skill in the art (POSITA) before the effective filling date of the claimed invention to a person having ordinary skill in the art to modify the teaching of Mesnier to provide the industry-standard architecture and programming model for computational storage, including shared buffers, as taught by SNIA, in order to allow better interoperability, easier device enumeration, more reliable selective exposure, and standardized request handling.
In regard to claims 6, 14, SNIA discloses further comprising a data processor connected to the buffer, the data processor configured to process a data in the buffer (in SNIA, computational storage engine (CSE)/processor that processes data in the shared buffer. See pages 42-48: once the configuration process has completed and both CSEE1 and CSEE2 are activated and the CSF1 is ready to process data, the usage process steps (as shown in Figure B.2.8) can occur: 1) The CSF1 is told by the host to execute the function on data; 2) Input Data is pulled from Device Storage into Device Memory, in the Allocated Function Data Memory (AFDM) space of the Function Data Memory (FDM); 3) The data is operated on by the CSF1 and is then stored as Output Data in the Device Storage at the location specified by the function; and 4) The host can then access both the original Input Data and the new Output Data as required to complete the process steps). It would have been obvious to a person of ordinary skill in the art (POSITA) before the effective filling date of the claimed invention to a person having ordinary skill in the art to modify the teaching of Mesnier to provide the industry-standard architecture and programming model for computational storage, including share buffers, as taught by SNIA, in order to allow better interoperability, easier device enumeration, more reliable selective exposure, and standardized request handling.
In regard to claims 7, 15, SNIA discloses wherein: the multi-function device further comprises: a first bridge connecting the fourth connector and the first connector; a second bridge connecting the fourth connector and the second connector; and a third bridge connecting the fourth connector and the fourth connector; and the buffer is connected to the first bridge, the second bridge, and the third bridge; and the first bridge, the second bridge, or the third bridge is configured to receive a request from the storage device, the first computational storage unit, or the second computational storage unit and to direct the request to the buffer (in SNIA, internal switch/fabric with multiple paths (bridges) from host interface to individual device ports. See pages 66-67: in order to determine if a CSx supports the Data Compression CSF, the CSx must first be discovered as a CSx, with a CSE that is able to perform the function. If the CSE is able to perform a Data Compression CSF, then the CSE must also indicate if the Data Compression CSF allows configuration. If the CSE allows for configuration parameters to the Data Compression CSF, then the configurable parameters must be shared. The following is a possible list of configurable parameters). It would have been obvious to a person of ordinary skill in the art (POSITA) before the effective filling date of the claimed invention to a person having ordinary skill in the art to modify the teaching of Mesnier to provide the industry-standard architecture and programming model for computational storage, including selective exposure of devices to the host, as taught by SNIA, in order to allow better interoperability, easier device enumeration, more reliable selective exposure, and standardized request handling.
In regard to claims 8, 16, 20, SNIA discloses wherein: the multi-function device further comprises a storage for a list of device configurations, the list of device configurations including a first entry for the storage device, a second entry for the first computational storage unit, and a third entry for the second computational storage unit; and the multi-function device is configured to selectively expose the first computational storage unit and the second computational storage unit to the host processor based at least in part on the list of device configurations (in SNIA, device discovery, configuration list/enumeration table, and selective exposure of devices to the host. See pages 66-67: in order to determine if a CSx supports the Data Compression CSF, the CSx must first be discovered as a CSx, with a CSE that is able to perform the function. If the CSE is able to perform a Data Compression CSF, then the CSE must also indicate if the Data Compression CSF allows configuration. If the CSE allows for configuration parameters to the Data Compression CSF, then the configurable parameters must be shared. The following is a possible list of configurable parameters). It would have been obvious to a person of ordinary skill in the art (POSITA) before the effective filling date of the claimed invention to a person having ordinary skill in the art to modify the teaching of Mesnier to provide the industry-standard architecture and programming model for computational storage, including device discovery, configuration list, capability invocation, as taught by SNIA, in order to allow better interoperability, easier device enumeration, more reliable selective exposure, and standardized request handling.
In regard to claims 9, 17, SNIA discloses wherein the multi-function device is configured to detect a device connected to at least one of the second connector or the third connector, determine a configuration of the device, and update the list of device configurations based at least in part on the configuration of the device (in SNIA, device enumeration, and updating the configuration list. See pages 66-67: in order to determine if a CSx supports the Data Compression CSF, the CSx must first be discovered as a CSx, with a CSE that is able to perform the function. If the CSE is able to perform a Data Compression CSF, then the CSE must also indicate if the Data Compression CSF allows configuration. If the CSE allows for configuration parameters to the Data Compression CSF, then the configurable parameters must be shared. The following is a possible list of configurable parameters). It would have been obvious to a person of ordinary skill in the art (POSITA) before the effective filling date of the claimed invention to a person having ordinary skill in the art to modify the teaching of Mesnier to provide the industry-standard architecture and programming model for computational storage, including the device discovery, as taught by SNIA, in order to allow better interoperability, easier device enumeration, more reliable selective exposure, and standardized request handling.
Examiner's note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the Applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passages as taught by the prior art or disclosed by the Examiner.
Conclusion
5. All claims are rejected.
6. Any inquiry concerning this communication or earlier communications from the examiner should be directed to examiner Raymond Phan, whose telephone number is (571) 272-3630. The examiner can normally be reached on Monday-Friday from 6:30AM- 3:00PM. The Group Fax No. (571) 273-8300.
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/RAYMOND N PHAN/
Primary Examiner, Art Unit 2175
Prosecution Insights