DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
The present application, 18108718 filed 02/13/2023 claims foreign priority to KR 10-2022-0124518, filed 09/29/2022.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/13/2023, 03/14/2023 and 03/11/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). See the rejection under 35 U.S.C. 112 below.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: type 1 IMC macros and type 2 IMC macros first recited in claim 1.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
type 1 IMC macros: see Fig. 5a reference numeral 510
type 2 IMC macros: see Fig. 5a reference numeral 520
Each IMC macro includes a memory array, adder tree, multiplexers, and a 1D shift adder
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3 and 13-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites “the operation direction of the type 2 IMC macros” in lines 2-3. There is insufficient antecedent basis for this limitation in the claim. The “operation direction” recited in claim 1 is for an operation direction of performing a multiply and accumulate (MAC) operation in the type 1 IMC macros and not an operation direction of the type 2 IMC macros. For purposes of examination, this is interpreted as “an operation direction of the type 2 IMC macros” instead.
Claim 13 recites “wherein the SRAM IMC device is configured to perform a multiply and accumulation (MAC) operation between an input feature map and a weight” in lines 7-8. This limitation is unclear because it merely states a function (that the SRAM IMC device must somehow perform a multiply and accumulation (MAC) operation between an input feature map and a weight) that is not performed by any structure recited in the claim. It is unclear whether the recited functions follow from the structure recited in the claim, i.e., type 1 IMC macros and type 2 IMC macros, so it is unclear whether the function requires some other structure or is simply a result of operating the system in a certain manner. For purposes of examination, this is interpreted as “wherein the type 1 IMC macros and the type 2 IMC macros are configured to perform a multiply and accumulation (MAC) operation between an input feature map and a weight”. Claims 14-16 inherit the same deficiency as claim 13 by reason of dependence.
Claim 14 recites “the IMC macros” in lines 2 and 3. It is unclear whether this is supposed to be interpreted to refer to the type 1 IMC macros or to the type 2 IMC macros or to both. For purposes of examination, this is interpreted as “the type 1 IMC macros and to the type 2 IMC macros” instead.
Claim 17 recites “a direction of the operation result” in lines 9-10. A direction is normally associated with the operation itself, and an operation result does not normally have a direction. Therefore, it is unclear how an operation result have a direction. For purposes of examination, this is interpreted as “a direction of the MAC operation” instead. Claim 18 inherit the same deficiency as claim 17 by reason of dependence.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 13-16 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 13 recites “type 1 IMC macros, in which a write direction of data is the same as an operation direction, and type 2 IMC macros, in which a write direction of data is different from the operation direction”. An original claim may lack written description support when (1) the claim defines the invention in functional language specifying a desired result but the disclosure fails to sufficiently identify how the function is performed or the result is achieved or (2) a broad genus claim is presented but the disclosure only describes a narrow species with no evidence that the genus is contemplated. The claim recites a broad genus claim to any operation, however, the disclosure only describes a multiply-accumulate operation with no evidence that all possible operations is contemplated. Further, a multiply-accumulate operation is not a representative number of species of all possible operations. For example, if the operation is a write operation, it is not apparent and it is not possible for the type 2 IMC macros to have a write direction of data that is different from the write operation direction. See MPEP 2163.03 subsection V for more information. Claims 14-16 inherit the same deficiency as claim 13 by reason of dependence.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 13-14 and 16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kwon et al. (US 20240061649 A1), hereinafter Kwon. Kwon is cited in the IDS submitted on 03/11/2024.
Regarding claim 13, Kwon teaches a static random access memory (SRAM) in memory computing (IMC) device comprising:
type 1 IMC macros, in which a write direction of data is the same as an operation direction (Kwon Fig. 3 and paragraphs [0042, 0097] type 1 IMC macros – first IMC macro 310; write direction – column direction; an operation direction - column direction), and
type 2 IMC macros, in which a write direction of data is different from the operation direction (Kwon Fig. 3 and paragraphs [0042, 0097] type 2 IMC macros – second IMC macro 330; write direction – row direction), and
wherein the SRAM IMC device is configured to perform a multiply and accumulation (MAC) operation between an input feature map and a weight (Kwon paragraphs [0094-0097]).
Regarding claim 14, Kwon teaches all the limitations of claim 13 as stated above. Further, Kwon teaches wherein either the input feature map or the weight is stored in the IMC macros, and whichever of the two is not written is instead streamed to the IMC macros (Kwon paragraph [0095]).
Regarding claim 16, Kwon teaches all the limitations of claim 13 as stated above. Further, Kwon teaches wherein the type 2 IMC macros are configured to perform an accumulation operation according to the operation direction, with output vectors corresponding to the type 1 IMC macros, respectively, streamed (Kwon Fig. 3 and paragraph [0097]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8-12 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon in view of Kwon.
Regarding claim 1, Kwon teaches an in memory computing (IMC) processor comprising:
a static random access memory (SRAM) IMC device comprising (Kwon Fig. 4 and paragraph [0100] SRAM IMC device - SRAM IMC device 415)
type 1 IMC macros in which a direction of writing data therein is the same as an operation direction of performing a multiply and accumulate (MAC) operation in the type 1 IMC macros (Kwon Fig. 4 and paragraphs [0100-0101] type 1 IMC macros – IMC macro 410), and
wherein the SRAM IMC device is configured to use the type 1 IMC macros (Kwon Fig. 4 and paragraphs [0100-0101]); and
a shift accumulator configured to perform a shift operation on an output of the SRAM IMC device and accumulate a result of the shift operation (Kwon Fig. 4 and paragraphs [0105-0107] shift accumulator – 430).
Fig. 4 of Kwon does not explicitly teach type 2 IMC macros in which a direction of writing data therein is different from the operation direction in the type 1 IMC macros, wherein the SRAM IMC device is configured to use the type 1 IMC macros and the type 2 IMC macros to perform a multiply and accumulation (MAC) operation between an input feature map and a weight.
However, Fig. 3 of Kwon teaches type 2 IMC macros in which a direction of writing data therein is different from an operation direction in the type 1 IMC macros and using the type 2 IMC macros to perform a multiply and accumulation (MAC) operation between an input feature map and a weight (Kwon Fig. 3 and paragraphs [0042, 0097] type 2 IMC macros – IMC macro 330).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Fig. 4 of Kwon and configure the IMC processor to include IMC macros in which a direction of writing data therein is different from the operation direction in the type 1 IMC macros for writing the operation result from the type 1 IMC macros and using the type 2 IMC macros for a subsequent MAC operation by directly storing the input feature maps in the type 2 IMC macros in order to reduce data movement (Kwon paragraphs [0097, 0117]).
Therefore, the combination of Kwon as modified teaches type 2 IMC macros in which a direction of writing data therein is different from the operation direction in the type 1 IMC macros, wherein the SRAM IMC device is configured to use the type 1 IMC macros and the type 2 IMC macros to perform a multiply and accumulation (MAC) operation between an input feature map and a weight.
Regarding claim 2, Kwon teaches all the limitations of claim 1 as stated above. Further, Kwon teaches wherein an output end of a type 1 IMC macro is connected, via the shift accumulator, with an input end of a type 2 IMC macro, and an output end of the type 2 IMC macro is connected with an input end of the type 1 IMC macro (Kwon Figs. 3-4 and paragraphs [0097, 0102]).
Regarding claim 3, Kwon teaches all the limitations of claim 1 as stated above. Further, Kwon teaches wherein each of the type 2 IMC macros is configured to perform an accumulation operation according to the operation direction of the type 2 IMC macros by receiving one bit according to the direction of the writing of the type 2 IMC macros (Kwon Fig. 3 and paragraphs [0097, 0148]).
Regarding claim 4, Kwon teaches all the limitations of claim 1 as stated above. Further, Kwon teaches wherein each of the type 2 IMC macros is configured to perform their MAC operation by receiving bits according to the direction of writing of the type 2 IMC macros (Kwon Figs. 3, 5, 7 and paragraphs [0097, 0139, 0148]).
Regarding claim 5, Kwon teaches all the limitations of claim 1 as stated above. Further, Kwon teaches wherein the SRAM IMC device is configured to perform the MAC operation between the input feature map and the weight by storing the input feature map in a type 1 IMC macro while the weight is streamed into the type 1 IMC macro (Kwon Figs. 3-5 and paragraph [0102, 0109, 0121]).
Regarding claim 6, Kwon teaches all the limitations of claim 5 as stated above. Further, Kwon teaches wherein the shift accumulator is configured to perform a first-direction partial sum operation by performing a shift operation on a MAC operation result of each of the type 1 IMC macros and by accumulating the result of the shift operation (Kwon Fig. 4 and paragraph [0107]).
Regarding claim 8, Kwon teaches all the limitations of claim 1 as stated above. Further, Kwon teaches wherein the shift accumulator comprises a buffer, wherein the buffer comprises: a first region storing or accumulating a MAC operation result corresponding to the type 1 IMC macros; and a second region for preventing data loss arising from the shift operation, and wherein a size of the first region and a size of the second region are determined based on a size of the type 1 IMC macros (Kwon Fig. 6 and paragraph [0129, 0132, 0135] buffer – 600; first region – 610; second region – 630).
Regarding claim 9, Kwon teaches all the limitations of claim 1 as stated above. Further, Kwon teaches wherein the shift accumulator is configured to be capable of performing the shift operation on a MAC operation result in a left direction and in a right direction, and is configured to accumulate the result of the shift operation (Kwon Fig. 6 and paragraph [0131]).
Regarding claim 10, Kwon teaches all the limitations of claim 1 as stated above. Further, Kwon teaches wherein the MAC operation comprises a linear operation or a convolution operation (Kwon paragraph [0101).
Regarding claim 11, Kwon teaches all the limitations of claim 1 as stated above. Further, Kwon teaches wherein the IMC processor is integrated into either a mobile device, a mobile computing device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, a music player, a video player, an entertainment unit, a navigation device, a communication device, an Internet of Things (IoT) device, a global positioning system (GPS) device, a television, a tuner, an automobile, an automotive part, an avionics system, a drone, a multi-copter, an electric vertical takeoff and landing (eVTOL) aircraft, or a medical device (Kwon paragraph [0115]).
Regarding claim 12, Kwon teaches all the limitations of claim 1 as stated above. Further, Kwon teaches wherein the shift accumulator is configured to perform an accumulation operation according to the operation direction, with output vectors corresponding to the type 1 IMC macros, respectively, streamed (Kwon paragraphs [0130-0131]).
Regarding claim 15, Kwon teaches all the limitations of claim 13 as stated above. Fig. 3 of Kwon does not explicitly teach further comprising an input streamer configured to delay a weight map corresponding to each of the type 1 IMC macros by as much as a unit cycle and stream the delayed weight map to an applicable one of the type 1 IMC macros.
However, Fig. 4 of Kwon discloses an input streamer configured to delay a weight map corresponding to each of the type 1 IMC macros by as much as a unit cycle and stream the delayed weight map to an applicable one of the type 1 IMC macros (Kwon Figs. 4, 7 and paragraph [0109] input streamer - 450).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Fig. 3 of Kwon and configure the device to include an input streamer configured to delay a weight map corresponding to each of the type 1 IMC macros by as much as a unit cycle and stream the delayed weight map to an applicable one of the type 1 IMC macros for reading and applying the weight maps thereby enabling partial sums of different input channels to be summed by a 2D shift accumulator without performance degradation (Kwon paraphs [0110-0111, 0136-0141]).
Therefore, the combination of Kwon as modified teaches an input streamer configured to delay a weight map corresponding to each of the type 1 IMC macros by as much as a unit cycle and stream the delayed weight map to an applicable one of the type 1 IMC macros.
Allowable Subject Matter
Claims 17-18 would be allowable if rewritten to overcome the 35 U.S.C. 112(b) rejection discussed above.
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
None of the prior art references cited explicitly teach or suggest the concept of using the type 2 IMC macros to accumulate the result/output of the shift accumulator. Fig. 3 and paragraphs [0097] of Kwon discloses using the IMC macro 330 for performing a MAC operation for the next layer of a neural network instead of using the IMC macro 330 to perform an accumulation operation. Therefore, none of the prior art references cited explicitly teach or suggest, in combination with other limitations of the claims, “wherein the SRAM IMC device is further configured to accumulate a result of the first-direction partial sum operation using the type 2 IMC macros” as recited in claim 7; and “accumulating a result of the first-direction partial sum operation, using type 2 IMC macros of the IMC processor, in which the write direction of the data is different from a direction of the operation result” as recited in claim 17.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Badaroglu et al. (US 20230115373 A1), Seo et al. (US 20220318610 A1) and Deshpande et al. (US 20230022347 A1) are generally related to a SRAM IMC device for performing MAC operations.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlo Waje whose telephone number is (571)272-5767. The examiner can normally be reached 9:00-6:00 M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Trujillo can be reached at (571) 272-3677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Carlo Waje/Examiner, Art Unit 2151 (571)272-5767
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