DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
The present application, 18109690, filed 02/14/2023 claims foreign priority to KR10-2022-0019574, filed 02/15/2022; claims foreign priority to KR10-2023-0001234, filed 01/04/2023.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/14/2023 and 10/16/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
A. floating-point units first recited in claim 1
B. input unit first recited in claim 7
C. suboperation units first recited in claim 7
D. operation unit in claims 10-12
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
A. floating-point units (first recited in claim 1): See Fig. 4(c) and paragraph [0041] the floating-point units includes multipliers, an adder and a shifter
B. input unit (first recited in claim 7) are conventional inputs
C. suboperation units (first recited in claim 7): See Figs. 2 and 4 and paragraph [0041]; the suboperation units are multipliers.
D. operation unit (in claims 10-12): See Fig. 4(c) the operation unit further includes a shifter and an adder
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-6 and 9-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “the respective floating-point units” in line 8. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, this is interpreted as respective floating-point units instead. Claim 3 recites a similar limitation and is rejected for the same reason. Claims 2-6 inherit the same deficiency as claim 1 by reason of dependence. Claim 4-6 inherit the same deficiency as claim 3 by reason of dependence.
Claim 4 recites “the suboperation result value” in line 2. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, this is interpreted as a suboperation result value instead. Claim 5-6 inherit the same deficiency as claim 4 by reason of dependence.
Claim 9 recites “the respective suboperation units” in line 3. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, this is interpreted as respective suboperation units. Claim 10-12 inherit the same deficiency as claim 9 by reason of dependence.
Further, claim 9 recites “wherein the first floating-point data and the second floating- point data are divided into sizes capable of being input to the suboperation units”. This limitation is unclear because it merely state a function (that the first floating-point data and the second floating- point data must somehow be divided into sizes capable of being input to the suboperation units) that is not performed by any structure recited in the claim. The recited function does not follow from the structure recited in the claim, i.e., the input unit and the operation unit, so it is unclear whether the function requires some other structure or is simply a result of operating the apparatus in a certain manner. Further, clarification is required. Claim 10-12 inherit the same deficiency as claim 9 by reason of dependence.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-12 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Under the Alice Framework Step 1, claims 1-6 recite a series of steps and, therefore, is a process. Claims 7-12 recite an apparatus and, therefore, is a machine.
Under Step 2A prong 1, claim 1 recites
A method for outer-product-based matrix multiplication for a floating-point data type, which is performed by multiple floating-point units, comprising:
receiving first floating-point data and second floating-point data; and
performing matrix multiplication on the first floating-point data and the second floating- point data,
wherein a result value of the matrix multiplication is calculated based on suboperation result values of the respective floating-point units.
The above limitations of performing matrix multiplication using an outer-product technique amounts to processing calculations and falls within the “Mathematical Concepts” and “Mental Processes” grouping of abstract ideas. The step of “performing matrix multiplication” is a process that under its broadest reasonable interpretation, covers performance of the limitation in the mind. That is, other than reciting “multiple floating-point units”, nothing in the claim element precludes the step from practically being performed in the human mind. For example, but for the “multiple floating-point units” language, the claim encompasses manually multiplying a four element column vector comprising first floating-point data with another four element row vector comprising second floating-point data to generate a sixteen element intermediate result matrix that are used to obtain a final result value as shown in Fig. 1B using pen and paper. Accordingly, the claim is directed to recite an abstract idea.
Under step 2A prong 2, the claim recites the following additional elements: floating-point units and receiving first floating-point data and second floating-point data. However, the additional element of “floating-point units” is recited at a high-level of generality (i.e., as generic floating-point units for performing floating-point operations) such that it amounts to no more than merely reciting the words “apply it” (or an equivalent) with the judicial exception or no more than mere instructions using a generic computer component or merely as a tool to implement the abstract idea. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f)(2) for more information. The additional elements of “receiving first floating-point data and second floating-point data” is merely adding an insignificant extra-solution activity, i.e. mere data gathering. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under step 2B, claim 1 does not include additional elements that, individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “floating-point units” is recited at a high-level of generality (i.e., as generic floating-point units for performing floating-point operations) such that it amounts to no more than merely reciting the words “apply it” (or an equivalent) with the judicial exception or no more than mere instructions using a generic computer component or merely as a tool to implement the abstract idea. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f)(2) for more information. The additional elements of “receiving first floating-point data and second floating-point data” is merely adding an insignificant extra-solution activity, i.e. mere data gathering. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Receiving or transmitting data over a network” and “Storing and retrieving information in memory” as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Under step 2A prong 1, claims 2-6 recite the same abstract idea as claim 1 by reason of dependence. Further, claim 2 recites further details of the abstract idea of the matrix multiplication “wherein the suboperation result values correspond to intermediate result values of an outer product of the first floating-point data and the second floating-point data”; claim 3 recites further abstract idea of “wherein the first floating-point data and the second floating- point data are divided into sizes capable of being input”; claim 4 recites further details of the abstract idea of the matrix multiplication “wherein performing the matrix multiplication comprises performing a shift operation and an addition operation on the suboperation result value of each of the floating-point units”; claim 5 recites further details of the abstract idea of the matrix multiplication “herein each of the first floating-point data and the second floating-point data is divided into upper bits and lower bits”; and claim 6 recites further details of the abstract idea of the matrix multiplication “wherein performing the matrix multiplication comprises performing a shift operation, corresponding to double a size of the lower bits, on a result value of a suboperation performed on the upper bits of the first floating-point data and the upper bits of the second floating-point data, and performing a shift operation, corresponding to the size of the lower bits, on a result value of a suboperation performed on the upper bits of the first floating-point data and the lower bits of the second floating-point data and on a result value of a suboperation performed on the lower bits of the first floating-point data and the upper bits of the second floating-point data” which falls within the “Mathematical Concepts” and “Mental Processes” grouping of abstract ideas. In particular claims 2 and 4-6 do not include additional elements that would require further analysis under step 2A prong 2 and step 2B. Accordingly, the claims are directed to recite an abstract idea.
Under step 2A prong 2, claim 3 recites the following additional elements: input. However, the additional elements of “input” to the respective floating-point units is merely adding an insignificant extra-solution activity, i.e. mere data gathering. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under step 2B, claim 3 does not include additional elements that, individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “input” to the respective floating-point units is merely adding an insignificant extra-solution activity, i.e. mere data gathering. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Receiving or transmitting data over a network” and “Storing and retrieving information in memory” as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Under Step 2A prong 1, claim 7 recites
An apparatus for outer-product-based matrix multiplication for a floating-point data type, comprising:
an input unit for receiving first floating-point data and second floating-point data; and
an operation unit for performing matrix multiplication on the first floating-point data and the second floating-point data,
wherein the operation unit includes suboperation units for calculating suboperation result values for a result value of the matrix multiplication.
The above limitations of performing matrix multiplication using an outer-product technique amounts to processing calculations and falls within the “Mathematical Concepts” and “Mental Processes” grouping of abstract ideas. The step of “performing matrix multiplication” is a process that under its broadest reasonable interpretation, covers performance of the limitation in the mind. That is, other than reciting “an operation unit that includes suboperation units”, nothing in the claim element precludes the step from practically being performed in the human mind. For example, but for the “an operation unit that includes suboperation units” language, the claim encompasses manually multiplying a four element column vector comprising first floating-point data with another four element row vector comprising second floating-point data to generate a sixteen element intermediate result matrix that are used to obtain a final result value as shown in Fig. 1B using pen and paper. Accordingly, the claim is directed to recite an abstract idea.
Under step 2A prong 2, the claim recites the following additional elements: an input unit for receiving first floating-point data and second floating-point data; an operation unit; and suboperation units. However, the additional element of “an input unit”, “an operation unit” and “suboperation units” are recited at a high-level of generality (i.e., as a generic input unit for receiving inputs; and as a generic operation unit comprising suboperation units for performing mathematical operations) such that they amount to no more than merely reciting the words “apply it” (or an equivalent) with the judicial exception or no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f)(2) for more information. The additional elements of “receiving first floating-point data and second floating-point data” is merely adding an insignificant extra-solution activity, i.e. mere data gathering. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under step 2B, claim 7 does not include additional elements that, individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element of “an input unit”, “an operation unit” and “suboperation units” are recited at a high-level of generality (i.e., as a generic input unit for receiving inputs; and as a generic operation unit comprising suboperation units for performing mathematical operations) such that they amount to no more than merely reciting the words “apply it” (or an equivalent) with the judicial exception or no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f)(2) for more information. The additional elements of “receiving first floating-point data and second floating-point data” is merely adding an insignificant extra-solution activity, i.e. mere data gathering. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Receiving or transmitting data over a network” and “Storing and retrieving information in memory” as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Regarding claims 8-12, they recite substantially the same limitations as claims 2-6 respectively. Claims 2-6 analysis applies equally to claims 8-12 respectively.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 and 7-9 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lin (US 20230342419 A1).
Regarding claim 1, Lin teaches a method for outer-product-based matrix multiplication for a floating-point data type, which is performed by multiple floating-point units, comprising (Lin Figs. 4B-5E, 11-12 and paragraphs [0059, 0074, 0093, 0096] multiple floating-point units – PEs and adder/accumulator):
receiving first floating-point data and second floating-point data (Lin Fig. 4B, 5A-5D and 9-12; and paragraphs [0085, 0093, 0120, 0123] first floating-point data – matrix A; second floating-point data – matrix B); and
performing matrix multiplication on the first floating-point data and the second floating- point data (Lin Figs. 5B-5D and 12; paragraphs [0096, 0099, 0140]),
wherein a result value of the matrix multiplication is calculated based on suboperation result values of the respective floating-point units (Lin Figs. 5E, 12 and paragraphs [0101, 0140] result value – result matrix; suboperation result values - elements of the intermediate result matrix C0-C3/elements of the fourth matrices).
Regarding claim 2, Lin teaches all the limitations of claim 1 as stated above. Further, Lin teaches wherein the suboperation result values correspond to intermediate result values of an outer product of the first floating-point data and the second floating-point data (Lin Figs. 5B-5D, 12 and paragraphs [0096, 0099, 0101, 0140] intermediate result values – elements of the intermediate result matrix C0-C3/ elements of the fourth matrices).
Regarding claim 3, Lin teaches all the limitations of claim 2 as stated above. Further, Lin teaches wherein the first floating-point data and the second floating- point data are divided into sizes capable of being input to the floating-point units and are then input to the respective floating-point units (Lin Figs. 11-12 and paragraphs [0131-0132, 0139-0140]).
Regarding claim 7, Lin teaches an apparatus for outer-product-based matrix multiplication for a floating-point data type, comprising:
an input unit for receiving first floating-point data and second floating-point data (Lin Fig. 4B, 5A-5D and 9-12; and paragraphs [0085, 0093, 0120, 0123] first floating-point data – matrix A; second floating-point data – matrix B; input unit – component receiving the input matrices); and
an operation unit for performing matrix multiplication on the first floating-point data and the second floating-point data (Lin Figs. 4A-5E, 11-12 and paragraphs [0059, 0074, 0083, 0096, 0099, 0140] operation unit – matrix calculation apparatus (vector outer product processing engine 401 and accumulator 402),
wherein the operation unit includes suboperation units for calculating suboperation result values for a result value of the matrix multiplication (Lin Figs. Figs. 4B-5E, 11-12 and paragraphs [0085-0086, 0101, 0140] result value – result matrix; suboperation units - PEs and adder/accumulator; suboperation result values - elements of the intermediate result matrix C0-C3/elements of the fourth matrices).
Regarding claim 8, Lin teaches all the limitations of claim 7 as stated above. Further, Lin teaches wherein the suboperation result values correspond to intermediate result values of an outer product of the first floating-point data and the second floating-point data (Lin Figs. 5B-5D, 12 and paragraphs [0096, 0099, 0101, 0140] intermediate result values – elements of the intermediate result matrix C0-C3/ elements of the fourth matrices).
Regarding claim 9, Lin teaches all the limitations of claim 8 as stated above. Further, Lin teaches wherein the first floating-point data and the second floating- point data are divided into sizes capable of being input to the suboperation units and are then input to the respective suboperation units (Lin Figs. 11-12 and paragraphs [0131-0132, 0139-0140]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-6 and 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Lin as applied to claims 1 and 7 above, and further in view of Makino et al. (US 20210011686 A1), hereinafter Makino.
Regarding claim 10, Lin teaches all the limitations of claim 9 as stated above. Further, Lin teaches wherein the operation unit performs (Lin Figs. Figs. 5B-5E, 12 and paragraphs [0101 and 0140]).
Lin does not explicitly teach wherein the operation unit performs a shift operation and an addition operation on the suboperation result value of each of the suboperation units.
However, on the same field of endeavor, Makino discloses performing a multiplication operation using divided inputs to generate a plurality of partial products that are shifted then added to generate the final product (Makino Figs. 3-4, 12 and paragraphs [0084-0091, 0141] ).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Lin and using Makino and configure the matrix calculation apparatus to include shift circuitry to perform a shift operation before the addition on the suboperation result values in order to correctly calculate each matrix result by properly aligning the suboperation result values before the addition (Makino paragraph [0091]). As disclosed in Figs. 11-12 and paragraphs [0139-0140] of Lin, each element of the input vectors is split into two portions, therefore, appropriate shifts must be performed similar to the partial product alignments of A10xB10, A11x10, A10xB11 and A11xB11 shown in Fig. 3 of Makino on each element of the fourth matrices 1-4 in order to correctly calculate each element value of the intermediate result matrix C0. For example, in order to properly calculate element a0b0 of matrix C0 in Fig. 5C, assuming M denotes the most significant bits and L denotes the least significant bits in Figs. 11-12 of Lin, a0Mb0M must be shifted by 28 bits since a0M and b0M are 14 bits; and a0Lb0M and a0Lb0M must be shifted by 14 bits before adding them with a0Lb0L to obtain the a0b0 value of matrix C0.
Therefore, the combination of Lin as modified in view of Makino teaches wherein the operation unit performs a shift operation and an addition operation on the suboperation result value of each of the suboperation units.
Regarding claim 11, of Lin as modified in view of Makino teaches all the limitations of claim 10 as stated above. Further, of Lin as modified in view of Makino teaches wherein each of the first floating-point data and the second floating-point data is divided into upper bits and lower bits (Lin Figs. 11-12 and paragraphs [0131-0133] upper bits – integer and first 13 bits of the mantissa (14 bits in total); lower bits – bit 14-23 including the additional padded 0s (14 bits in total)).
Regarding claim 12, of Lin as modified in view of Makino teaches all the limitations of claim 11 as stated above. Further, of Lin as modified in view of Makino teaches wherein the operation unit performs a shift operation, corresponding to double a size of the lower bits, on a result value of a suboperation performed on the upper bits of the first floating-point data and the upper bits of the second floating-point data (Makino Fig. 3 shows A10xB10 is shifted by 2-unit-bit-length. The reason to combine is the same as claim 4.), and performs a shift operation, corresponding to the size of the lower bits, on a result value of a suboperation performed on the upper bits of the first floating-point data and the lower bits of the second floating-point data and on a result value of a suboperation performed on the lower bits of the first floating-point data and the upper bits of the second floating-point data (Makino Fig. 3 shows A10xB11 and A11xB10 are shifted by 1-unit-bit-length. The reason to combine is the same as claim 4).
Regarding claims 4-6, they are directed to a method and recite substantially the same limitations as the apparatus of claims 10-12 respectively. Claims 10-12 analysis applies equally to claims 4-6 respectively.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Fleischer et al. (US 20210049230 A1) related to performing an outer-product-based matrix multiplication for a floating-point data type.
Ryu et al. (US 20200394504 A1) related to performing matrix multiplication using divided inputs and performing shift and add operations on the intermediate results to obtain the output result.
Won et al. (NPL – “M3FPU: Multiformat Matrix Multiplication FPU Architectures for Neural Network Computations”) related to performing an outer-product-based matrix multiplication for a floating-point data type.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlo Waje whose telephone number is (571)272-5767. The examiner can normally be reached 9:00-6:00 M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Trujillo can be reached at (571) 272-3677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Carlo Waje/Examiner, Art Unit 2151 (571)272-5767
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