DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
This is a final office action for application 18/109,750 in response to the amendment(s) filed on 03/06/2026. Claims 2-14 and 16-18 are under examination.
Withdrawn Objections
The amendment(s) to the claim(s) filed 03/06/2026 is acknowledged and the previous claim objections are withdrawn.
Response to Arguments
Applicant’s arguments filed on 03/06/2026 have been fully considered but are not persuasive with respect to the currently pending claims for the reasons set forth below. The previous rejections have been withdrawn or modified where appropriate, and the claims are rejected on the grounds set forth below.
Applicant argues that “drawings are now in compliance because the specification has been amended to include the previously missing reference numbers” (see e.g. pages 6-7 of applicant’s arguments).
Examiner agrees in part. The previous drawing objections have been withdrawn. However, reference character A in FIG. 6C is still missing from the specification. For the above reason, Applicant’s arguments are persuasive to the previous objection but do not overcome the new objection of FIG. 6C.
Applicant argues that “the rejection of claims 1-18 under 35 U.S.C. 112(b) should be withdrawn because claims 1 and 15 have been canceled and the pending claims have been amended to address the antecedent basis issues” (se e.g. page 8 of Applicant’s arguments).
Examiner agrees in part. The previous rejection under 35 U.S.C. 112(b) has been withdrawn in view of Applicant’s amendments. However, amended claim 9 now recites “the spacer housing,” while only “a PCB spacer housing” was properly introduced in independent claim 16. Accordingly, claim 9 is rejected under 35 U.S.C. 112(b) for lack of antecedent basis as set forth below. For the above reasons, Applicant’s arguments are persuasive as to the previous 112(b) rejection, but do not overcome the new 112(b) rejection of claim 9.
Applicant argues that “the rejection of claims 1, 2, 6, 8, 13, 15, and 17 under 35 U.S.C. 102(a)(1) over Park should be withdrawn because claims 1 and 15 have been canceled and claims 2, 6, 8, 13, and 17 now depend from claim 16, which Applicant asserts is in condition for allowance” (see e.g. page 8 of Applicant’s arguments).
Examiner agrees in part. The previous anticipation rejection under 35 U.S.C. 102(a)(1) over Park has been withdrawn. However, Applicant’s argument that claim 16 is in condition for allowance is not persuasive. As set forth below, amended independent claim 16 is rejected under 35 U.S.C. 103 over Park in view of Varipatis. Park discloses the first printed circuit board, second printed circuit board, PCB spacer/interposer, PCB spacer housing/dielectric substrate, board-to-board terminals/conductive terminals and vias, opposed first and second sides, and interior opening receiving mounted components. Varipatis teaches filling a volume/opening over PCB-mounted electronic components with potting material to cover/encapsulate the components and protect them from contaminants such as water, metal, and dust. Therefore, claims 2, 6, 8, 13, and 17 are not allowable merely because they depend from claim 16. For the above reasons, Applicant’s arguments are persuasive as to withdrawal of the previous 102 rejection, but are not persuasive as to patentability of the currently pending claims.
Applicant argues that “claim 16 is not rendered obvious by Park in view of Yamashita because Yamashita does not teach or suggest a potting material in an interior opening of a PCB spacer and does not teach covering electronic components with potting material” (see e.g. pages 8-12 of Applicant’s arguments).
Examiner agrees in part. Applicant’s arguments have been considered and the previous rejection of claim 16 over Park in view of Yamashita has been overcome. However, in light of the amendments/arguments a new search was conducted and new prior art identified. The present rejection no longer relies on Yamashita for the potting material limitation of claim 16. Instead, claim 16 is rejected over Park in view of Varipatis. Park is relied upon for the PCB spacer/interposer, the interior opening, and the mounted components received in the interior opening. Varipatis is relied upon for teaching potting material applied in a volume/opening over PCB-mounted electronic components to cover/encapsulate the components and protect them from contamination. Accordingly, Applicant’s arguments regarding Yamashita are moot with respect to the newly stated rejection of claim 16 over Park in view of Varipatis.
In conclusion, Applicant’s arguments were persuasive to the extent that the previous 112(b) rejection and the previous 102 rejection over Park have been withdrawn, and the previous rejection of claim 16 over Park in view of Yamashita has been overcome. However, the arguments do not place the currently pending claims in condition for allowance because the amended claims are rejected under the grounds set forth below.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: FIG. 6C: part number A .
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites the limitation "the spacer housing". However, only “a PCB spacer housing” was properly introduced in claim 16 and thus there is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
Claims 2, 6, 8, 13 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US-20210144856-A1) and further in view of Varipatis et al. (US-20170365826-A1).
Regarding Claim 16, Park discloses a battery pack (see e.g. "electronic device" in paragraph [0008]) comprising:
a first printed circuit board (see e.g. "first PCB" in paragraph [0045] and part number 420 in FIG. 4);
a second printed circuit board (see e.g. "second PCB" in paragraph [0045] and part number 430 in FIG. 4); and
a PCB spacer (see e.g. "interposer" in paragraph [0045] and part number 440 in FIGs. 4 and 6A-6C), the PCB spacer including a PCB spacer housing (see e.g. "dielectric substrate" in paragraph [0048] and part number 441 in FIG. 5) and at least two board-to-board terminals (see e.g. "plurality of conductive terminals" and "the plural conductive terminals 442 may be electrically connected through a conductive via 444 in FIG. 6, or a conductive post penetrating from the first substrate surface 4401 of the dielectric substrate 441 to the second substrate surface 4402. " in paragraph [0048] and part number 442 in FIG. 5 and part number 444 in FIG. 6 electrically coupled to the conductive terminals of the first and second PCB);
the first printed circuit board coupled to a first side of the PCB spacer (see e.g. "the interposer 440 may be preferentially mounted on the first PCB 420 through pre-solder applied to the conductive terminals" in paragraph [0045] and part number 420 in FIG. 4) and the second printed circuit board coupled to a second side of the PCB spacer (see e.g. "the interposer 440 may be preferentially mounted on the second PCB 420 through pre-solder applied to the conductive terminals" in paragraph [0045] and part number 430 in FIG. 4), the first side of the PCB spacer being opposed to the second side of the PCB spacer (see e.g. part numbers 420, 430 and 440 in FIG. 6A),
wherein the PCB spacer includes an interior opening defined by sides of the PCB spacer housing (see e.g. "opening 4404" in paragraph [0049] and part number 4404 in FIG. 5), the interior opening receives one or more of a plurality of components mounted on a surface of the first printed circuit board facing the PCB spacer (see e.g. " the opening 4404 may be utilized as a receiving space for accommodating electrical elements or a shield can arranged on at least one of the two PCBs 420 and 430." in paragraph [0049] and part number 425 in FIG. 6A; electrical element 425 is disposed on the surface of the first PCB 420 in the opening of the PCB spacer housing).
Park does not disclose that the interior opening is filled with a potting material to cover the plurality of mounted components.
Varipatis, however, in the same field of endeavor, battery packs with printed circuit boards, discloses a volume/opening over mounted components of a printed circuit board (see e.g. “the LPM material 66 may be molded such that a potting wall 68 is formed around and encapsulates a portion of the perimeter of the PCB 34” and “The potting wall 68 along with the top surface 60 of the PCB 34 form a volume 70” in paragraph [0075] and part numbers 66, 68 and 70 in FIGs. 6-7 of Varipatis) wherein that volume/opening is filled with a potting material to cover/encapsulate the plurality of mounted components (see e.g. “a potting material or conformal coating material 74 may be applied to the top surface/side 60 of the PCB 34 in the volume 70 created by the potting wall 68 and the top side 60 of the PCB 34” in paragraph [0076] and part number 74 in FIGs. 9A-10B of Varipatis; potting material 74 is applied in volume 70 over the electronic components 48 mounted on the top surface 60 of PCB 34).
Varipatis also teaches that the potting material protects the electronic components that populate the PCB of the battery pack from contamination including water, metal, and dust (see e.g. paragraphs [0003]-[0010] of Varipatis).Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the interior opening of Park et al. such that the interior opening is filled with a potting material to cover the plurality of mounted components as taught by Varipatis et al. in order to encapsulate/cover and protect the mounted electronic components on the printed circuit board from contaminants such as water, metal, and dust, as suggested by Varipatis.
Park in view of Varipatis does not explicitly disclose that the PCB spacer housing is injection molded around the board-to-board terminals.
Park, however, discloses the PCB spacer is formed around the board to board terminals (see e.g. part numbers 441 and 442 in FIGs. 5 and 6A-6C; the housing (441) is formed around the conductive terminals (442) in FIGs. 6 and 6A-6C). Furthermore, the limitation that the PCB spacer housing is injection molded around the board-to-board terminals is a product-by-process limitation. The patentability of a product does not depend on the method by which is was produced. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. As explained above, Park discloses a PCB spacer housing that is formed around and surrounds the board-to-board terminals making the PCB spacer housing structurally the same and thus is anticipated by the prior art. See MPEP 2113.
Regarding Claim 2, Park in view of Varipatis disclose the battery pack of claim 16 (see e.g. claim 16 rejection above).
Park further discloses that the board-to-board terminals electrically connect the first printed circuit board to the second printed circuit board (see e.g. "a first PCB 420 disposed in the internal space and including a plurality of first conductive terminals 421, a second PCB 430 disposed substantially parallel to the first PCB 420 and including a plurality of second conductive terminals 431, and an interposer 440 disposed between the first PCB 420 and the second PCB 430 to electrically connect the first PCB 420 and the second PCB 430" in paragraph [0053] and part numbers 421, 431, 442, 443 and 444 in FIG. 6A; the first PCB and second PCB are electrically connected through the conductive terminals and vias of the PCB spacer).
Regarding Claim 6, Park in view of Varipatis disclose the battery pack of claim 16 (see e.g. claim 16 rejection above).
Park further discloses that the spacer housing has a generally planar, rectangular shape (see e.g. FIG. 5).
Regarding Claim 8, Park in view of Varipatis disclose the battery pack of claim 16 (see e.g. claim 16 rejection above).
Park in view of Varipatis does not explicitly disclose the PCB spacer is formed by an injection molding process.
Park, however, discloses a PCB spacer that has the same structure and functionality as the PCB spacer claimed by the instant application. Furthermore, the limitation that the PCB spacer is formed by an injection molding process is a product-by-process limitation. The patentability of a product does not depend on the method by which is was produced. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. As explained above, Park discloses a PCB spacer housing that is structurally the same and has the same functionality as the PCB spacer claimed in the instant application and thus is anticipated by the prior art. See MPEP 2113.
Regarding Claim 13, Park in view of Varipatis disclose the battery pack of claim 16 (see e.g. claim 16 rejection above).
Park further discloses that the battery pack comprises a battery pack housing (see e.g. "housing" in paragraph [0022] and part number 110 in FIG. 1), the battery pack housing forming an interior cavity (see e.g. FIG. 4; the interior space of the housing); a set of battery cells (see e.g. "battery" in paragraph [0039] and part number 350 in FIG. 3); a battery cell holder housing the set of battery cells (see e.g. "second support member" in paragraph [0035] and part number 360 in FIG. 3; the battery cells sit within the second support member housing), the battery cell holder positioned within the interior cavity (see e.g. part number 360 in FIG. 3; the second support member sits within the battery pack housing inside of the electronic device), the first printed circuit board being coupled to the battery cell holder (see e.g. "At least a part of the battery 350 may be disposed on substantially the same plane as the PCB 340." in paragraph [0039] and part number 340 in FIG. 3; the first PCB sits directly on the battery cell holder).
Regarding Claim 17, Park in view of Varipatis disclose the battery pack of claim 16 (see e.g. claim 16 rejection above).
Park further discloses that the battery pack further comprises a hold-down screw mechanically coupling the second printed circuit board and the PCB spacer to the first printed circuit board (see e.g. "a fastening member such as a screw, firmly supporting the electrical connection between the first PCB 420, the interposer 440, and the second PCB 430" in paragraph [0045]).
Claims 3-5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US-20210144856-A1) in view of Varipatis et al. (US-20170365826-A1) as applied to claim 16 above, and further in view of Yamashita et al. (US-5031308-A).
Regarding Claim 3, Park in view of Varipatis disclose the battery pack of claim 16 (see e.g. claim 16 rejection above).
Park in view of Varipatis does not disclose that the first printed circuit board includes terminal holes to receive the board-to-board terminals and the second PCB includes terminal holes to receive the board-to-board terminals.
Yamashita, however, in the same field of endeavor, multilayered printed circuit boards, discloses that the first printed circuit board includes terminal holes (see e.g. "each of the double-face PWB 110, 112 has a through-hole 138" in Column 6 lines 24-26 part number 138 in FIG. 1 of Yamashita) to receive the board-to-board terminals (see e.g. "solder bumps" in Column 6 line 31 and part numbers 136a and 136b in FIG. 1 of Yamashita) and the second PCB includes terminal holes (see e.g. "each of the double-face PWB 110, 112 has a through-hole 138" in Column 6 lines 24-26 part number 138 in FIG. 1 of Yamashita) to receive the board-to-board terminals (see e.g. "solder bumps" in Column 6 line 31 and part numbers 136a and 136b in FIG. 1 of Yamashita).
Yamashita further teaches that printed circuit boards of this type improve the production rate of good quality products and thus reduce manufacturing problems (see e.g. Column 7 lines 9-22 of Yamashita). Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the first and second printed circuit board of Park et al. in view of Varipatis et al. such that the first printed circuit board includes terminal holes to receive the board-to-board terminals and the second printed circuit board includes terminal holes to receive the board-to-board terminals as taught by Yamashita et al. in order to improve the production rate of good quality products and reduce manufacturing problems as suggested by Yamashita.
Regarding Claim 4, Park in view of Varipatis and further in view of Yamashita disclose the battery pack of claim 3 (see e.g. claim 3 rejection above).
Park in view of Varipatis does not explicitly disclose that the first printed circuit board terminal holes are electrically coupled to components mounted on the first printed circuit board and the second printed circuit board terminal holes are electrically coupled to components mounted on the second printed circuit board.
Yamashita, however, discloses that the first printed circuit board terminal holes are electrically coupled to components mounted on the first printed circuit board and the second printed circuit board terminal holes are electrically coupled to components mounted on the second printed circuit board (see e.g. "Each of the double- face PWB 110, 112 has a through-hole 138 at a predetermined position, the inner surface of the through hole 138 being plated. The through-hole 138 electrically connects front and rear conductive layers 124, 128 or 130, 126 together" in Column 6 lines 24-28 and FIG. 1 of Yamashita; the through-holes are electrically coupled to the conductive layers on the first and second PCBs respectively).
Yamashita further teaches that printed circuit boards of this type improve the production rate of good quality products and thus reduce manufacturing problems (see e.g. Column 7 lines 9-22 of Yamashita). Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the first and second printed circuit board of Park et al. in view of Varipatis et al. such that the first printed circuit board terminal holes are electrically coupled to components mounted on the first printed circuit board and the second printed circuit board terminal holes are electrically coupled to components mounted on the second printed circuit board as taught by Yamashita et al. in order to improve the production rate of good quality products and reduce manufacturing problems as suggested by Yamashita.
Regarding Claim 5, Park in view of Varipatis disclose the battery pack of claim 16 (see e.g. claim 16 rejection above).
Park further discloses that the board-to-bard terminals are a conductive material (see e.g. "conductive terminals" in paragraph [0005]).
Park in view of Varipatis, however, are silent as to the material of the conductive terminals and thus does not disclose that the board-to-board terminals comprise a conductive metal material.
Yamashita, however, discloses board-to-board terminals (see e.g. "solder bumps" in Column 6 lines 56-60 and part numbers 136a and 136b in FIG. 1 of Yamashita). comprising a conductive metal material (see e.g. "the solder bump containing 2% of silver, 62% of tin and 36% of lead" in Column 9 lines 17-19 of Yamashita; silver, tine and lead are all conductive metal materials).
Yamashita further teaches that printed circuit boards of this type improve the production rate of good quality products and thus reduce manufacturing problems (see e.g. Column 7 lines 9-22 of Yamashita). Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the conductive board-to-board terminals of Park et al. in view of Varipatis et al. such that the board-to-board terminals comprises a conductive metal material as taught by Yamashita et al. in order to improve the production rate of good quality products and reduce manufacturing problems as suggested by Yamashita.
Regarding Claim 7, Park in view of Varipatis disclose the battery pack of claim 16 (see e.g. claim 16 rejection above).
Park in view of Varipatis is silent as to the what material the PCB spacer is made of and thus does not disclose that the PCB spacer comprises a plastic material.
Yamashita, however, discloses a PCB spacer (see e.g. "unitary insulating" in Column 6 lines 66-67 and part number 144 in FIG. 2 of Yamashita) comprising a polymer resin (see e.g. "polymer resin" in Column 6 lines 33-38 of Yamashita; a polymer resin is a plastic material).
Yamashita further teaches that printed circuit boards of this type improve the production rate of good quality products and thus reduce manufacturing problems (see e.g. Column 7 lines 9-22 of Yamashita). Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify PCB spacer material of Park et al. in view of Varipatis et al. such that the PCB spacer comprises a plastic material as taught by Yamashita et al. in order to improve the production rate of good quality products and reduce manufacturing problems as suggested by Yamashita.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US-20210144856-A1) in view of Varipatis et al. (US-20170365826-A1) as applied to claim 16 above, and further in view of DeKeuster et al. (US-20220037734-A1).
Regarding Claim 9, Park in view of Varipatis disclose the battery pack of claim 16 (see e.g. claim 16 rejection above).
Park in view of Varipatis does not disclose that the spacer housing includes at least one clip extending from the first side of the spacer housing and the clip clips onto the first printed circuit board to couple and hold the spacer housing on the first printed circuit board.
DeKeuster, however, in the same field of endeavor, discloses a spacer housing (see e.g. "housing" in paragraph [0042] and part number 30 in FIG. 4 of DeKeuster) that includes at least one clip extending from the first side of the spacer housing (see e.g. "clip" in paragraph [0042] and part number 44 in FIG. 4 of DeKeuster) and the clip clips onto the first printed circuit board to couple and hold the spacer housing on the first printed circuit board (see e.g. "The clips 44 secure the PCB 34 to the support member 32 to secure the PCB 34 within the housing 30" in paragraph [0042] and FIG. 9A of DeKeuster).
DeKeuster further teaches that the clips are more robust to tolerance stacks and part variation associated with the PCB which allows the PCB to slightly move during expansion which dampens loading and provides flexibility increasing lifespan of the housing (see e.g. paragraph [0043] of DeKeuster). Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the PCB housing of Park et al. in view of Varipatis et al. such that the PCB spacer housing includes at least one clip extending from the first side of the spacer housing and the clip clips onto the first printed circuit board to couple and hold the spacer housing on the first printed circuit board as taught by DeKeuster et al. in order to have a more flexible housing as suggested by DeKeuster.
Claims 10-12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US-20210144856-A1) in view of Varipatis et al. (US-20170365826-A1) as applied to claim 16 above, and further in view of Counts et al. (US-20200350635-A1).
Regarding Claim 10, Park in view of Varipatis disclose the battery pack of claim 16 (see e.g. claim 16 rejection above).
Park in view of Varipatis does not disclose that the battery pack further comprises a first battery strap, the first battery strap electrically and mechanically coupled to the first PCB.
Counts, however, in the same field of endeavor, battery packs with multiple PCBs, discloses a battery pack (see e.g. "battery pack" in paragraph [0005] and FIG. 1 of Counts) comprising a first battery strap (see e.g. " battery cell straps 322" in paragraph [0006] and part number 322 and 324 in FIG. 4 of Counts), the first battery strap electrically and mechanically coupled to the first PCB (see e.g. "the battery cell straps 322 and 324 to be soldered—or otherwise connected—to the PCB 329" in paragraph [0007] of Counts; soldering would be a method of ethically and mechanically connecting the straps to the PCB).
Counts further teaches that a battery pack of this type reduces material costs and assembly time (see e.g. paragraph [0011] of Counts). Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the battery pack of Park et al. in view of Varipatis et al. such that the battery pack further comprises a first battery strap, the first battery strap electrically and mechanically coupled to the first printed circuit board as taught by Counts et al. in order to reduce materials costs and assembly time as suggested by Counts.
Regarding Claim 11, Park in view of Varipatis and further in view of Counts discloses the battery pack of claim 10 (see e.g. claim 10 rejection above).
Park in view of Varipatis does not disclose that the first battery strap includes an end that is received in a first battery strap hole in the first PCB.
Counts, however, discloses that the first battery strap includes an end that is received in a first battery strap hole in the first PCB (see e.g. "The PCB ends of the battery cell straps are received in the corresponding, associated battery strap through hole/cutout of the PCB and the through hole of the corresponding, associated strap contact." in paragraph [0081] and FIGs. 24-26 of Counts).
Counts further teaches that a battery pack of this type reduces material costs and assembly time (see e.g. paragraph [0011] of Counts). Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the battery pack of Park et al. in view of Varipatis et al. such that the first battery strap includes an end that is received in a first battery strap hole in the first printed circuit board as taught by Counts et al. in order to reduce materials costs and assembly time as suggested by Counts.
Regarding Claim 12, Park in view of Varipatis and further in view of Counts discloses the battery pack of claim 11 (see e.g. claim 11 rejection above).
Park in view of Varipatis does not disclose that the first battery strap hole is electrically coupled to components mounted on the first printed circuit board.
Counts, however, discloses that the first battery strap hole is electrically coupled to components mounted on the first printed circuit board (see e.g. "the strap contact through holes of each pair of strap contact through holes is connected with a PCB trace that connects the strap contact through hole to a mounted component 869." in paragraph [0073] and FIG. 10 of Counts).
Counts further teaches that a battery pack of this type reduces material costs and assembly time (see e.g. paragraph [0011] of Counts). Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the battery pack of Park et al. in view of Varipatis et al. such that the first battery strap hole is electrically coupled to components mounted on the first printed circuit board as taught by Counts et al. in order to reduce materials costs and assembly time as suggested by Counts.
Regarding Claim 14, Park in view of Varipatis and further in view of Counts discloses the battery pack of claim 10 (see e.g. claim 10 rejection above).
Park in view of Varipatis does not disclose that the first battery strap is electrically coupled to a contact pad that is electrically connected to a most negative terminal of the set of battery cells.
Counts, however, discloses that the first battery strap is electrically coupled to a contact pad (see e.g. "Each battery cell strap includes a cell end 637 and a PCB end 639" in paragraph [0079] and part numbers 624 and 637 of FIG. 18 of Counts; the cell end is the contact pad which is in direct (electrical) contact with the battery strap) that is electrically connected to a most negative terminal of the set of battery cells (see e.g. "the cell end 637 of the negative power battery cell strap is connected to the negative terminal of the most negative battery cell in the string of battery cells." in paragraph [0079] of Counts).
Counts further teaches that a battery pack of this type reduces material costs and assembly time (see e.g. paragraph [0011] of Counts). Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the battery pack of Park et al. in view of Varipatis et al. such that the first battery strap is electrically coupled to a contact pad that is electrically connected to a most negative terminal of the set of battery cells as taught by Counts et al. in order to reduce materials costs and assembly time as suggested by Counts.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US-20210144856-A1) in view of Varipatis et al. (US-20170365826-A1) as applied to claim 17 above, and further in view of Cheng (US-20110269319-A1).
Regarding Claim 18, Park in view of Varipatis disclose the battery pack of claim 17 (see e.g. claim 17 rejection above).
Pak in view of Varipatis does not disclose that the first printed circuit board includes a threaded surface mounted nut and the hold-down screw is received by and screwed into the nut.
Cheng, however, in the same field of endeavor, printed circuit board modules, discloses a printed circuit board (see e.g. "first rigid PCB" in paragraph [0014] and part number 11 in FIG. 5 of Cheng) that includes a threaded surface mounted nut (see e.g. "nuts" in paragraph [0025] and part number 162 in FIG. 5 of Cheng) and the hold-down screw is received by and screwed into the nut (see e.g. "bolts" in paragraph [0025] and part number 161 in FIG. 5 of Cheng).
Cheng further teaches that in typical PCB manufacturing a welding processes is needed to mechanically connect a connector to the PCBs, however, at high temperature the welding may damage the PCBs and thus the method of using bolts and nuts is an alternative method that does not damage the PCBs (see e.g. paragraphs [0004]-[0005] of Cheng). Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the first printed circuit board of Park et al. in view of Varipatis et al. such that the first printed circuit board includes a threaded surface mounted nut and the hold-down screw is received by and screwed into the nut as taught by Cheng in order to not damage the PCB as suggested by Cheng.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE EFYMOW whose telephone number is (571)270-0795. The examiner can normally be reached Monday - Thursday 10:30 am - 8:30 pm EST.
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/J.J.E./Examiner, Art Unit 1723
/NICHOLAS P D'ANIELLO/Primary Examiner, Art Unit 1723
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