DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/20/2026 has been entered.
Response to Amendment
The office action is responding to the amendments filed on 01/20/2026. Claims 1, 11 and 19 have been amended. Claim 2 was previously cancelled.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4, 7-9, 11-12 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pope [US 2022/0376703 A1] in view of Basavaraj et al. [CN-112445526-A] in further view of SOLOVEYCHIK et al. [US 2024/0134930 A1] and yet in further view of Vasudevan et al. [US 2019/0004958 A1].
Claim 1 is rejected over Pope, Basavaraj, SOLOVEYCHIK and Vasudevan.
Pope teaches “A memory processing unit (MPU) comprising: a first memory including a plurality of memory regions, wherein one or more of the plurality of memory regions are configured in corresponding pluralities of memory blocks, and” as “One aspect of the disclosure is directed to a system, the system including: one or more memory devices including a first memory device; one or more processors including a first processor, wherein the one or more processors are coupled to the one or more memory devices;” [¶0005]
“and a plurality of processing regions interleaved between the plurality of regions of the first memory, wherein the plurality of processing regions is configured to compute vector or matrix functions, and wherein the processing regions include a plurality of core groups, wherein the core groups include one or more compute cores,” as “the device can implement an interleaver as described with reference to FIG. 4 for combining individual outputs from the entropy coders to pass as outgoing data from the device, for example to a processor or a memory device.” [¶0098] and “The processor 140 performs one or more operations related to executing the neural network, for example matrix multiplication or computing the output to an activation function, and returns the uncompressed data 202B to the memory device 130.” [¶0063]
Pope does not explicitly teach wherein the memory blocks are configured to store Group Brain Floating Point (B-float) encoded data,
wherein each Group B-float encoded entry comprises a plurality of pixels encoded with a shared exponent;
wherein the compute cores in corresponding core groups of the plurality of processing regions are configurable for core-to-core dataflow between adjacent compute groups in respective ones of the plurality of processing regions.
However, Basavaraj teaches “wherein the memory blocks are configured to store Group Brain Floating Point (B-float) encoded data,” as “each of the logic blocks (A-I) of the matrix operand 210 is sequentially stored in a block of the fixed size of the memory 220. In the illustrated embodiment, for example, the size of each memory block is 2kB, and includes 32 rows of memory 220 with a width of 512 bits (or 64 bytes), which means that each row has the capability of storing up to 32 elements of the BFLOAT16 type. ” [Spec]
Pope and Basavaraj are analogous arts because they teach memory control and storage system access.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Pope and Basavaraj before him/her, to modify the teachings of Pope to include the teachings of Basavaraj with the motivation of the non-temporary data is not too likely to be heavily used to benefit from the cache in the first-level cache, and should be prioritized. [Basavaraj, Spec]
The combination of Pope and Basavaraj does not explicitly teach wherein each Group B-float encoded entry comprises a plurality of pixels encoded with a shared exponent;
wherein the compute cores in corresponding core groups of the plurality of processing regions are configurable for core-to-core dataflow between adjacent compute groups in respective ones of the plurality of processing regions.
However, SOLOVEYCHIK teaches “wherein each Group B-float encoded entry comprises a plurality of pixels encoded with a shared exponent;” as “With block floating point, an exponent is shared across a set of mantissa significant values (see diagonally line filled blocks of the int8 vectors at the bottom of FIG. 5B),” [¶0060]
Pope, Basavaraj and SOLOVEYCHIK are analogous arts because they teach memory control and storage system access.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Pope, Basavaraj and SOLOVEYCHIK before him/her, to modify the teachings of combination of Pope and Basavaraj to include the teachings of SOLOVEYCHIK with the motivation of present method and apparatus enables the storage of a large number of matrix elements in a compressed format that can be decompressed upon retrieval for matrix computations. [SOLOVEYCHIK, ¶0012]
The combination of Pope, Basavaraj and SOLOVEYCHIK does not explicitly teach wherein the compute cores in corresponding core groups of the plurality of processing regions are configurable for core-to-core dataflow between adjacent compute groups in respective ones of the plurality of processing regions.
However, Vasudevan teaches “wherein the compute cores in corresponding core groups of the plurality of processing regions are configurable for core-to-core dataflow between adjacent compute groups in respective ones of the plurality of processing regions.” as [Fig. 1, elements 112 and 114] (Fig. 1 shows core to core data flow between adjacent processing units, 120-1 and 120-2.)
Pope, Basavaraj, SOLOVEYCHIK and Vasudevan are analogous arts because they teach memory control and storage system access.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Pope, Basavaraj, SOLOVEYCHIK and Vasudevan before him/her, to modify the teachings of combination of Pope, Basavaraj and SOLOVEYCHIK to include the teachings of Vasudevan with the motivation of high speed I/O interfaces where the data is consumed/produced by the CPU from/to I/O, data flow architectures that use core to core communications to implement messaging/pipelining. [Vasudevan, ¶0031]
Claim 3 is rejected over Pope, Basavaraj, SOLOVEYCHIK and Vasudevan.
Pope does not explicitly teach wherein the Group B-float encoded data comprises Group B-float encoded feature map pixels values.
However, Basavaraj teaches “wherein the Group B-float encoded data comprises Group B-float encoded feature map pixels values.” as “ The operation size = 36 (for example, the total number of read operations = the number of pixels per row * row number (3 * 12 = 36));” [Spec]
Claim 4 is rejected over Pope, Basavaraj, SOLOVEYCHIK and Vasudevan.
Pope does not explicitly teach wherein the plurality of memory blocks of each of the plurality of regions of the first memory are arranged in a plurality of columns and rows.
However, Basavaraj teaches “wherein the plurality of memory blocks of each of the plurality of regions of the first memory are arranged in a plurality of columns and rows.” as “ the REGOP-MV instruction may include various fields capable of extracting matrix operand from the memory,” [Spec]
Claim 7 is rejected over Pope, Basavaraj, SOLOVEYCHIK and Vasudevan.
Pope teaches “wherein one or more of the plurality of core groups of a respective one of the plurality of processing regions are coupled between adjacent ones of the plurality of memory regions of the first memory, and between adjacent core groups of the respective one of the plurality of processing regions.” as [Fig. 4] (Fig. 4 shows plurality of entropy coders, which are essentially processors [Ref ¶0042 (An entropy coder can include a multiplier circuit and a look-up table for storing an entropy code table corresponding to an entropy encoding. The compressor and decompressor devices of the system can distribute incoming data to multiple entropy coders, process the data using the entropy encoding, and combine the individual outputs of the entropy coders to generate the final output corresponding to the incoming data.) The entropy coders are adjacent to plurality of memory buffers.)
Claim 8 is rejected over Pope, Basavaraj, SOLOVEYCHIK and Vasudevan.
Pope teaches “wherein the plurality of core groups of respective ones of the plurality of processing regions is coupled between adjacent ones of the plurality of memory regions of the first memory.” as [Fig. 4] (Fig. 4 shows plurality of entropy coders (i.e. processing cores) along with processing regions (element 450) adjacent to memory regions (element 460))
Claim 9 is rejected over Pope, Basavaraj, SOLOVEYCHIK and Vasudevan.
Pope does not explicitly teach wherein compute cores of respective ones of the core groups are configured in one or more compute clusters, wherein compute cores in a given compute cluster are configured to compute a given compute function.
However, Basavaraj teaches “wherein compute cores of respective ones of the core groups are configured in one or more compute clusters, wherein compute cores in a given compute cluster are configured to compute a given compute function.” as “ The retirement unit 1154 and the (one or more) physical register file units 1158 are coupled to (one or more) execution clusters 1160. (one or more) execution cluster 1160 comprises a group of one or more execution units 1162 and a group of one or more memory access unit 1164.” [Spec]
Claim 11 is rejected over Pope, Basavaraj, SOLOVEYCHIK and Vasudevan under the same rationale of rejection of claim 1.
Claim 12 is rejected over Pope, Basavaraj, SOLOVEYCHIK and Vasudevan under the same rationale of rejection of claim 4.
Claim 18 is rejected over Pope, Basavaraj, SOLOVEYCHIK and Vasudevan.
Pope teaches “wherein: the first memory comprises a static volatile memory; and the second memory comprises a non-volatile memory.” as “The storage device(s) 1130 can be a combination of volatile and non-volatile memory,” [¶0123]
Claim(s) 5-6, 13 and 19-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pope [US 2022/0376703 A1] in view of Basavaraj et al. [CN-112445526-A], in further view of SOLOVEYCHIK et al. [US 2024/0134930 A1], in further view of Vasudevan et al. [US 2019/0004958 A1] and yet in further view of Langhammer et al. [US 2019/0155574].
Claim 5 is rejected over Pope, Basavaraj, SOLOVEYCHIK, Vasudevan and Langhammer.
The combination of Pope, Basavaraj, SOLOVEYCHIK and Vasudevan does not explicitly teach wherein a plurality of bases and an instance of a given exponent for a corresponding group of channels of the Group B-float encoded data are stored in a corresponding row of memory blocks of a corresponding region of the first memory.
However, Langhammer teaches “wherein a plurality of bases and an instance of a given exponent for a corresponding group of channels of the Group B-float encoded data are stored in a corresponding row of memory blocks of a corresponding region of the first memory.” as “Carry propagate adder 214 may include additional circuitry to support rounding and floating point exceptions for the floating-point multiplier. Additional circuitry may be provided to implement the floating-point multiplier exponent calculation.” [¶0044]
Pope, Basavaraj, SOLOVEYCHIK, Vasudevan and Langhammer are analogous arts because they teach memory control and storage system access.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Pope, Basavaraj, SOLOVEYCHIK, Vasudevan and Langhammer before him/her, to modify the teachings of combination of Pope, Basavaraj, SOLOVEYCHIK and Vasudevan to include the teachings of Langhammer with the motivation of it would be advantageous to provide a DSP Block that is backwards compatible with general purpose applications, while at the same time being able to be configured to support smaller machine learning applications. [Langhammer, ¶0032]
Claim 6 is rejected over Pope, Basavaraj, SOLOVEYCHIK, Vasudevan and Langhammer.
The combination of Pope, Basavaraj, SOLOVEYCHIK and Vasudevan does not explicitly teach wherein the exponent for corresponding groups of channels of the Group B-float encoded data are dynamic.
However, Langhammer teaches “wherein the exponent for corresponding groups of channels of the Group B-float encoded data are dynamic.” as “Both FP16 and BFLOAT16 numbers are 16 bits and therefore have the same size and memory footprint. BfLOAT16, however, trades off mantissa precision for exponent width (i.e., relative to FP16, BFLOAT16 exhibits reduced accuracy but increased dynamic range).” [¶0077]
Claim 13 is rejected over Pope, Basavaraj, SOLOVEYCHIK, Vasudevan and Langhammer under the same rationale of rejection of claim 5.
Claim 19 is rejected over Pope, Basavaraj, SOLOVEYCHIK, Vasudevan and Langhammer.
Pope teaches “A memory processing method comprising: configuring a first memory to store Group B-float encoded data,” as “The system as described herein can be configured to generate an entropy encoding based on generating a probability distribution of codewords in input data to the system.” [¶0037]
“wherein the first memory includes a plurality of regions;” as “Each entropy coder 401A-N can include a respective buffer 460A-N. The buffer can be any type of memory implemented as part of hardware implementing an entropy coder.” [¶0070]
“configuring data flow between compute cores of one or more of a plurality of processing regions and corresponding adjacent ones of the plurality of regions of the first memory, wherein the plurality of processing regions are interleaved between the plurality of regions of the first memory; configuring data flow between a second memory and the compute cores of the one or more of the plurality of processing regions; configuring data flow between compute cores within respective ones of the one or more of the plurality of processing regions,” as “The interleaver 404 can be configured to combine the individual outputs 407A-N and pass the combined output as outgoing data 405. The outgoing data 405 can be passed to, for example, a memory device or a processor, depending on whether the device 400 is a compressor device or a decompressor device.” [¶0078]
Pope does not explicitly teach wherein each Group B- float encoded entry comprises a plurality of pixels encoded with a shared exponent, and
wherein the compute cores are arranged in corresponding core groups within the respective processing regions, and wherein compute cores in corresponding core groups are configurable for core-to-core dataflow between adjacent compute groups in respective ones of the plurality of processing regions;
configuring one or more sets of compute cores of one or more of the plurality of processing regions to perform respective compute functions of a neural network model;
loading weights for the neural network model into the second memory;
loading activation data for the neural network model into one or more of the plurality of regions of the first memory; and
synchronizing data movement between one or more compute cores producing given data and one or more other compute cores consuming the given data based on the neural network model.
However, Basavaraj teaches “configuring one or more sets of compute cores of one or more of the plurality of processing regions to perform respective compute functions of a neural network model;” as “The memory layout of these matrix operands is very important to the overall performance of the neural network.” [Spec]
“loading activation data for the neural network model into one or more of the plurality of regions of the first memory; and” as “In order to perform some neural network operation, the dimension of the matrix operand may need to be rearranged (shuffled) or re-ordering, or some portion of the matrix operand may need to be extracted, slice (slice), trimming and/or reordering.” [Spec]
“synchronizing data movement between one or more compute cores producing given data and one or more other compute cores consuming the given data based on the neural network model.” as “ For example, in some cases, the matrix processor 110 may be used to represent the host computing device 120 training artificial neural network and/or performing inference, which generally needs to use complex matrix arithmetic (e.g., many large multi-dimensional matrix operand matrix multiplication and convolution) to perform a plurality of computing intensive operation .” [Spec]
Pope and Basavaraj are analogous arts because they teach memory control and storage system access.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Pope and Basavaraj before him/her, to modify the teachings of Pope to include the teachings of Basavaraj with the motivation of the non-temporary data is not too likely to be heavily used to benefit from the cache in the first-level cache, and should be prioritized. [Basavaraj, Spec]
The combination of Pope and Basavaraj does not explicitly teach wherein each Group B- float encoded entry comprises a plurality of pixels encoded with a shared exponent, and
wherein the compute cores are arranged in corresponding core groups within the respective processing regions, and wherein compute cores in corresponding core groups are configurable for core-to-core dataflow between adjacent compute groups in respective ones of the plurality of processing regions;
loading weights for the neural network model into the second memory;
However, SOLOVEYCHIK teaches “wherein each Group B- float encoded entry comprises a plurality of pixels encoded with a shared exponent, and” as “With block floating point, an exponent is shared across a set of mantissa significant values (see diagonally line filled blocks of the int8 vectors at the bottom of FIG. 5B),” [¶0060]
Pope, Basavaraj and SOLOVEYCHIK are analogous arts because they teach memory control and storage system access.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Pope, Basavaraj and SOLOVEYCHIK before him/her, to modify the teachings of combination of Pope and Basavaraj to include the teachings of SOLOVEYCHIK with the motivation of present method and apparatus enables the storage of a large number of matrix elements in a compressed format that can be decompressed upon retrieval for matrix computations. [SOLOVEYCHIK, ¶0012]
The combination of Pope, Basavaraj and SOLOVEYCHIK does not explicitly teach wherein the compute cores are arranged in corresponding core groups within the respective processing regions, and wherein compute cores in corresponding core groups are configurable for core-to-core dataflow between adjacent compute groups in respective ones of the plurality of processing regions;
loading weights for the neural network model into the second memory;
However, Vasudevan teaches “wherein the compute cores are arranged in corresponding core groups within the respective processing regions, and wherein compute cores in corresponding core groups are configurable for core-to-core dataflow between adjacent compute groups in respective ones of the plurality of processing regions;” as [Fig. 1, elements 112 and 114] (Fig. 1 shows core to core data flow between adjacent processing units, 120-1 and 120-2. They are is the same processor 110.)
Pope, Basavaraj, SOLOVEYCHIK and Vasudevan are analogous arts because they teach memory control and storage system access.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Pope, Basavaraj, SOLOVEYCHIK and Vasudevan before him/her, to modify the teachings of combination of Pope, Basavaraj and SOLOVEYCHIK to include the teachings of Vasudevan with the motivation of high speed I/O interfaces where the data is consumed/produced by the CPU from/to I/O, data flow architectures that use core to core communications to implement messaging/pipelining. [Vasudevan, ¶0031]
The combination of Pope, Basavaraj, SOLOVEYCHIK and Vasudevan does not explicitly teach loading weights for the neural network model into the second memory;
However, Langhammer teaches “loading weights for the neural network model into the second memory;” as “Training determines the weights or coefficients by analyzing data (e.g., image data), whereas inference applies them. Training may use floating-point calculations, while inferencing may use fixed-point integer calculations.” [¶0032]
Pope, Basavaraj, SOLOVEYCHIK, Vasudevan and Langhammer are analogous arts because they teach memory control and storage system access.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Pope, Basavaraj, SOLOVEYCHIK, Vasudevan and Langhammer before him/her, to modify the teachings of combination of Pope, Basavaraj, SOLOVEYCHIK and Vasudevan to include the teachings of Langhammer with the motivation of it would be advantageous to provide a DSP Block that is backwards compatible with general purpose applications, while at the same time being able to be configured to support smaller machine learning applications. [Langhammer, ¶0032]
Claim 20 is rejected over Pope, Basavaraj, SOLOVEYCHIK, Vasudevan and Langhammer.
Pope does not explicitly teach wherein the plurality of regions of the first memory each include a plurality of memory blocks arranged in a plurality of columns and rows.
However, Basavaraj teaches “wherein the plurality of regions of the first memory each include a plurality of memory blocks arranged in a plurality of columns and rows.” as “the REGOP-MV instruction may include various fields capable of extracting matrix operand from the memory,” [Spec]
Claim 21 is rejected over Pope, Basavaraj, SOLOVEYCHIK, Vasudevan and Langhammer.
The combination of Pope, Basavaraj, SOLOVEYCHIK and Vasudevan does not explicitly teach further comprising configuring the first memory to store a plurality of bases and an instance of a given exponent for a corresponding group of channels of the Group B-float encoded data in a corresponding row of memory blocks of a corresponding region of the first memory.
However, Langhammer teaches “further comprising configuring the first memory to store a plurality of bases and an instance of a given exponent for a corresponding group of channels of the Group B-float encoded data in a corresponding row of memory blocks of a corresponding region of the first memory.” as “Carry propagate adder 214 may include additional circuitry to support rounding and floating point exceptions for the floating-point multiplier. Additional circuitry may be provided to implement the floating-point multiplier exponent calculation.” [¶0044]
Claim 22 is rejected over Pope, Basavaraj, SOLOVEYCHIK, Vasudevan and Langhammer.
The combination of Pope, Basavaraj, SOLOVEYCHIK and Vasudevan does not explicitly teach wherein the exponent for corresponding groups of channels of the Group B-float encoded data are dynamic.
However, Langhammer teaches “wherein the exponent for corresponding groups of channels of the Group B-float encoded data are dynamic.” as “Both FP16 and BFLOAT16 numbers are 16 bits and therefore have the same size and memory footprint. BfLOAT16, however, trades off mantissa precision for exponent width (i.e., relative to FP16, BFLOAT16 exhibits reduced accuracy but increased dynamic range).” [¶0077]
Claim(s) 10, 14 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pope [US 2022/0376703 A1] in view of Basavaraj et al. [CN-112445526-A] in further view of SOLOVEYCHIK et al. [US 2024/0134930 A1], in further view of Vasudevan et al. [US 2019/0004958 A1] and yet in further view of Chen et al. [CN-116893912-A].
Claim 10 is rejected over Pope, Basavaraj, SOLOVEYCHIK, Vasudevan and Chen.
The combination of Pope, Basavaraj, SOLOVEYCHIK and Vasudevan does not explicitly teach wherein one or more compute groups include one or more memory M-cores and one or more arithmetic A-Cores.
However, Chen teaches “wherein one or more compute groups include one or more memory M-cores and one or more arithmetic A-Cores.” as “When the M-core sends data to the A-core, the program running period of the A-core is uncontrollable, which may lead to the problem of data misuse.” [Spec]
Pope, Basavaraj, SOLOVEYCHIK, Vasudevan and Chen are analogous arts because they teach memory control and storage system access.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Pope, Basavaraj, SOLOVEYCHIK, Vasudevan and Chen before him/her, to modify the teachings of combination of Pope, Basavaraj, SOLOVEYCHIK and Vasudevan to include the teachings of Chen with the motivation of compared with performing packet storage processing on all the result data, It can effectively reduce the data storage pressure of the target process corresponding to the data storage space. [Chen, Spec]
Claim 14 is rejected over Pope, Basavaraj, SOLOVEYCHIK, Vasudevan and Chen.
Pope teaches “further comprising one or more memory regions of a second memory coupled to the plurality of processing regions.” as [Fig. 4] (Fig 4 shows memory buffer elements 460 are coupled to the Multiplication circuits 450)
Claim 16 is rejected over Pope, Basavaraj, SOLOVEYCHIK, Vasudevan and Chen.
Pope teaches “wherein respective ones of the second memory regions are coupled to respective ones of the plurality of processing regions.” as [Fig. 4] (Fig 4 shows memory buffer elements 460 are coupled to the Multiplication circuits 450. The buffers can be non-volatile memories.)
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pope [US 2022/0376703 A1] in view of Basavaraj et al. [CN-112445526-A] in further view of SOLOVEYCHIK et al. [US 2024/0134930 A1] in further view of Vasudevan et al. [US 2019/0004958 A1] in further view of Chen et al. [CN-116893912-A] and yet in further view of Langhammer et al. [US 2019/0155574].
Claim 15 is rejected over Pope, Basavaraj, SOLOVEYCHIK, Vasudevan, Chen and Langhammer.
The combination of Pope, Basavaraj, SOLOVEYCHIK, Vasudevan and Chen does not explicitly teach wherein the second memory is configured to store weight values.
However, Langhammer teaches “wherein the second memory is configured to store weight values.” as “Training determines the weights or coefficients by analyzing data (e.g., image data), whereas inference applies them. Training may use floating-point calculations, while inferencing may use fixed-point integer calculations.” [¶0032]
Pope, Basavaraj, SOLOVEYCHIK, Vasudevan, Chen and Langhammer are analogous arts because they teach memory control and storage system access.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Pope, Basavaraj, SOLOVEYCHIK, Vasudevan, Chen and Langhammer before him/her, to modify the teachings of combination of Pope, Basavaraj, SOLOVEYCHIK, Vasudevan and Chen to include the teachings of Langhammer with the motivation of it would be advantageous to provide a DSP Block that is backwards compatible with general purpose applications, while at the same time being able to be configured to support smaller machine learning applications. [Langhammer, ¶0032]
Allowable Subject Matter
Claim 17 and 23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to amended claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/MASUD K KHAN/Primary Examiner, Art Unit 2132
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