DETAILED ACTION
This office action is in response to the amendment filed on 07/08/2026.
Claims 1-7 are cancelled.
Claims 8 – 23 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-23 are rejected under 35 U.S.C. 103 as being unpatentable over PILLILLI (US 20210224061 A1) and in view of Krishnamurthy (US 20140130151).
Regarding claim 8, PILLILLI discloses a semiconductor chip package [Fig. 4], comprising:
a plurality of processing cores [processor cores 410];
an accelerator to include circuitry configured to offload at least one task from
the plurality of processing cores after boot-up of the plurality of processing cores and
the accelerator [0048: Accelerators 442 can be a programmable or fixed function offload engine that can be accessed or used by a processor 410. For example, an accelerator among accelerators 442 can provide sequential and speculative decoding operations in a manner described herein, compression (DC) capability, cryptography services such as public key encryption (PKE), cipher, hash/authentication capabilities, decryption, or other capabilities or services],
the circuitry of the accelerator also configured to authenticate firmware having a version identifier [0010: A security controller of a device (e.g., CPU, GPU, network interface, accelerator, xPU) can fetch the firmware image from the staging buffer, authenticate the firmware image][0045: This may trigger flows where the security version number (SVN), Revision ID (REVID) etc. of the upgraded image, specific capability vectors are read that may be used as information to run other flows]; and
security circuitry [device root of trust (DROT)] configured to prevent loading of the firmware of an earlier version than a second version that was previously stored for the firmware in a secure non volatile memory [0045: the DROT can perform anti-rollback checks to prevent downgrading of the device to an older version of its software].
However, PILLILLI does not explicitly disclose security circuitry configured to prevent loading of the firmware having the version identifier if the version identifier is an earlier version than a second version identifier that was previously stored for the firmware in a secure non volatile memory.
Krishnamurthy discloses security circuitry configured to prevent loading of the firmware having the version identifier if the version identifier is an earlier version than a second version identifier that was previously stored for the firmware in a secure non volatile memory [0011: obtaining a lowest acceptable firmware version number (LAFVN), wherein the LAFVN is stored in a secure element environment, wherein the secure element environment utilizes memory separated from the substrate; and comparing the FVN and the LAFVN, wherein if the FVN is less than the LAFVN, then disallowing the first firmware installation][0012-0014] [0073: The NFCC 145, in order to prevent a rollback of the firmware to an older version, can retrieve the LAFVN from the secure element environment and compare the FVN with the LAFVN. If the comparison indicates that the FVN is less than LAFVN, then the NFCC disallows this firmware installation because it may be a rollback to an older firmware version] [Fig. 3].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of PILLILLI and Krishnamurthy because they both directed to prevent loading the old firmware. Krishnamurthy’s disclosing of securely and persistently storing an acceptable firmware-version identifier and comparing subsequently presented firmware against that identifier would allow PILLILLI to prevent the old firmware from being deployed when its identifiers indicate a version older than the securely stored acceptable version.
Regarding claim 9, PILLILLI discloses semiconductor chip package of claim 8 wherein the circuitry of the accelerator is to decrypt an encrypted hash of the firmware and the version identifier to generate the version identifier [0023-0024] [0036-0037].
Regarding claim 10, PILLILLI discloses semiconductor chip package of claim 9 wherein the circuitry of the accelerator is to decrypt the encrypted hash with a public key that is stored on a semiconductor chip [0023-0024] [0036-0037].
Regarding claim 11, Krishnamurthy discloses semiconductor chip package of claim 9 wherein the circuitry of the accelerator is to authenticate the firmware having the version identifier based on a comparison of the decrypted hash with another hash that is calculated from the firmware and the version identifier [0081][0089][0091].
Regarding claim 12, PILLILLI discloses the semiconductor chip package of claim 8 wherein the security circuitry is integrated within a security module that is integrated on a semiconductor chip having the accelerator [0045-0048].
Regarding claim 13, PILLILLI discloses the semiconductor chip package of claim 8 wherein the circuitry of the accelerator is configured to offload encryption/decryption tasks from the plurality of processing cores [0045-0048].
Regarding claim 14, PILLILLI discloses the semiconductor chip package of claim 8 wherein the circuitry of the accelerator is configured to offload compression/decompression tasks from the plurality of processing cores [0045-0048].
Regarding claim 15, PILLILLI discloses the semiconductor chip package of claim 8 wherein the circuitry of the accelerator is configured to chain decryption and decompression tasks [0045-0048].
Regarding claim 16, PILLILLI discloses the semiconductor chip package of claim 8 wherein the plurality of processing cores are part of a general purpose processor or specific purpose processor [0013][0046][0048].
Regarding claim 17, PILLILLI discloses the semiconductor chip package of claim 8 wherein the semiconductor chip package comprises an infrastructure processing unit [0013][0046][0048].
Regarding claims 18 – 23, these claims are rejected for the same reasons as set forth in claims 8,9,16,10-12 respectively, above.
Response to Arguments
Applicant’s arguments filed on 07/08/2026 have been fully considered but are moot in view of new ground(s) of rejection because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Examiner's note: Examiner has cited particular paragraphs and columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner (see MPEP § 2123).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHIL K NGUYEN whose telephone number is (571)270-3356. The examiner can normally be reached 9:30 a.m - 5 p.m.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached at (571)270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PHIL K NGUYEN/Primary Examiner, Art Unit 2176
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