DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
The present application, 18110152, filed 02/15/2023 Claims Priority from Provisional Application 63311787, filed 02/18/2022.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “604-2” has been used to designate both A and B inputs to FA 600 in Fig. 8. Examiner suggest amending the B input as “604-1” consistent with Fig. 6.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description:
102 in Fig. 1
206, 208, 218-2 and 218-3 in Fig. 2
306-1, 306-2, 306-3 and 306-4 in Fig. 3
306-1, 306-2 and 306-3 in Fig. 4
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
Applicant is reminded of the proper content of an abstract of the disclosure.
A patent abstract is a concise statement of the technical disclosure of the patent and should include that which is new in the art to which the invention pertains. The abstract should not refer to purported merits or speculative applications of the invention and should not compare the invention with the prior art.
If the patent is of a basic nature, the entire technical disclosure may be new in the art, and the abstract should be directed to the entire disclosure. If the patent is in the nature of an improvement in an old apparatus, process, product, or composition, the abstract should include the technical disclosure of the improvement. The abstract should also mention by way of example any preferred modifications or alternatives.
Where applicable, the abstract should include the following: (1) if a machine or apparatus, its organization and operation; (2) if an article, its method of making; (3) if a chemical compound, its identity and use; (4) if a mixture, its ingredients; (5) if a process, the steps.
Extensive mechanical and design details of an apparatus should not be included in the abstract. The abstract should be in narrative form and generally limited to a single paragraph within the range of 50 to 150 words in length.
See MPEP § 608.01(b) for guidelines for the preparation of patent abstracts.
The abstract is objected to because it refers to purported merits or speculative applications of the invention and compares the invention with the prior art. Further, the invention is an apparatus (i.e. a digital in-memory computing macro circuit), however, the abstract do not include the organization and operation of the apparatus.
The specification is objected to under 37 C.F.R. 1.74, which requires the detailed description to refer to the different parts of the figures by use of reference letters or reference numerals. Implicit in this rule is that the detailed description correctly reference the figures. In this application the figures and detailed description are inconsistent as explained below.
A. In paragraph [0005] line 13, “the input 120” should read “the input 102” instead
Claim Objections
Claims 4 and 18 are objected to under 37 C.F.R. 1.71(a) which requires “full, clear, concise, and exact terms” as to enable any person skilled in the art or science to which the invention or discovery appertains, or with which it is most nearly connected, to make and use the same. The following should be corrected.
A. In claim 4 line 6, “a single full adder circuits” should read “a single full adder circuit” for better clarity.
B. In claim 18 lines 5-6, “a single full adder circuits” should read “a single full adder circuit” for better clarity.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3-4 and 12-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites “the approximate compressor” in lines 1-2. It is unclear which specific approximate compressor of the plurality of approximate compressors is being referred to. For purposes of examination, this is interpreted as “each approximate compressor” instead. Claim 4 recites a similar limitation in lines 1-2 and is rejected for the same reason.
Claim 4 recites “wherein the approximate compressor is a double approximate compressor that comprises a first plurality of AND and OR logic gates that receive as input respective pairs of bitcell values, a second plurality of AND and OR logic gates that receive outputs of the first plurality of AND and OR logic gates and the single approximate compressor also comprises …”. This limitation is unclear because the first part of the wherein statement recites that the approximate compressor is a double approximate compressor, however, the second part of the wherein statement recites further components of the single approximate compressor. For purposes of examination, the highlighted (bolded and underlined) limitation is interpreted as double consistent with Fig. 4.
Claim 12 recites “the number of series-connected pass-gates” in lines 12-13. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, this is interpreted as “a number of series-connected pass-gates” instead. Claim 17 recites a similar limitation in lines 12-13 and is rejected for the same reason. Claims 13-16 inherit the same deficiency as claim 1 by reason of dependence. Claims 18-20 inherit the same deficiency as claim 17 by reason of dependence.
Claim 13 recites “the single approximate compressor” in lines 1-2 and 3. It is unclear which specific single approximate compressor of the plurality of single approximate compressors is being referred to. For purposes of examination, this is interpreted as “each single approximate compressor” instead. Claim 15 recites a similar limitation in lines 1-2 and is rejected for the same reason.
Claim 18 recites “the double approximate compressor” in lines 1-2 and 5. It is unclear which specific double approximate compressor of the plurality of double approximate compressors is being referred to. For purposes of examination, this is interpreted as “each double approximate compressor” instead. Claim 15 recites a similar limitation in lines 1-2 and is rejected for the same reason.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 8-9, 11-13, 16-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Badaroglu et al. (US 20230047364 A1), hereinafter Badaroglu, in view of Luo et al. (US 20220113939 A1), hereinafter Luo and Ahn (US 6505226 B1).
Regarding claim 1, Badaroglu teaches a digital in-memory computing macro circuit, comprising (Badaroglu Fig. 4 and paragraph [0062]):
a plurality of adders adder adders (Badaroglu Fig. 4 and paragraphs [0065-0066, 0069] plurality of adders – 409/410; plurality of bitcell values – CIM cell output);
an adder tree that receives a plurality of adder adders (Badaroglu Fig. 4 and paragraphs [0066, 0069] adder tree – 412; plurality of sums – outputs of 410; sum – output of 412; plurality of adders – 414); and
a shift accumulator that accumulates the sum and sums of subsequent bitcell multiplication cycles in a pipeline (Badaroglu Fig. 4 and paragraphs [0066, 0069] shift accumulator – 416).
Badaroglu does not explicitly teach a plurality of approximate compressors wherein each approximate compressor of the plurality of approximate compressors receives as an input a plurality of bitcell values of a plurality of bitcell multiplications and generates an output comprising an approximate sum of the plurality of bitcell values; and an adder tree that receives a plurality of approximate sums, the plurality of approximate sums comprising an approximate sum from each approximate compressor of the plurality of approximate compressors and generates a sum corresponding to a total value of the plurality of bitcell multiplications, wherein the adder tree comprises a plurality of ripple carry adders that each comprise a plurality of full adder circuits that use inverters such that a number of series- connected pass-gates in each full adder circuit of the plurality of full adder circuits is less than two.
However, on the same field of endeavor, Luo discloses a plurality of approximate compressors wherein each approximate compressor of the plurality of approximate compressors receives as an input a plurality of bitcell values of a plurality of bitcell multiplications and generates an output comprising an approximate sum of the plurality of bitcell values (Luo Fig. 7C, 8A, 8B, 8F-8H and paragraphs [0050, 0055-0056, 0060-0065] approximate compressors – elements 801, 802 and 806-808 employed in the approximation lanes 724 of the CSA tree structure).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Badaroglu and configure the adder trees 410 in stage 409 as approximate compressors in order to reduce power and area requirements/gate count by replacing the accurate circuitry with approximate circuitry (Luo paragraph [0050]).
Therefore, the combination of Badaroglu as modified in view of Luo teaches a plurality of approximate compressors wherein each approximate compressor of the plurality of approximate compressors receives as an input a plurality of bitcell values of a plurality of bitcell multiplications and generates an output comprising an approximate sum of the plurality of bitcell values; and an adder tree that receives a plurality of approximate sums, the plurality of approximate sums comprising an approximate sum from each approximate compressor of the plurality of approximate compressors and generates a sum corresponding to a total value of the plurality of bitcell multiplications.
Badaroglu does not explicitly teach wherein the adder tree comprises a plurality of ripple carry adders that each comprise a plurality of full adder circuits that use inverters such that a number of series-connected pass-gates in each full adder circuit of the plurality of full adder circuits is less than two.
However, on the same field of endeavor, Ahn discloses a ripple carry adder that comprises a plurality of full adder circuits that use inverters such that a number of series- connected pass-gates in each full adder circuit of the plurality of full adder circuits is less than two (Ahn Figs. 4-6 and col 4 lines 8-50; ripple carry adder – adder in Fig. 4; plurality of full adder circuits – 41-48; inverters – inverters; the full adders in Figs. 5-6 only includes one pass-gate (i.e., PM14/NM14 pair in Fig. 5 and PM24/NM24 pair in Fig. 6).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Badaroglu and configure the adders 414 in stage 412 as ripple carry adders that each comprise a plurality of full adder circuits that use inverters such that a number of series- connected pass-gates in each full adder circuit of the plurality of full adder circuits is less than two in order to increase processing speed compared to conventional ripple type adders by generating a carry output signal by using an inverter and/or to reduce layout surface (Ahn col 6 lines 37-47).
Therefore, the combination of Badaroglu as modified in view of Luo and Ahn teaches a plurality of ripple carry adders that each comprise a plurality of full adder circuits that use inverters such that a number of series- connected pass-gates in each full adder circuit of the plurality of full adder circuits is less than two.
Regarding claim 2, Badaroglu as modified in view of Luo and Ahn teaches all the limitations of claim 1 as stated above. Further, Badaroglu as modified in view of Luo and Ahn teaches wherein each approximate compressor is at least one of a single approximate compressor or a double approximate compressor (Luo Fig. 7C, 8A, 8B, 8F-8H and paragraphs [0055-0056, 0060-0065] the arrangements of elements in 724 (for each bit significance
2
4
to
2
8
) can be interpreted as a single approximate compressor comprising circuits 801-802 and 807/808 as single approximation stage or as a double approximate compressor comprising circuits 801-802 in a first approximation stage and 807/808 in a second approximation stage).
Regarding claim 3, Badaroglu as modified in view of Luo and Ahn teaches all the limitations of claim 2 as stated above. Further, Badaroglu as modified in view of Luo and Ahn teaches wherein the approximate compressor is a single approximate compressor that comprises a plurality of AND and OR logic gates that receive as input respective pairs of bitcell values, and the single approximate compressor also comprises a plurality of full adders circuits that receive outputs of the plurality of AND and OR logic gates (Luo Fig. 7C, 8A, 8B, 8G-8H and paragraphs [0055-0056, 0060-0065] plurality of AND and OR logic gates – 801; plurality of full adders circuits – 807).
Regarding claim 4, Badaroglu as modified in view of Luo and Ahn teaches all the limitations of claim 2 as stated above. Further, Badaroglu as modified in view of Luo and Ahn teaches wherein the approximate compressor is a double approximate compressor that comprises a first plurality of AND and OR logic gates that receive as input respective pairs of bitcell values, a second plurality of AND and OR logic gates that receive outputs of the first plurality of AND and OR logic gates and the single approximate compressor also comprises a single full adder circuits that receive outputs of the second plurality of AND and OR logic gates (Luo Fig. 7C, 8A, 8B, 8G-8H and paragraphs [0055-0056, 0060-0065] first plurality of AND and OR logic gates – 801 in stage 732; second plurality of AND and OR logic gates – 802 and 807/808 in stage 734 in the
2
4
compressor, 807/808 in stage 734 and 736 in the
2
5
to
2
8
compressor; single full adder circuit - 807/808 in stage 736 in the
2
4
compressor; 807/808 in stage 738 in the
2
5
to
2
8
compressor).
Regarding claim 8, Badaroglu as modified in view of Luo and Ahn teaches all the limitations of claim 1 as stated above. Further, Badaroglu as modified in view of Luo and Ahn teaches wherein the ripple carry adders comprise at least one of three, four, five, or six full adder circuits (Badaroglu Fig. 4 shows the first stage of 412 is a 6-bit addition which requires at least a six full adders. Alternatively, the 8-bit adder in Ahn Fig. 4 incudes at least three, four, five, or six full adder circuits).
Regarding claim 9, Badaroglu as modified in view of Luo and Ahn teaches all the limitations of claim 1 as stated above. Further, Badaroglu as modified in view of Luo and Ahn teaches wherein the full adder circuits of the ripple carry adders comprise one or more of each of a first type of full adder circuit and a second type of full adder circuit (Ahn Figs. 4-6 and col 4 lines 8-50; first type of full adder – one of the even/odd number (n or n+1) full adder; second type of full adder circuit – the other one of the even/odd number (n or n+1) full adder).
Regarding claim 11, Badaroglu as modified in view of Luo and Ahn teaches all the limitations of claim 9 as stated above. Further, Badaroglu as modified in view of Luo and Ahn teaches wherein the first type of full adder circuit corrects for a ripple carry adder logic modification caused by the second type of full adder circuit (Ahn Figs. 4-6 and col 4 lines 8-50).
Regarding claims 12, it is directed to a digital in-memory computing macro circuit, comprising substantially the same limitations as the digital in-memory computing macro circuit of claim 1 with the exception that the digital in-memory computing macro circuit of claim 12 comprises a plurality of single approximate compressors instead of a plurality of approximate compressors. Furthermore, the feature of a plurality of single approximate compressors is recited in claims 2-3. Claims 2-3 analysis applies equally to claim 12.
Regarding claims 13 and 16, they recite substantially the same limitations as claims 3 and 11 respectively. Claims 3 and 11 analysis applies equally to claims 13 and 16 respectively.
Regarding claims 17, it is directed to a digital in-memory computing macro circuit, comprising substantially the same limitations as the digital in-memory computing macro circuit of claim 1 with the exception that the digital in-memory computing macro circuit of claim 12 comprises a plurality of double approximate compressors instead of a plurality of approximate compressors. Furthermore, the feature of a plurality of double approximate compressors is recited in claims 2 and 4. Claims 2 and/or 4 analysis applies equally to claim 17.
Regarding claims 18 and 20, they recite substantially the same limitations as claims 4 and 11 respectively. Claims 4 and 11 analysis applies equally to claims 18 and 20 respectively.
Allowable Subject Matter
Claims 5-7 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 14-15 and 19 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and if rewritten to overcome the 35 U.S.C. 112(b) rejection discussed above.
The following is a statement of reasons for the indication of allowable subject matter:
The combination of Badaroglu, Luo and Ahn is the closest prior art found. Luo discloses a carry-save adder (CSA) tree structure for partial product compression that replaces accurate adders/compressors with approximate adders/compressors for reducing power and area requirements/gate count of the CSA tree circuit. Further, Luo discloses the probability of the inputs and outputs and the error associated with elements 801-802 and 807-808. Furthermore, as shown in Figs. 8E and 8H, the approximate compressor 808 includes less logic gates (and equivalently, less transistor) than the accurate compressor 805. However, Luo fails to disclose the transistor count of the approximate adders/compressors and the AND-OR gates and the root mean square error of the CSA tree in Fig. 7C. On the other hand, Ahn discloses a ripple carry adder comprising a plurality of full adders wherein the full adders receiving even input bits are configured to receive the input bits and an inverted carry in while thee full adders receiving odd input bits are configured to receive the inverted input bits and a carry. However, Luo fails to disclose the full adders in Figs. 5-6 comprise inverters at every node in the full adders that do not have a full-swing signal.
Therefore, none of the prior art references cited explicitly teach or suggest, in combination with other limitations of the claims, “wherein the double approximate compressor has fewer transistors than the single approximate compressor” as recited in claim 5; “wherein the single approximate compressor comprises less than 100 transistors” as recited in claims 6 and 15; “wherein the double approximate compressor comprises less than 70 transistors” as recited in claim 7; “wherein the first type of full adder circuit and the second type of full adder circuit comprise inverters at every node in the full adder circuits that do not have a full-swing signal” as recited in claim 10; “wherein the approximate sum has a root mean square error of 4.03%” as recited in claim 14; and “wherein the approximate sum has a root mean square error of 6.76%” as recited in claim 19.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wang et al. (NPL – “DIMC: 2219TOPS/W 2569F2/b Digital In-Memory Computing Macro in 28nm Based on Approximate Arithmetic Hardware”) discloses the claimed invention. However, Wang et al. is not considered as prior art because it was published (02/23/2022) after the effective filing date of the claimed invention (02/18/2022).
Wang et al. (NPL – “All-Digital Full-Precision In-SRAM Computing with Reduction Tree for Energy-Efficient MAC Operations”) related to a CIM macro that includes a compressor-based reduction tree, an adder tree, and a shift accumulator. However, Wang et al. is not considered as prior art because it was published (10/28-30/2022) after the effective filing date of the claimed invention (02/18/2022).
He et al. (CN 111475136 A) generally related to an approximate compressor having a zero-mean error.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlo Waje whose telephone number is (571)272-5767. The examiner can normally be reached 9:00-6:00 M-F.
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/Carlo Waje/Examiner, Art Unit 2151 (571)272-5767
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