Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/16/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(o) because figures 2C, 3, and 7 lack suitable descriptive legends. These figures have legends, however, due to the black and white and color shading of the drawings, it is unclear which legend is referring to which line in the graphs.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “The unit array of claim 9, further comprising … one or more unit arrays”, of claim 12 must be shown or the feature(s) canceled from the claim(s). The limitation is describing a unit array comprising of one or more unit arrays within the unit array. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The applicant’s specification is objected to because the paragraphs are not numbered, and thus is failing to comply with 37 CFR 1.52(b)(6) “should be individually and consecutively numbered using Arabic numerals, so as to unambiguously identify each paragraph. The number should consist of at least four numerals enclosed in square brackets, including leading zeros (e.g., [0001]).”
Appropriate correction is required.
Claim Objections
Claim 1 is objected to because of the following informalities:
Claim 1 appears to contain a grammatical error and should be changed to: “to perform computations with data stored”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With regards to claim 1, claim 1 recites the limitations of: “a plurality of unit arrays which store a weight having a sign and perform a multiplication operation on the input provided from the word line and the weight”. It is unclear if the weight is a singular weight value shared among the plurality of unit arrays or if they each individually have their own (and possibly different) weight stored in them, or if each of the plurality of unit arrays stores a value such that a combination of the plurality of values stored on each of the unit arrays results in a singular weight (each of the unit arrays store a portion of the weight value stored). Furthermore, it is unclear if the limitation is meant to be understood as all of the plurality of unit arrays each perform a multiplication operation on the input and the weight, or if it is meant to be understood as the plurality of unit arrays work together in a manner where between all of them a singular multiplication operation is performed. For purposes of examination, the Examiner interprets these limitations as meaning each of the plurality of unit arrays store their own (possibly different from one another) weight, and that each of the unit arrays individually perform their own multiplication operation such that each unit array performs a multiplication operation using their input from the word line and stored weight.
Furthermore, claim 1 recites the limitations of: “a plurality of word lines to which an input is provided”, and “the input provided from the word line”. The claim recites a plurality of word lines on which an input is provided. It is unclear which of the word lines is being referred to as “the word line” in the limitation, “the input provided from the word line”. As referenced above, the Examiner interprets the limitations, “a plurality of unit arrays which store a weight having a sign and perform a multiplication operation on the input provided from the word line and the weight”, as meaning each of the plurality of unit arrays store their own (possibly different from one another) weight, and that each of the unit arrays individually perform their own multiplication operation such that each unit array performs a multiplication operation using their input from the word line and stored weight. Therefore, the Examiner interprets at least one word line, of the plurality of word lines, to be connected to each unit array of the plurality of unit arrays, and that the above limitations are describing a single unit array of the plurality of unit arrays performing its own multiplication operation using the input from its connected word line, and its own stored weight and wherein each of the plurality of unit arrays similarly perform the multiplication operations using their own weight and input from their individually connected word lines. Furthermore, claim 1 recites the limitations of “wherein each of the plurality of unit arrays includes a source follower amplifier including a ferroelectric transistor configured to output a voltage corresponding to a result of the multiplication operation with respect to an input voltage provided to the word line”. Similarly, it is unclear which of the word lines of the plurality of word lines is “the word line”. The limitation starts of by reciting “each of the plurality of unit arrays”. Therefore, for purposes of examination, the Examiner interprets “the word line” in this limitation to mean a singular word line, of the plurality of word lines, is connected to each unit array of the plurality of unit arrays, and “the word line” is referring to the word line connected to the unit array in which the multiplication operation is performed, wherein the claim is highlighting a single unit array of the plurality of unit arrays, performing a multiplication operation.
Furthermore, claim 1 recites the limitations of: “each of the plurality of unit arrays includes a source follower amplifier including a ferroelectric transistor”. It is unclear if the limitation is meant to be understood as the source follower amplifier is a larger circuit and includes a ferroelectric transistor, or if it is meant to be understood as the source follower amplifier itself is a ferroelectric transistor. For purposes of examination, the Examiner interprets the source follower amplifier to be the ferroelectric transistor.
Furthermore, claim 1 recites the limitations of: “each of the plurality of unit arrays includes a source follower amplifier including a ferroelectric transistor configured to output a voltage corresponding to a result of the multiplication operation with respect to an input voltage provided to the word line”. It is unclear if the output voltage “corresponding to a result of the multiplication operation” is meant to directly be the result of the multiplication operation, or if it is meant to be some other value related but not directly equivalent to the result of the multiplication operation.
Furthermore, claim 1 recites the limitations of: “each of the plurality of unit arrays includes a source follower amplifier including a ferroelectric transistor configured to output a voltage corresponding to a result of the multiplication operation”. The claim language of the limitations imply a possibility of multiple results output from the singular multiplication operation, “output a voltage corresponding to a result of the multiplication operation”. It is unclear if it is meant to be understood as there are more than one result and the output voltage corresponds to one of them, or if the limitation is meant to be understood as “each of the plurality of unit arrays includes a source follower amplifier including a ferroelectric transistor configured to output a voltage corresponding to [[a]] the result of the multiplication operation”.
Furthermore, claim 1 recites the limitations of: “and an accumulation line connected to the plurality of unit arrays and on which results of the multiplication operations performed by the plurality of unit arrays are accumulated”, and “each of the plurality of unit arrays includes a source follower amplifier including a ferroelectric transistor configured to output a voltage corresponding to a result of the multiplication operation with respect to an input voltage provided to the word line”. The claim describes the multiplication to be between an input and a weight, and only describes outputting a voltage “corresponding” to a result of the multiplication operation. The claim further describes accumulating the results of the multiplication operations on the accumulation line. It is unclear if the result of the multiplication operation is meant to be a current or a voltage. The described circuitry resembles a parallel circuit with the input of the unit arrays being provided a same input from a word line, and having the output at the accumulation line. However, the output of a parallel circuit would not be summing (accumulating) the voltages across the parallel components, though currents in parallel circuitries are summed1. It is unclear if the claim is meant to be understood as currents are accumulated, voltages are accumulated, or the outputs of the multiplication are currents summed and converted into a voltage, or if the unit arrays are meant to instead resemble a series circuit.
Claims 2-8 inherit the same deficiencies as claim 1 based on dependence.
With regards to claim 2, claim 2 recites the limitations of: “wherein the unit array includes”. Claim 1, which claim 2 is dependent upon, recites “a plurality of unit arrays”. It is unclear which of the unit arrays of the plurality of unit arrays claim 2 is referring to. For purposes of examination, the Examiner interprets the claim to be referring to each unit array of the plurality of unit arrays.
Furthermore, claim 2 recites the limitations of: “wherein the unit array includes: a plurality of source follower amplifiers”. Claim 2 is dependent on claim 1, claim 1 recites the limitations of, “each of the plurality of unit arrays includes a source follower amplifier including a ferroelectric transistor”. As referenced above, the Examiner interprets source follower amplifier, of claim 1, to be the ferroelectric transistor. However, with claim 2 reciting that the unit array includes a plurality of source followers, it is unclear if they all are meant to include/be ferroelectric transistors, or if only one of the plurality of source follower amplifiers are meant to include/be a ferroelectric transistor. For purposes of examination, the Examiner interprets all of the source followers to be ferroelectric transistors.
Claims 3-7 inherit the same deficiencies as claim 2 based on dependence.
With regards to claim 3, claim 3 recites the limitations of: “wherein a drain of the source follower amplifier is supplied with a predetermined voltage”. Claim 3 is dependent on claim 2, claim 2 recites “a plurality of source follower amplifiers”. It is unclear which of the plurality of source follower amplifiers claim 3 is referring to. For purposes of examination, the Examiner interprets the claim to mean that each of the source followers comprise a drain which the predetermined voltage is supplied.
With regards to claim 4, claim 4 recites the limitations of: “the ferroelectric transistor has a threshold voltage corresponding to the weight stored in the ferroelectric transistor”. Claim 4 is dependent on claim 1, claim 1 recites the limitations of, “a plurality of unit arrays which store a weight”, and “each of the plurality of unit arrays includes a source follower amplifier including a ferroelectric transistor”. Claim 1 describes the ferroelectric transistor as being a part of a unit array. It is unclear if the weight stored in the ferroelectric transistor is the same weight as is stored by the unit array, or if the weight stored in the ferroelectric transistor is an additional, separate weight stored. For purposes of examination, the Examiner interprets the weight stored in the ferroelectric transistor to be the same as the weight stored by the unit array.
Furthermore, claim 4 recites the limitations of: “the ferroelectric transistor”. Claim 4 is dependent on claim 1, claim 1 recites the limitations of, “each of the plurality of unit arrays includes a source follower amplifier including a ferroelectric transistor”. Furthermore, claim 4 is dependent on claim 2, claim 2 recites the limitation, “the unit array includes: a plurality of source follower amplifiers” and as referenced above, the examiner interprets all of the source followers to be ferroelectric transistors. Therefore, it is unclear not only which of the plurality of ferroelectric transistors within a single unit array claim 4 is referring to as “the ferroelectric transistor”, but also, because claim 1 describes each of the plurality of unit arrays as comprising a ferroelectric transistor, which ferroelectric transistor claim 4 is referring to out of the plurality of ferroelectric transistors referenced in claim 1, “each of the plurality of unit arrays includes a source follower amplifier including a ferroelectric transistor”.
Furthermore, claim 4 recites the limitations of: “and the source follower amplifier outputs a voltage”. Claim 4 is dependent on claim 1, claim 1 recites the limitations of, “each of the plurality of unit arrays includes a source follower amplifier”. Furthermore, claim 4 is dependent upon claim 2, claim 2 recites the limitations of, “a plurality of source follower amplifiers”. It is unclear which of the plurality of source follower amplifiers claim 4 is referring to.
Furthermore, claim 4 recites the limitations of: “the source follower amplifier outputs a voltage corresponding to a difference between the threshold voltage and a voltage corresponding to the provided input as a result of the multiplication operation to the multiplication line”. Claim 4 is dependent upon claim 2, claim 2 recites the limitations of, “a transfer switch configured to control a connection between the multiplication line and the accumulation line”. Claim 4 is also dependent on claim 1, claim 1 recites the limitations of, “each of the plurality of unit arrays includes a source follower amplifier including a ferroelectric transistor configured to output a voltage corresponding to a result of the multiplication operation with respect to an input voltage provided to the word line”, and “an accumulation line connected to the plurality of unit arrays and on which results of the multiplication operations performed by the plurality of unit arrays are accumulated”. It is unclear if the output voltage of the claim 4 limitation, “the source follower amplifier outputs a voltage … as a result of the multiplication operation to the multiplication line”, is meant to be the same as the voltage of the claim 1 limitation, “source follower amplifier including a ferroelectric transistor configured to output a voltage corresponding to a result of the multiplication operation”, or if the claim 4 limitation is meant to be understood as the source follower amplifier outputs a different voltage than that of the claim 1 limitation.
Furthermore, claim 4 recites the limitations of: “the source follower amplifier outputs a voltage … as a result of the multiplication operation to the multiplication line”. The claim language of the limitations imply a possibility of multiple results output from the singular multiplication operation, “the source follower amplifier outputs a voltage … as a result of the multiplication operation to the multiplication line”. It is unclear if it is meant to be understood as there are more than one result and the source follower outputs a voltage of one of the results, or if the limitation is meant to be understood as “the source follower amplifier outputs a voltage … as [[a]] the result of the multiplication operation to the multiplication line”.
Furthermore, claim 4 recites the limitations of: “the source follower amplifier outputs a voltage corresponding to a difference between the threshold voltage and a voltage corresponding to the provided input as a result of the multiplication operation to the multiplication line”. Claim 4 is dependent on claim 1, claim 1 recites the limitation of, “unit arrays which store a weight having a sign and perform a multiplication operation on the input provided from the word line and the weight”. Claim 1 describes the multiplication operation as the input from the word line multiplied with the stored weight. Claim 4 describes the result of the multiplication operation as “a difference between the threshold voltage and a voltage corresponding to the provided input”. It is unclear if the multiplication of claim 4 is meant to replace the multiplication operation of claim 1, or if the multiplication operation of claim 4 is meant to be in addition to the multiplication operation of claim 1, or if the multiplication operation between the input and the weight is meant to be equivalent to a difference between the threshold voltage and a voltage corresponding to the provided input, or if the operation that is computed by the source follower amplifier is actually a difference between the voltage corresponding to the input and the threshold voltage and the result of the difference operation is equivalent to if the input were to be multiplied with the weight.
With regards to claim 5, claim 5 recites the limitations of: “when the input corresponds to a logic low, the transfer switch is turned on”. Claim 5 is dependent on claim 2, claim 2 recites the limitation of, “wherein the unit array includes: … a transfer switch”. Claim 2 is dependent upon claim 1, claim 1 recites the limitation of, “a plurality of unit arrays”. As referenced above, the Examiner interprets the claim 2 limitation to be referring to each unit array of the plurality of unit arrays. Therefore, it is unclear which transfer switch of the plurality claim 5’s limitation is referring to. For purposes of examination, the Examiner, similarly to the interpretation of claim 1, interprets claim 5 to be referring to each transfer switch which is included in each of the plurality of unit arrays.
Claim 6 inherits the same deficiency as claim 5 based on dependence.
With regards to claim 7, claim 7 recites the limitations of: “the transfer switch is turned on”. Claim 7 is dependent on claim 2, claim 2 recites the limitation of, “wherein the unit array includes: … a transfer switch”. Claim 2 is dependent upon claim 1, claim 1 recites the limitation of, “a plurality of unit arrays”. As referenced above, the Examiner interprets the claim 2 limitation to be referring to each unit array of the plurality of unit arrays. Therefore, it is unclear which transfer switch of the plurality claim 7’s limitation is referring to. For purposes of examination, the Examiner, similarly to the interpretation of claim 1, interprets claim 7 to be referring to each transfer switch which is included in each of the plurality of unit arrays.
With regards to claim 9, claim 9 recites the limitations of: “a multiplication line from which a result of a multiple operation is output”. It is unclear if the limitation is meant to be understood as there are multiple operations output to a multiplication line, or if it is meant to be understood as a multiplication line from which a result of a multiplication operation is output.
Furthermore, claim 9 recites the limitations of: “and a plurality of source follower amplifiers composed of a ferroelectric transistor”. It is unclear if the limitation is meant to be understood as there are a plurality of source follower amplifiers each composed of a ferroelectric transistor or if it is meant to be understood as the plurality of source follower amplifiers are composed of a singular ferroelectric transistor. For purposes of examination, the Examiner interprets the limitation to be understood as there are a plurality of source follower amplifiers each composed of a ferroelectric transistor.
Furthermore, claim 9 recites the limitations of: “and a source for outputting a result of a multiplication operation”. Claim 9 also recites the limitation of, “a memory module and configured to perform a multiplication operation”. It is unclear if the multiplication operation in the limitation “and a source for outputting a result of a multiplication operation” is meant to be the same multiplication or a different multiplication operation than the multiplication operation from the limitation “a memory module and configured to perform a multiplication operation” mentioned earlier in the claim.
Furthermore, claim 9 recites the limitations of: “outputs a difference between the input and a threshold voltage of the ferroelectric transistor as the result of the multiplication operation”, and “a source for outputting a result of a multiplication operation of the weight value and the input”. It is unclear if the multiplication operations of these two limitations are meant to be the same operation, or separate operations. It is unclear if the operation of the limitation “outputs a difference between the input and a threshold voltage of the ferroelectric transistor as the result of the multiplication operation” is meant to be what the source follower is actually doing, with the result of the difference operation being equivalent to “a multiplication operation of the weight value and the input”, or if the source follower amplifier is performing “a multiplication operation of the weight value and the input” with the result being equivalent to “a difference between the input and a threshold voltage of the ferroelectric transistor”.
Furthermore, claim 9 recites the limitations of: “wherein the source follower amplifier outputs a difference”. Claim 9 also recites the limitation of, “a plurality of source follower amplifiers”. It is unclear which of the source follower amplifiers the limitation is referring to.
Furthermore, claim 9 recites the limitations of: “the weight value”. There is insufficient antecedent basis for this limitation in the claim.
Claims 10-12 inherit the same deficiencies as claim 9 based on dependence.
With regards to claim 11, claim 11 recites the limitations of: “wherein an input is provided to one of the plurality of word lines”. Claim 11 is dependent on claim 9, claim 9 recites the limitation of, “a plurality of word lines to which an input is provided”. It is unclear if the “an input” is referring to the same input as of claim 9, or if the “an input” is a different input from claim 9.
Furthermore, claim 11 recites the limitations of: “the source follower amplifier”. Claim 11 is dependent upon claim 9, claim 9 recites the limitation of, “a plurality of source follower amplifiers”. It is unclear which of the plurality of source follower amplifiers claim 11 is referring to.
Furthermore, claim 11 recites the limitations of: “an input is provided to one of the plurality of word lines”. Claim 11 is dependent upon claim 9, claim 9 recites the limitation of, “a plurality of word lines to which an input is provided”. Claim 9 recites that an input is provided to the plurality of word lines, not a singular of the word lines. It is unclear how the limitation of claim 11 coincides with the limitation set forth in the claim it is dependent upon, claim 9.
With regards to claim 12, claim 12 recites the limitations of: “comprising an accumulation line connected to the multiplication line and on which the multiplication result is accumulated”. It is unclear if “and on which the multiplication result is accumulated” is meant to be referring to the multiplication line, the accumulation line, or both the accumulation and multiplication lines.
Furthermore, claim 12 recites the limitations of: “The unit array of claim 9 further comprising”, and “and one or more unit arrays”. The claim limitation “The unit array of claim 9 further comprising” is describing a singular unit array, and “further comprising” describes additional functions/functions within the unit array. The limitation of “and one or more unit arrays” is unclear if the one or more unit arrays are meant to be within the unit array of claim 9, or some exterior unit arrays not yet mentioned.
Furthermore, claim 12 recites the limitations of: “accumulation line connected to the multiplication line and on which the multiplication result is accumulated, and one or more unit arrays connected to the accumulation line, wherein results of multiplication operations of the one or more unit arrays are accumulated on the accumulation line”. Claim 12 is dependent on claim 9, claim 9 recites the limitations of “a source for outputting a result of a multiplication operation of the weight value and the input to the multiplication line, wherein the source follower amplifier outputs a difference between the input and a threshold voltage of the ferroelectric transistor as the result of the multiplication operation”. Claim 9 describes the output as a result of the multiplication operation as the difference between the input and a threshold voltage. It is unclear if the result being accumulated on the accumulation line is meant to be a current or a voltage. The described multiplication of a source follower amplifier performing a multiplication operation by outputting the difference between an input and the threshold voltage would suggest a voltage output2. However, claim 9 further describes a parallel circuit, a shared input on word lines (and drain with a same predetermined voltage) “unit array comprising: a plurality of word lines to which an input is provided”, and “unit array comprising: a plurality of word lines to which an input is provided”, and a shared output line, “a source for outputting a result of a multiplication operation of the weight value and the input to the multiplication line”. However, the output of a parallel circuit would not be summing (accumulating) the voltages across the parallel components, though currents in parallel circuitries are summed3. It is unclear if the claim is meant to be understood as currents are accumulated, voltages are accumulated, or the outputs of the multiplication are currents summed and converted into a voltage, or if the unit arrays are meant to instead resemble a series circuit.
Deferring of Indication of Allowable Subject Matter and application of prior art
Due to the nature of, and numerous amounts of 35 U.S.C. 112(b) rejections made rendering the Examiner unable to reasonably discern many of the limitations claimed, the Examiner is deferring decision as to application of prior art, and/or indication of allowable subject matter over prior art pending resolution of the 35 U.S.C. 112(b) rejections made.
Prior Art Made of Record
The prior art made of record and not relied upon is considered pertinent to Applicant’s
disclosure:
Tran et al. U.S. Patent Application Publication 2022/0374161 A1
Discloses a computation apparatus located in memory and configured to perform computation with data stored in the memory. (Fig. 7 item 32 (Vector by matrix array), 33 (non-volatile memory array); [0029] regarding non-volatile memory cell array 33 multiplies the inputs by the weights stored)
Discloses the computation apparatus comprising: a plurality of word lines to which an input is provided. (Fig. 7 item 33 (non-volatile memory array); Fig. 9 regarding a plurality of word lines)
Discloses a plurality of unit arrays which store a weight having a sign. (Fig. 9 regarding the plurality of memory cells; [0030] regarding positive and negative weights stored in the cell array)
Discloses performing a multiplication operation on the input provided from the word line and the weight. ([0029] regarding multiplying the inputs by the weights stored in the non-volatile memory array 33; [0028] regarding input to the VMM array is from the word line; [0044] regarding a word line used for input voltage into the memory cell; Fig. 9 regarding word lines into gates of transistors in memory cells)
Discloses an accumulation line connected to the plurality of unit arrays and on which results of the multiplication operations performed by the plurality of unit arrays are accumulated. ([0029] regarding multiplying the inputs by the weights stored in the non-volatile memory array 33, and adding them up per output line (source line))
Discloses each of the plurality of unit arrays includes a source follower configured to output a current corresponding to the result of the multiplication operation with respect to an input provided to the word line. (Figs. 2-5 showing memory cells with the bit lines connected to the drain of the transistor; [0029] regarding multiplying inputs with weights, and adding up the multiplication results on the source line; [0037] regarding summing all of the currents to the source line)
Discloses the memory cells operating in the linear region, and discloses that a transistor operating in the linear region can be used to linearly convert an input/output current into an input/output voltage ([0045]-[0047])
Tian-ling et al. CN117474058 A
Discloses a computation apparatus using ferroelectric transistors for multiplying an input with a weight (Fig. 1; page 21/29 paragraph 4)
Discloses a pre-charge circuit (Fig. 1 reference number 102)
Discloses the stored weight as having a sign (paragraph [0092], and page 29/29 regarding a translated table which includes weights with negative and positive values)
Discloses accumulating voltages of the first and second RBL (page 21/29 paragraph 13)
Discloses a transistor configured in the manner of a source follower amplifier (page 25/29 paragraph 14 regarding an input applied to the gate, drain connected to ground, and source connected to RBL)
Kobayashi et al. U.S. Patent Application Publication 2021/0026601 A1
Discloses a computer apparatus, computing multiply accumulate operations (Fig. 8A; [0101])
Discloses storing weights with a sign ([0120] regarding multiply-accumulate operations on positive and negative weights)
Discloses the computation performed using ferroelectric transistors (Fig. 8A; [0101])
Discloses the transistors as being able to be in the configuration of a source follower amplifier ([0171] regarding source of transistors connected to output line, drain connected to an input)
Conclusion
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/J.A.K./Examiner, Art Unit 2182 /EMILY E LAROCQUE/ Primary Examiner, Art Unit 2182
1 Parallel Circuit vs series circuit. Parallel Circuit vs Series Circuit - Difference and Comparison | Diffen. (2022, April). web.archive.org/web/20220408181534/https://www.diffen.com/difference/Parallel_Circuit_vs_Series_Circuit regarding parallel and series circuitries
2 Prasad, Guru. (2017). Design and Analysis of Super Source Follower. 10.13140/RG.2.2.29886.41288.
Regarding a difference between the input and threshold voltage results in an output voltage
3 Parallel Circuit vs series circuit. Parallel Circuit vs Series Circuit - Difference and Comparison | Diffen. (2022, April). web.archive.org/web/20220408181534/https://www.diffen.com/difference/Parallel_Circuit_vs_Series_Circuit regarding parallel and series circuitries
Prosecution Insights