Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This Office Action responds to the Application filed on 2/16/2023 and IDS filed on 2/16/2023 and 12/16/2024.
Claims 1-13 are pending.
Specification
3. The disclosure is objected to because of the following:
Equations on Pages 5; Lines 5-15 and 14; Lines 5-14, Page 17; Lines 17-24,
Page 18; Line 1 are not legible.
Appropriate correction is required.
Claim Objections
4. Claim 7 objected to because of the following:
Equations in claim 7 is not legible.
5. Appropriate correction is required.
Claim Rejections - 35 USC § 112
6. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
7. Claims 1-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 and similarly claim 13 recited “a first training operation of performing
training with a design parameter of the SRAM according to a read operation metric of the SRAM… a transistor level simulation result of the SRAM…a second training operation of performing training with the design parameter of the SRAM according to the read operation metric of the SRAM… a layout level simulation result of the SRAM… a third training operation of performing training with the design parameter of the SRAM according to the read operation metric of the SRAM… a measurement result measured with a chip in which the SRAM is formed”, however it is not apparent of the relationship between the first training operation, the second training operation, and the third training operation. It is not apparent what the first training operation, the second training operation, and the third training operation represent in relation to determine of read access yield. It is not apparent what is simulated with the transistor level of the SRAM in order to get the transistor level simulation result of the SRAM. It Is not apparent what is simulated with respect to the layout level simulation of the SRAM, in order to get the result of layout level simulation. It is not apparent what is measured with respect to the SRAM in order to obtain the measurement result measured with a chip in which the SRAM is formed.
Claim 8 recited “inputting a transistor level simulation result of the SRAM, a layout level simulation result of the SRAM, and a measurement result measured with a chip in which the SRAM is formed”, however It is not apparent what is simulated with the transistor level of the SRAM in order to get the transistor level simulation result of the SRAM. It Is not apparent what is simulated with respect to the layout level simulation of the SRAM, in order to get the result of layout level simulation. It is not apparent what is measured with respect to the SRAM in order to obtain the measurement result measured with a chip in which the SRAM is formed.
As per claims 2-7, 9-11, and 13 are rejected to for incorporating the above limitations into the claims by dependency.
Allowable Subject Matter
8. Claims 1-13 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
9. The following is a statement of reasons for the indication of allowable subject matter:
With respect to claims 1-7, the closest prior art Kim et al. (U.S. Pub. No.
2019/0065630), teach a training method that train a neural network using a transistor level simulation result (See Figure 1 B, i.e. S112), and using a layout level simulation result (See Figure 1B, i.e. S114).
The prior art does not teach: A static random access memory (SRAM) read access yield training method that is a method of training a multi-layer perceptron on a read access yield of an SRAM, the method comprising: a first training operation of performing training with a design parameter of the SRAM according to a read operation metric of the SRAM, training data according to the read operation metric of the SRAM, and a transistor level simulation result of the SRAM; a second training operation of performing training with the design parameter of the SRAM according to the read operation metric of the SRAM, the training data according to the read operation metric of the SRAM, and a layout level simulation result of the SRAM; and a third training operation of performing training with the design parameter of the SRAM according to the read operation metric of the SRAM, the training data according to the read operation metric of the SRAM, and a measurement result measured with a chip in which the SRAM is formed, as recited in independent claim 1, wherein claims 2-7 depend on claim 1.
With respect to claims 8-11, the closest prior art Kim et al. (U.S. Pub. No.
2019/0065630), teach a training method that train a neural network using a transistor level simulation result (See Figure 1 B, i.e. S112), and using a layout level simulation result (See Figure 1B, i.e. S114).
The prior art does not teach: A static read only memory (SRAM) read access yield prediction method using a trained multi-layer perceptron, the method comprising:
inputting a transistor level simulation result of the SRAM, a layout level simulation result of the SRAM, and a measurement result measured with a chip in which the SRAM is formed into the multi-layer perceptron trained with the same design parameter of the SRAM and the same training data according to a read operation metric of the SRAM, together with the design parameter of the SRAM; inferring, by the multi-layer perceptron, a probability corresponding to the read operation metric; and computing a read access yield of the SRAM from the computed probability, as recited in independent claim 8, wherein claims 9-11 depend on independent claim 8.
With respect to claims 12-13, the closest prior art Kim et al. (U.S. Pub. No.
2019/0065630), teach a computing apparatus comprising: at least one processor; and a memory in which one or more programs to be executed by the at least one processor are stored, wherein the one or more programs, when executed by the at least one processor, cause the at least one processor to (See Figure 1A) perform a training method of training a neural network with transistor level simulation result (See Figure 1 B, i.e. S112), and using a layout level simulation result (See Figure 1B, i.e. S114).
The prior art does not teach: a first training operation of performing training with a design parameter of the SRAM according to a read operation metric of the SRAM, training data according to the read operation metric of the SRAM, and a transistor level simulation result of the SRAM; a second training operation of performing training with the design parameter of the SRAM according to the read operation metric of the SRAM, the training data according to the read operation metric of the SRAM, and a layout level simulation result of the SRAM; and a third training operation of performing training with the design parameter of the SRAM according to the read operation metric of the SRAM, the training data according to the read operation metric of the SRAM, and a measurement result measured with a chip in which the SRAM is formed, as recited in independent claim 12, wherein claim 13 depend on claim 12.
Conclusion
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NHA T NGUYEN whose telephone number is (571)270-1405. The examiner can normally be reached M-F 8:00AM-5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NHA T NGUYEN/Primary Examiner, Art Unit 2851
Prosecution Insights