DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7/27/2026 has been entered.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11588261 and claims 1-20 of U.S. Patent No. 11018444. Although the claims at issue are not identical, they are not patentably distinct from each other because the processors, the memory or storage drives, inputs/outputs , the controller are disclosed as operating claimed and features are slightly different.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 13 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. US 2016/0085718 A1 (hereinafter Huang) in view of Thompson US 2017/0357610 A1 (hereinafter Thompson).
Regarding claim 1, Huang discloses a device comprising a processor and a memory drive connected to the processor. In particular, Huang discloses an extended NVMe storage network in which each storage node 111a, 111b includes a host processor (CPU A/CPU B), local non-volatile memories, and an extended NVMe controller 112A/112B. Huang further teaches that the controller can accept NVMe commands, access the local non-volatile memories, and convert NVMe commands to NVM-over-Ethernet (“NVMoE”) commands for accessing remote non-volatile memories. See Huang, Fig. 1A and paragraph [0052].
Huang further discloses wherein the device operates in a first operating mode or a second operating mode based on a first instruction. Huang teaches that received NVMe commands/data may be directed either to a local namespace for local memory/storage or to a remote namespace for remote memory/storage. See Huang paragraph [0074], Figs. 4-5. Where an NVMe command is directed to remote memory, the extended NVMe controller converts the command into an NVMoE command suitable for transmission over the external network. See Huang paragraph [0075], Fig. 4. Thus, the received NVMe command constitutes the claimed first instruction, and the destination identified by that instruction determines whether the controller operates using conventional/local NVMe access or networked NVMoE access.
The interpretation is further supported by Huang paragraphs [0050]-[0053]. Huang teaches receiving from the host CPU an NVMe command directed to a remote namespace, applying an NVMe-over Ethernet protocol to that command, and also expressly distinguishes conventional NVMe functionality in which the host processor accesses local non-volatile memory. See Huang paragraphs [0050]-[0053], Figs. 1A-1B.
Huang further discloses wherein, in the first operating mode, the device is configured to operate at a first non-zero operating speed. Huang explains that conventional NVMe provides direct I/O access to local non-volatile memory over a PCIe interface. See Huang paragraph [0006]. Huang’s local-access embodiment of Fig. 1A similarly performs actual NVMe data transfer between the host processor, controller, and local non-volatile memory. See Huang paragraph [0052], Fig. 1A. Accordingly, operation of the PCIe/NVMe link necessarily occurs at a non-zero operating speed.
Huang, however, does not expressly characterize its networked NVMoE implementation using the standardized terminology “NVMe over Fabrics (NVMe-oF)” recited in the claim.
Thompson expressly teaches this limitation. Thompson teaches an NVMe storage system employing NVMe over Fabric (NVMf) SSDs coupled through a network. See Thompson paragraph [0009], Fig. 1. Thompson further teaches, with respect to Fig. 2, a PCIe/NVMe initiator communicating with network-attached Flash devices 204-206, wherein both the NVMe initiator and network-attached Flash devices use the NVMe over Fabrics protocol. See Thompson paragraph [0010], Fig. 2. Thompson expressly identifies the NVMf device as a solid-state disk providing nonvolatile storage and requiring an NVMe-over-Fabrics-compatible interface to the Ethernet network. See Thompson paragraph [0011].
Therefore, Thompson teaches wherein the second operating mode comprises a Non-volatile memory Express (NVMe) over fabrics (NVMe-oF) mode.
It would have been obvious to one of ordinary skill in the art before the effective filing date to implement Huang’s networked NVMe/NVMoE operating functionality using the NVMe-over-Fabrics protocol taught by Thompson because both references address providing remote access to nonvolatile/SSD storage by transporting NVMe commands across an Ethernet/network fabric. Huang expressly identifies the purpose as extending NVMe from local PCIe storage to remote storage over Ethernet, while Thompson teaches NVMe-oF as an implementation for connecting NVMe initiators to network-attached SSDs. Such a modification would have amounted to using a known NVMe network transport protocol for its known purpose of providing network access to NVMe storage, with the predictable result of operating Huang’s network attached storage functionality according to NVMe-oF protocol.
Huang further discloses wherein, in the NVMe-oF mode, the memory drive selects a second non-zero operating speed from among two or more non-zero operating speeds available in the NVMe-oF mode based on a second instruction.
In particular, Huang discloses a network storage-device flow-control mechanism in Fig. 17. Huang expressly stages that the source and target may each be a storage node, host device, or storage device. See Huang paragraph [0104], Fig. 17.
More particularly, Huang teaches:
-when the target buffer status is “Satisfied,” the source transitions to XSLOW, in which data/control data is transmitted at a slow or reduced speed, e.g., one-half the full speed; and
-when the target status is “Hungry” or “Starving,” the source transitions to XON, in which data/control data is transmitted at full speed.
See Huang paragraph [0106], Fig. 17. Thus, Huang expressly provides at least two different non-zero operating speeds—a reduced/half speed and a full speed—from which the networked storage device selects according to received control information.
Huang further teaches that the source periodically polls the target or otherwise receives an updated target status and “changes states” depending upon the target’s flow-control message. See Huang [0107], Fig. 17. Thus, selection between the available non-zero speeds is responsive to the second instruction rather than merely being a fixed hardware capability.
Huang additionally discloses an extended NVMe controller including an Ethernet MAC that may be, for example, a 10GE MAC or 40GE MAC, further establishing that multiple non-zero Ethernet operating rates were known for Huang’s networked NVMe architecture. See Huang paragraph [0079], Fig. 6.
Accordingly, it would have been obvious to retain Huang’s disclosed instruction-responsive network flow/speed-selection mechanism when implementing Huang’s networked NVMe operation using Thompson’s NVMe-oF protocol because the flow-control mechanism performs the same known function—adjusting data-transfer rate according to the receiving storage device’s condition—and Thompson’s substitution of an NVMe-oF transport does not eliminate the known need for network flow control. The combination therefore yields an NVMe-oF storage system in which the storage device selects between two or more non-zero operating speeds based upon received control information.
Regarding “the second non-zero operating speed being different from the first non-zero operating speed,” Huang expressly teaches different non-zero transmission rates, including full speed and a reduced speed such as one-half full speed, and teaches actively selecting between those rates according to the flow control message. See Huang paragraph [0105]-[0107], Fig. 17. It would have been obvious to select, during the networked/NVMe-oF operation supplied by Thompson, a non-zero rate different from the rate used during conventional/local NVMe operation because Huang expressly teaches varying the networked operating rate in response to operating conditions, thereby providing the predictable benefit of controlling network traffic and preventing target-buffer overrun.
Regarding claim 13, Huang teaches a first interface layer (Fig. 6); a memory drive (NVME) attached to the first interface layer at a first side of the memory drive; a processor (Fig. 1A) connected to the memory drive; and a second interface layer attached to the processor at a second side of the processor. The rest of the claim language is rejected for the same reasons set forth above in claim 1.
As per claim 18, it’s rejected for the same reasons set forth above in claims 13 and claim 1.
Claims 2-7, 9-12, 14-17, 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. US 2016/0085718 A1 (hereinafter Huang) in view of Thompson US 2017/0357610 A1 (hereinafter Thompson), and further in view of McKnight US 20170300445 A1 (hereinafter McKnight).
As per claim 2, Huang in view of Thompson teaches the device of claim 1 as discussed above but did not specifically teach the limitation of claim 2. However, McKnight teaches a printed circuit board (PCB: 100, 200, 108, or see abstract or paragraph 0090), wherein: the memory drive is connected at a first side of the PCB via a connector; and the processor (102) is mounted on the PCB at a second side of the PCB.
It would have been obvious to one of ordinary skill in the art before the effective filing date to mount the Huang/Thompson NVMe-oF storage components using McKnight’s known PCB and connector arrangement because McKnight expressly teaches such an arrangement for mount and interconnecting NVMe storage devices in ca compact storage system, and thereby providing a compact and modular storage architecture that facilitate connection and replacement of storage devices and accommodates different storage protocols with reduced redesign.
Regarding claim 3, McKnight discloses: the processor comprises a field programmable gate array (FPGA(see paragraph 0091); the memory drive comprises a first solid state drive (SSD: see paragraphs 0015, 0046) and a second SSD; the connector comprises a first SSD connector and a second SSD connector; and the first SSD is connected to the PCB at the first side of the PCB via the first SSD connector and the second SSD is connected to the PCB at the first side of the PCB via the second SSD connector (see paragraphs 0015, 0038).
Regarding claim 4, McKnight discloses: the connector is electrically connected to the memory drive (112, 130, NVME, NAS or see paragraphs 0010) at a first side of the memory drive; and the connector is attached to the PCB at the first side of the PCB and is perpendicular to the first side of the PCB.
Regarding claim 5, McKnight discloses: a structural support between the second side of the PCB and a second side of the memory drive (112, 130, NVME, NAS or see paragraphs 0010).
Regarding claims 6 and 16, McKnight discloses: a length of the memory drive is of 3.5” and a length of the PCB, but fails to explicitly disclose the length of the board being about 110 and 142 mm or the length of the PCB being equal to or greater than a length of the memory drive or the length of the PCB is equal to or longer than a length of the processor, wherein the length of the processor is about 80 mm or the two or more non-zero operating speeds of the memory drive are two or more operating speeds at or greater than 10G, such a modification would have involved a mere change in the size of the component, which is considered as a change of size of a component. A change in size of a component generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). It would have been obvious to one having ordinary skill in the art to have the length of the board being about 110 and 142 mm, or a length of the PCB is equal to or longer than a length of the processor, wherein the length of the processor is about 80 mm or the two or more non-zero operating speeds of the memory drive are two or more operating speeds at or greater than 10Gin order to meet the system specification and requirement.
Regarding claim 7, McKnight discloses a first side of the processor (102) is attached to the second side of the PCB, wherein the processor is electrically connected to the PCB (figs. 1-2).
Regarding claims 9-11, 17, 20, McKnight discloses: the aforementioned limitations, but fails the length of the PCB being equal to or greater than a length of the memory drive or the length of the PCB is equal to or longer than a length of the processor, wherein the length of the processor is about 80 mm or the two or more non-zero operating speeds of the memory drive are two or more operating speeds at or greater than 10G, such a modification would have involved a mere change in the size of the component. A change in size of a component is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). It would have been obvious to one having ordinary skill in the art to be longer than a length of the processor, wherein the length of the processor is about 80 mm or the two or more non-zero operating speeds of the memory drive are two or more operating speeds at or greater than 10G in order to meet the system specification and requirement.
Regarding claim 12, McKnight discloses the first instruction is received from a mid-plane (see abstract), wherein the first instruction is controlled by two general-purpose input/output (GPIO) pins controlled by a baseboard management controller (BMC) of a switch or a local central processing unit (CPU) of a motherboard, or one or more internal registers associated with the processor (see paragraphs 0013, 0073.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date to provide the mode-selection instruction through known platform-management mechanisms such as GPIO pins, BMC control, a local CPU, or processor registers, because each was a known mechanism for communicating configuration/control information to storage hardware.
Regarding claim 14, McKnight discloses a printed circuit board (PCB) connected to the memory drive at a first side of the PCB via a connector, wherein the processor is mounted on the PCB at a second side of the PCB and a first side of the processor is attached to the PCB, wherein the connector is perpendicular to the first side of the PCB (see paragraphs 0015, 0038). The motivation of claim 2 applies in here as well.
Regarding claim 15, McKnight discloses a structural support between the second side of the PCB and a second side of the memory drive (see paragraphs 0015, 0038).
Regarding claim 19, McKnight discloses connecting the memory drive (112, 130, NVME, NAS or see paragraphs 0010) at a first side of a printed circuit board (PCB) via a connector; mounting the processor on a second side of the PCB (see paragraphs 0015, 0038). , wherein a first side of the processor (102) is attached to the PCB; and incorporating a structural support between the second side of the PCB and a second side of the memory drive, 25 wherein the connector is perpendicular to the first side of the PCB (see paragraphs 0015, 0038). The motivation in claim 2 above applies in here as well.
Response to Arguments
Applicant’s arguments filed in response to the previous Office Action have been fully considered but are not persuasive.
Applicant argues that McKnight does not disclose or suggest a single storage device that operates in a first operating mode at a first non-zero operating speed and, in a second NVMe-oF operating mode, selects a different second non-zero operating speed from among two or more available non-zero operating speeds based on a second instruction. Applicant further argues that modifying McKnight to provide such functionality would require a change in McKnight’s principle of operation. These arguments are moot in view of the newly applied prior art. The present rejection no longer relies upon McKnight to teach the disputed limitations. Instead, Huang in view of Thompson is relied upon.
In particular, Huang teaches an extended NVMe controller that receives NVMe commands directed to either local storage or remote storage and converts commands directed to remote storage into NVMoE commands for transmission over an Ethernet network. Huang further teaches instruction-responsive selection between different non-zero transmission speeds. In the flow-control embodiment of Fig. 17, the source operates at a reduced speed, e.g., half of full speed, in the XSLOW state and a full speed in the XON state depending upon the target’s flow control message. See Huang, Fig. 17 and paragraphs [0104]-[0107].
Thompson expressly teaches NVMe over Fabrics (NVMe-oF) storage, including network-attached Flash devices/SSDs communicating using the NVMe-over Fabrics protocol and presenting an NVMe-oF compatible interface to an Ethernet network. See Thompson, Figs. 1-2 and paragraph [0009]-[0011].
Accordingly, Applicant’s arguments that McKnight fails to disclose the claimed NVMe-oF mode, first and second non-zero operating speeds, or instruction-responsive selection of the second operating speed are moot, because those limitations are now addressed by Huang and Thompson in the new rejection.
Allowable Subject Matter
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and filed the terminal disclaimer.
Conclusion
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/IDRISS N ALROBAYE/ Supervisory Patent Examiner, Art Unit 2181
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