DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1, 13 and 18 are objected to because of the following informalities: The acronyms “NVMe” and “NVMe-oF” must be spelled out on first use in each independent claim (e.g., “Non-Volatile Memory Express (NVMe)” and “NVMe over Fabrics (NVMe-oF)”). Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11588261 and claims 1-20 of U.S. Patent No. 11018444. Although the claims at issue are not identical, they are not patentably distinct from each other because the processors, the memory or storage drives, inputs/outputs , the controller are disclosed as operating claimed and features are slightly different.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 and 9-20 are rejected under 35 U.S.C. 103 as being unpatentable over McKnight US 20170300445 A1.
Regarding claim 1, McKnight discloses a device comprising:; a processor (102 or see paragraphs 0090-0091); and a memory drive (112, 130, NVME, NAS or see paragraphs 0010) connected to the processor, wherein the device operates in a first operating mode or a second operating mode based on a first instruction (see paragraph 0091), and wherein, in the second operating mode, the memory drive selects a second non-zero operating speed from among two or more non-zero operating speeds available in the second operating mode based on a second instruction (see paragraphs 0042, 0073);
wherein the second operating mode comprises a NVMe over fabrics (NVMe-oF) mode. McKnight discloses a storage system featuring a processor and a memory drive (NVMe, SSD). The reference explicitly describes a motherboard arranged to operate in “any one of a plurality of protocol modes” based on selected “protocol bridge modules.” McKnight further teaches selecting non-zero operating speeds based on instructions (see paragraph 0042).
While McKnight may not explicitly use the term “NVMe-oF,” it discloses a system optimized for “multiple configurations of storage protocols” including NVMe and NAS. NVMe-oF is a well-known industry standard that extends NVMe commands over network fabrics. The PCB lengths are a mere change in size within the level of ordinary skill in art. Implementing a standard protocol like NVMe-oF on a device capable of NVMe and Network (NAS operations is an obvious design choice in order to meet the system specification and requirement. Note that NVMe-oF is a standard configuration for the type of high-speed (10G or greater) memory drive operations. Therefore, configurating hardware to run standard “over fabrics” protocol would have been an obvious modification to a person of ordinary skill in the art to achieve efficient data transfer.
Regarding claim 2, McKnight discloses a printed circuit board (PCB: 100, 200, 108, or see abstract or paragraph 0090), wherein: the memory drive is connected at a first side of the PCB via a connector; and the processor (102) is mounted on the PCB at a second side of the PCB.
Regarding claim 3, McKnight discloses: the processor comprises a field programmable gate array (FPGA(see paragraph 0091); the memory drive comprises a first solid state drive (SSD: see paragraphs 0015, 0046) and a second SSD; the connector comprises a first SSD connector and a second SSD connector; and the first SSD is connected to the PCB at the first side of the PCB via the first SSD connector and the second SSD is connected to the PCB at the first side of the PCB via the second SSD connector (see paragraphs 0015, 0038).
Regarding claim 4, McKnight discloses: the connector is electrically connected to the memory drive (112, 130, NVME, NAS or see paragraphs 0010) at a first side of the memory drive; and the connector is attached to the PCB at the first side of the PCB and is perpendicular to the first side of the PCB.
Regarding claim 5, McKnight discloses: a structural support between the second side of the PCB and a second side of the memory drive (112, 130, NVME, NAS or see paragraphs 0010).
Regarding claims 6 and 16, McKnight discloses: a length of the memory drive is of 3.5” and a length of the PCB, but fails to explicitly disclose the length of the board being about 110 and 142 mm or the length of the PCB being equal to or greater than a length of the memory drive or the length of the PCB is equal to or longer than a length of the processor, wherein the length of the processor is about 80 mm or the two or more non-zero operating speeds of the memory drive are two or more operating speeds at or greater than 10G, such a modification would have involved a mere change in the size of the component, which is considered as a change of size of a component. A change in size of a component generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). It would have been obvious to one having ordinary skill in the art to have the length of the board being about 110 and 142 mm, or a length of the PCB is equal to or longer than a length of the processor, wherein the length of the processor is about 80 mm or the two or more non-zero operating speeds of the memory drive are two or more operating speeds at or greater than 10Gin order to meet the system specification and requirement.
Regarding claim 7, McKnight discloses a first side of the processor (102) is attached to the second side of the PCB, wherein the processor is electrically connected to the PCB (figs. 1-2).
Regarding claims 9-11, 17, 20, McKnight discloses: the aforementioned limitations, but fails the length of the PCB being equal to or greater than a length of the memory drive or the length of the PCB is equal to or longer than a length of the processor, wherein the length of the processor is about 80 mm or the two or more non-zero operating speeds of the memory drive are two or more operating speeds at or greater than 10G, such a modification would have involved a mere change in the size of the component. A change in size of a component is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). It would have been obvious to one having ordinary skill in the art to be longer than a length of the processor, wherein the length of the processor is about 80 mm or the two or more non-zero operating speeds of the memory drive are two or more operating speeds at or greater than 10G in order to meet the system specification and requirement.
Regarding claim 12, McKnight discloses the first instruction is received from a mid-plane (see abstract), wherein the first instruction is controlled by two general-purpose input/output (GPIO) pins controlled by a baseboard management controller (BMC) of a switch or a local central processing unit (CPU) of a motherboard, or one or more internal registers associated with the processor (see paragraphs 0013, 0073.
Regarding claim 13, McKnight discloses a first interface layer; a memory drive (112, 130, NVME, NAS or see paragraphs 0010) attached to the first interface layer at a first side of the memory drive; a processor (102) connected to the memory drive; and a second interface layer attached to the processor (102) at a second side of the processor; and wherein the system operates in a first operating mode or a second operating mode based on a first instruction, wherein in the second operating mode, the system selects a first non-zero operating speed from among two or more non-zero operating speeds available in the second operating mode based on a second instruction, and wherein the first interface layer and the second interface layer are configured to transfer heat generated by the memory drive and the processor (102) to outside. The amended claim language of the operating modes is rejected for the same reasons set forth above in claim 1.
Regarding claim 14, McKnight discloses a printed circuit board (PCB) connected to the memory drive at a first side of the PCB via a connector, wherein the processor is mounted on the PCB at a second side of the PCB and a first side of the processor is attached to the PCB, wherein the connector is perpendicular to the first side of the PCB (see paragraphs 0015, 0038).
Regarding claim 15, McKnight discloses a structural support between the second side of the PCB and a second side of the memory drive (see paragraphs 0015, 0038).
Regarding claim 18, McKnight discloses a processor (102) and a memory drive (112, 130, NVME, NAS or see paragraphs 0010) connected to the processor, the method comprising: selecting, by the device, a first operating mode or a second operating mode based on a first instruction; and in the second operating mode, selecting, by the device, a second non-zero operating speed from among two or more non-zero operating speeds available in the second operating mode based on a second instruction (see paragraphs 0091 0092). The amended claim language of the operating modes is rejected for the same reasons set forth above in claim 1.
Regarding claim 19, McKnight discloses connecting the memory drive (112, 130, NVME, NAS or see paragraphs 0010) at a first side of a printed circuit board (PCB) via a connector; mounting the processor on a second side of the PCB (see paragraphs 0015, 0038). , wherein a first side of the processor (102) is attached to the PCB; and incorporating a structural support between the second side of the PCB and a second side of the memory drive, 25 wherein the connector is perpendicular to the first side of the PCB (see paragraphs 0015, 0038).
Response to Arguments
Applicant's arguments filed on 6/5/2026 have been fully considered but they are not persuasive. The Applicant argues that McKnight is “completely silent” regarding a drive configured to operate in both an NVMe mode and an NVMe over fabrics (NVMe-oF) mode, and silent on selecting speeds within said NVMe-oF mode.
While McKnight may not explicitly use the term “NVMe-oF,” it discloses a system optimized for “multiple configurations of storage protocols” including commands over network fabrics. To a person of ordinary skill in the art, implementing NVMe-oF in a system already designed for multi-protocol NVMe and network storage (NAS) would be a routine optimization to enable high-performance remote access. The examiner maintains that selecting a specific protocol (NVMe-oF for a device already capable of protocol switching is the “application of a known configuration to a known device” to achieve a predictable result. Furthermore, McKnight already discloses selecting from “two or more non-zero operating speeds” based on an instruction. Applying this pre-existing speed-selection capability to an NVMe-oF protocol mode is a “mere change in the system specification” to meet performance requirement, which is within the level of ordinary skill. It would have been obvious to person having ordinary skill in the art before the effective filing date of the invention to configure the multi-protocol device of McKnight to utilize the NVMe-oF standard to facilitate high-speed data transfer over a fabric, as this represents a standard industry implementation for the hardware described.
Allowable Subject Matter
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and filed the terminal disclaimer.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IDRISS N ALROBAYE whose telephone number is (571)270-1023. The examiner can normally be reached Mon-Fri, 8am-4:30pm.
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/IDRISS N ALROBAYE/ Supervisory Patent Examiner, Art Unit 2181
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