Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for Examination.
DETAILED ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 3, 6, 7, 8-19 is/are rejected under 35 U.S.C. 102(a) (1) as being anticipated by Bernat et.al. (U.S Patent Application Publication 2020/0073464; hereinafter “Bernat”].
Regarding claims 1, 10, 17, Bernat discloses , An accelerator apparatus, comprising:
an interface to receive service requests from at least one processing core;
[“,, the compute sled 800 may rely on other sleds, such as acceleration sleds and/or storage sleds, to perform such compute tasks…”, 0049; 0054 .. the system 1510 includes an orchestrator server 1520, which may be embodied as a managed node comprising a compute device (e.g., a processor 820 on a compute sled 800) executing management software (e.g., a cloud operating environment, such as OpenStack) that is communicatively coupled to multiple sleds 400 including a large number of compute sleds 1530 .., accelerator sleds 1550 ..”, 0075 ; a compute sled 1614 in communication with each other and with a pod manager 1616 (similar to the orchestrator server 1520; “ As indicated in block 1806, the accelerator sled 1610 (e.g., the adaptive power management logic unit 1640) may receive the request from the pod manager 1616 (e.g., via the management controller interface logic unit 1700). In receiving the request, and as indicated in block 1808, the accelerator sled 1610 may receive the kernel to be executed on the accelerator sled 1610 (e.g., in one of the slots 1630, 1632, 1634, 1636 of the accelerator devices 1620, 1622)”, 0084; Fig.17]
and
coprocessor circuitry coupled to the interface and, the coprocessor circuitry comprised of a plurality of coprocessor slices[“ The accelerator circuits 1020 may be embodied as any type of processor, co-processor, compute circuit, or other device capable of performing compute or processing operations..”, 0060 ; “..the accelerator sled 1610 (e.g., the adaptive power management logic unit 1640), in operation, may perform a method for providing adaptive power management for the accelerator devices (e.g., the accelerator devices 1620, 1622) on the accelerator sled 1610. While the method 1800 is described as being perf..”, 0084; i.e the accelerator devices corresponds to the coprocessor circuitry) ], the coprocessor circuitry configured to:
detect a performance type for the at least one processing core [“the orchestrator server 1520 may identify trends in the resource utilization of the workload (e.g., the application 1532), such as by identifying phases of execution (e.g., time periods in which different operations, each having different resource utilizations characteristics, are performed) of the workload (e.g., the application 1532) .. .. the orchestrator server 1520 may determine which resource(s) should be used with which workloads based on the total latency associated with each potential resource available in the data center 100 (e.g., the latency associated with the performance of the resource itself in addition to the latency associated with the path through the network between the compute sled executing the workload and the sled 400 on which the resource is located). “, 0076;0075; 0079;Fig.16;( i.e. processor of compute sled); “the adaptive power management logic unit 1640 includes a management controller interface logic unit 1700, a prediction logic unit 1702, a power utilization limit logic unit 1704, and a power profile logic unit 1706.. profile data indicative of the performance (e.g., latency, operations per second, etc.) of the kernel as a function of the amount of power utilized by the underlying accelerator device, and service level agreement (SLA) data indicative of the target performance that is expected by the customer associated with the kernel (e.g., the expected latency, operations per second, etc.)..”, 0081; ”the accelerator sled 1610 may receive SLA data indicative of a target number of operations per second to be performed by the kernel. Additionally, or alternatively, and as indicated in block 1818, the accelerator sled 1610 may receive SLA data indicative of a target latency (e.g., a maximum amount of time that should be taken to complete a defined set of operations) to be satisfied. “, 0084; ( i.e. detecting the performance type based on type of workload/ application assigned to the orchestrator / processor with respect to the performance data ( profile , SLA data)];
operate the plurality of coprocessor slices in at least one of a plurality of power modes based on the performance type detected for the at least one processing core [ “
the accelerator sled 1610 includes an adaptive power management logic unit 1640 which may be embodied as any device or circuitry (e.g., reconfigurable circuitry, an application specific integrated circuit (ASIC), etc.) or software configured to set power utilization limits of each accelerator device 1620, 1622 on the accelerator sled 1610 to keep the total power utilization within a predefined budget for the accelerator sled 1610, to provide the appropriate amount of power to each accelerator device 1620, 1622 to enable each kernel 1660, 1662, 1664, 1666 to satisfy a corresponding target performance (e.g., defined in a corresponding SLA), and to selectively increase or decrease power utilization limits for each kernel based on predicted power utilization needs of the kernels (e.g., determined based on identified patterns of power utilization of the kernels 1660, 1662, 1664, 1666 (e.g., of the underlying accelerator devices 1620, 1622)).”, 0080; “..software configured to obtain, through a management interface (e.g., a baseboard management interface, the communication circuit 830, etc.), data indicative of the total power budget for the accelerator sled 1610 (e.g., 2 kilowatts), each kernel that is to be executed on the accelerator sled 1610, profile data indicative of the performance (e.g., latency, operations per second, etc.) of the kernel as a function of the amount of power utilized by the underlying accelerator device, and service level agreement (SLA) data indicative of the target performance that is expected by the customer associated with the kernel “, 0081-0082; “.. FIG. 19, in which the accelerator sled 1610 determines, as a function of a total power budget for the accelerator sled 1610, a power utilization limit (e.g., a maximum amount of power that may be utilized) for kernel(s) (e.g., by the corresponding accelerator device(s) executing the kernel(s)) on the accelerator sled 1610.”, 0084]
wherein: the at least one processing core comprises at least one host processing core [ “., a processor 820 on a compute sled 800”, 0075; 0079; Fig.16] :
the plurality of coprocessor slices comprise accelerator coprocessor slices[“the accelerator circuits 1020 may be embodied as any type of processor, co-processor,..”, 0060; 0084; Fig.16] : and
the plurality of power modes are to be dynamically configured based, at least in part, upon machine learning model data.[ “that is configured to determine the performance of the kernel at different power utilizations (e.g., by analyzing the sets of operations defined in the kernel, by simulating execution of the kernel using a model of an accelerator device, etc.). “, 0084; 0081; “the power utilization limit logic unit 1704 may be embodied as any device or circuitry (e.g., an integrated circuit, reconfigurable circuitry, a microcontroller, etc.) or software configured to set the power utilization limit of each accelerator device 1620, 1622 to ensure that the total power budget for the accelerator sled 1610 is not exceeded and to selectively increase or decrease the power utilization limit for each accelerator device 1620, 1622 (e.g., by increasing the frequency and/or voltage) to enable the corresponding kernel to satisfy the target performance specified in the SLA data (e.g., based on the profile data obtained by the management controller interface logic unit 1700 and based on predictions in power utilizations from the prediction logic unit 1702)…”, 0082 ; 0084(profile data) ; “For example, the accelerator sled 1610 (e.g., the adaptive power management logic unit 1640) may identify the performance target defined in the SLA data for the kernel and determine, from the profile data, the corresponding power utilization associated with that performance (e.g., 300 Watts for a 10 microsecond latency, etc.). The accelerator sled 1610 may (e.g., after one or more iterations of the method 1800) determine, as a function of a pattern of power utilization of each kernel, the power utilization limit for each kernel, as indicated in block 1834. In doing so, and as indicated in block 1836, the accelerator sled 1610 (e.g., the adaptive power management logic unit 1640) may determine a time period over which the power utilization of a present kernel (e.g., the kernel 1660) is predicted to change. Relatedly, the accelerator sled 1610 (e.g., the adaptive power management logic unit 1640) may determine whether one or more other kernels (e.g., the kernels 1662, 1664, 1666) executed on the accelerator sled 1610 are predicted to change their power utilization during that same time period, as indicated in block 1838.”, 0086; 0092; ( i.e configuring the power modes based on the profile data model)]
Regarding Claims 2, 11, 18, Bernat discloses , wherein the performance type includes at least one of a performance type and an efficiency type [0075-0076; 0079; 0084].
Regarding Claims 3, 12, 19, Bernat discloses, wherein the coprocessor circuitry is further configured to configure the plurality of power modes based on a policy [“service level agreement (SLA) data indicative of the target performance..”, 0081; 0082];.
Regarding Claims 13 , Bernat discloses , wherein the policy comprises setting all of the plurality of coprocessor slices to a power-managed mode[0081-0082; 0086;0088].
Regarding claims 6, 14, Bernat, wherein the policy comprises setting zero coprocessor slices to a power-managed mode to disable power-efficient operations[ “..determines whether to enable adaptive power management…”, 0084; 0086-0087]
Regarding Claim 7, Bernat discloses , wherein the coprocessor circuitry comprises a system on chip (SoC).[0060;0079].
Regarding Claim 8, Bernat discloses, the coprocessor circuitry comprises a field programmable gate array (FPGA) [ 0079; Fig.16].
Regarding Claims 9, 15, Bernat discloses , wherein the service requests are provided or received through application programming interface (API) function calls[ 0075; 0078; 0084 ; Fig.15, 16].
Regarding Claim 16, Bernat discloses wherein the API function calls define a preferred slice type or other parameter of coprocessor functionality[0084;0086-0088]
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 5 , 20 are rejected under 35 U.S.C. 103 as being unpatentable over Bernat.
Regarding Claims 4, 20, Bernat discloses , wherein the policy comprises setting at least a subset of the plurality of coprocessor slices to a power-managed mode [0082; “the accelerator sled 1610 (e.g., the adaptive power management logic unit 1640) may adjust a voltage and/or a frequency of one or more of the accelerator devices 1620, 1622 to selectively increase or decrease the power utilization limit of the accelerator devices 1620, 1622, as indicated in blocks 1850 and 1852. For example, the accelerator sled 1610 may increase the voltage and/or frequency, and thereby increase the power utilization limit of, the accelerator device 1620 while concurrently decreasing the voltage and/or frequency, and thereby decreasing the power utilization limit of, the accelerator device 1622 to keep the total power utilization of the accelerator devices 1620, 1622 within the total power budget for the accelerator sled 1610”, 0088.
However, Bernat does not expressly disclose the power-managed mode in which a corresponding coprocessor slice is clock gated.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Bernat to clock gate a coprocessor slice as Bernat teaches, “ adjusting the voltage and/ or frequency of the respective accelerator devices to keep the total power utilization of within the power budget and to satisfy the target performance specified in the service level agreement (SLA) data [0082; 0088]
Regarding Claim 5, Bernat discloses , wherein the policy comprises setting all of the plurality of coprocessor slices to a power-managed mode discloses , 0081-0082; 0086;0088].
Response to Arguments
Applicant’s arguments with respect to newly amended limitations for claim(s) 1, 10, 17 have been considered but are moot because the arguments do not apply to Bernat reference being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Subramanian et al., U.S Patent Application Publication 2019/0094926, teaches A computing device, a method and a system to control power. The computing device includes memory storing instructions; and processing circuitry configured to perform the instructions. The processing circuitry is to receive respective requests from respective ones of the plurality of nodes, the requests addressed to a plurality of corresponding accelerators, each of the respective requests including information on a kernel to be executed by a corresponding accelerator, on the corresponding accelerator, and on a performance target for execution of the kernel. The processing circuitry is further too, based on the information in said each of the respective requests, control a power supply to the corresponding accelerator.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GAYATHRI SAMPATH whose telephone number is (571)272-5489. The examiner can normally be reached on Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached on 5712701640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/GAYATHRI SAMPATH/ Examiner, Art Unit 2176
/JAWEED A ABBASZADEH/ Supervisory Patent Examiner, Art Unit 2176
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