Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for Examination.
DETAILED ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 3, 6, 7, 9-19 is/are rejected under 35 U.S.C. 102(a) (1) as being anticipated by Herdrich et.al. (U.S Patent Application Publication 2013/0262902; hereinafter “Herdrich”].
Regarding claims 1, 10, 17, Herdrich discloses , An accelerator apparatus, comprising:
an interface to receive service requests from at least one processing core; and [FIG. 1, processor 100 may be a heterogeneous processor having a number of large cores, small cores and accelerators..”, 0016; “multiple accelerators 140a-140c also may be coupled to interconnect 130…the accelerators may include media processors such as audio and/or video processors, cryptographic processors, fixed function units and so forth. .”, 0020; “method 300 may be implemented in part by interconnect logic such as power control logic within an interconnect structure that can receive interrupts, e.g., from accelerators coupled to the interconnect structure and forward the interrupts to a selected location.”, 0029;”… Although the cores may not be active, other agents within a processor or SoC such as one or more accelerators may be performing tasks. At block 320, an interrupt may be received from such an accelerator. This interrupt may be sent when the accelerator has completed a task, encountered an error, or when the accelerator needs additional data or other processing is to be performed by another component such as a given core…”, 0030; Fig.1( i.e.. The interconnect / PCU receiving service requests from an accelerator) ]; and
coprocessor circuitry coupled to the interface and, the coprocessor circuitry comprised of a plurality of coprocessor slices, the coprocessor circuitry configured to: [0016-0017;”both large cores 110 and small cores 120 may be coupled to an interconnect 130”, 0019; 0029; ( i.e . The large and small cores comprises the pluralities of coprocessor slices)] .
detect a performance type for the at least one processing core [“When the accelerator runs out of data, it directs a wake signal to request additional data that can be from the small core, which wakes and determines that this simple data move operation can be accomplished without waking the large core, thus saving power. .. instead detects that a complex vector operation (like a 256-bit AVX instruction) exists in the instruction stream, the large core may be awakened to handle the complex instruction (and other instructions in this stream) to enable reduced latency. ..”, 0028; “.. many operations to be performed upon waking from a low power state can be offloaded to a simpler, more power-efficient core to avoid waking a larger more powerful core in heterogeneous environments (where many cores of various sizes are included in a system for performance or power efficiency reasons)”, 0036; . “an accelerator can send a hint to the PCU or other management agent with an interrupt to indicate that the requested operation is a relatively simple operation such that it can be handled effectively in the small core. This accelerator-provided hint may be used by the PCU to automatically direct incoming interrupts to the small core for handling. “, 0053; ( i.e. detecting the performance type based on the type of operation / instruction to be executed by the large or small cores) ] and
operate the plurality of coprocessor slices in at least one of a plurality of power modes based on the performance type detected for the at least one processing core[ 0028;“..That is, the logic may be programmed to always send a resume signal to the small core (or a selected one of multiple such small cores, depending upon system implementation) when both large and small cores are in a low power state. ... Note that certain types of filtering or caching mechanisms may be added to block 330 such that certain interrupt sources are always routed to one core or another, as desired to balance performance and power.”, 0030; “ if it is determined that the requested operation can be handled in the small core, control passes to block 350 where the operation is thus performed in the small core”, 0034; “If instead it is determined at diamond 340 that the small core cannot handle the requested operation, e.g., if the operation is a relatively complex operation that the small core is not configured to handle, control instead passes to block 360. There, a wakeup signal can be sent, e.g., directly from the small core to the large core, to cause the large core to be powered up”, 0035; ( i.e .waking/ enabling power to large or small cores based on the type of the instruction/ operation received to balance power and performance.) ].
Regarding Claims 2, 11, 18, Herdrich discloses , wherein the performance type includes at least one of a performance type and an efficiency type [ “ By steering interrupts and other core waking events to the smaller cores instead of the larger cores, the smaller cores may run longer and wake more often, but this is still more power efficient than waking a large core to perform a trivial task such as data moving. Note that as described below for some operations, the large core may be powered on for execution, as for instance smaller cores might not support vector operations (e.g., AVX operations), complex addressing modes or floating point (FP) operations “, 0023; 0036].
Regarding Claims 3, 12, 19, Herdrich discloses, wherein the coprocessor circuitry is further configured to configure the plurality of power modes based on a policy [0026-0037; “PCU 450 may include various logic to enable power efficient operation in accordance with an embodiment of the present invention…”0041-0044], the policy being determined based at least on a count of services executing on at least two different types of processing cores[0028; 0030; 0032-0033];.
Regarding Claims 13 Herdrich discloses , wherein the policy comprises setting all of the plurality of coprocessor slices to a power-managed mode[0028; 0030; 0056].
Regarding claims 6, 14, Herdrich,, wherein the policy comprises setting zero coprocessor slices to a power-managed mode to disable power-efficient operations[ “ method 300 may begin by placing both large and small cores in a sleep state (block 310). That is, it is assumed that no active operations are being performed in the cores. As such, they can be placed in a selected low power state to reduce power consumption. Although the cores may not be active, other agents within a processor or SoC such as one or more accelerators may be performing tasks”, 0030].
Regarding Claim 7, Herdrich discloses , wherein the coprocessor circuitry comprises a system on chip (SoC).[0014;0039; Fig.6 ].
Regarding Claims 9, 15, Herdrich discloses , wherein the service requests are provided or received through application programming interface (API) function calls[ 0040;0045].
Regarding Claim 16, Herdrich discloses wherein the API function calls define a preferred slice type or other parameter of coprocessor functionality[0045].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 5, 8, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Herdrich
Regarding Claims 4, 20, Herdrich discloses , wherein the policy comprises setting at least a subset of the plurality of coprocessor slices to a power-managed mode [ 0028; 0036; ( i.e determining to wake the power efficient small cores or the performance efficient large cores based on the instruction type),
However, Herdrich does not expressly disclose wherein the power-managed mode in which a corresponding coprocessor slice is clock gated.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Herdrich to clock gate a coprocessor slice as Herdrich teaches, “depending on an expected workload of the processor, the OS may select a non-idle state, e.g., OS C0 or one of multiple idle states, e.g., OS C-states C1-C3. Each of these idle states can be mapped to a corresponding hardware low power state that is under control of processor hardware..”, 0026; “directs a wake signal to request additional data that can be from the small core, which wakes and determines that this simple data move operation can be accomplished without waking the large core, thus saving power. If a timer interrupt arrives and the small core wakes up and instead detects that a complex vector operation (like a 256-bit AVX instruction) exists in the instruction stream, the large core may be awakened to handle the complex instruction”, 0028; , i.e providing plurality of power saving states according to the workload to achieve greater power savings and balance power and performance,[ 0023; 0030].
Regarding Claim 5 Herdrich discloses , wherein the policy comprises setting all of the plurality of coprocessor slices to a power-managed mode[0028; 0030; 0056].
Regarding Claim 8, Herdrich discloses , the coprocessor circuitry [ 0014, 0017; 0056; (i.e plurality of heterogeneous processor/ core types)].
Herdrich does not expressly disclose the coprocessor circuitry comprises a field programmable gate array (FPGA).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Herdrich to implement a field programmable gate array (FPGA), since it has been held to be within the general skill of a worker in the art to select the component on the basis of its suitability for the intended use as a matter of design choice.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Parks et al., U.S Patent Application Publication 2008/0184042, teaches An apparatus and method provide power to perform functions on a computing device. The apparatus contains multiple processors that may operate at different power levels to consume different amounts of power and perform different functions. For example, one processor may be a low power processor that may control or operate at least one peripheral device to perform a low capacity function. Control may also switch from the low power processor to a high capacity processor. In one example, the high capacity processor controls the low power processor and further controls the at least one peripheral device through the lower power processor.
Kumar et al., U.S Patent Application Publication 2015/0198992, teaches An apparatus is disclosed for managing operational modes of a processor. The apparatus may include the processor which may include a coprocessor, an instruction queue, and a monitoring circuit for detecting instructions for the coprocessor in the instruction queue. The monitoring circuit may detect when the instruction queue holds no instructions for the coprocessor. If the instruction queue holds no instructions for the coprocessor, the coprocessor may be placed into a mode in which the coprocessor consumes less power. The monitoring circuit may detect an instruction for the coprocessor in the instruction queue. In response to the instruction for the coprocessor, the coprocessor may be placed into a mode in which the coprocessor may execute the instruction.
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/GAYATHRI SAMPATH/ Examiner, Art Unit 2176
/JAWEED A ABBASZADEH/ Supervisory Patent Examiner, Art Unit 2176