DETAILED ACTION
Claims 1-5, 7, and 9-21 are presented for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Newly submitted claim 21 directed to an invention that is independent or distinct from the invention originally claimed for the following reasons: the inventions require a different field of search (e.g., searching different classes/subclasses or electronic resources, or employing different search strategies or search queries).
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claim 21 is withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-5, 9-10, 12-17, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Arunachalam (US Pat No. 11,188,437) in view of Paterson et al. (US PG Pub No. 2018/0309565 A1).
Regarding claim 1, Arunachalam teaches a system comprising:
a processing device, coupled to a work execution agent (Abstract), the processing device configured to:
determine a first time for executing an operation associated with a work execution agent (col 9 lines 29-39, wherein an execution time window is determined for a requested task is determined);
receive a latency measurement associated with the work execution agent, wherein the latency measurement is calculated based on executing a previous operation associated with the work execution agent at the device (col 9 lines 14-27, wherein historical data including the latency associated with a specified host computing node is used to determine the estimated time for completion of a requested task).
Arunachalam does not teach modify the first time to a second time for executing the operation based on the latency measurement, wherein the first time is modified to the second time by subtracting the latency measurement from the first time to compensate for a latency of executing the operation, and wherein modifying the first time to the second time causes the work execution agent to execute the operation at the second time.
Paterson teaches using a latency measurement to determine an offset value and using the offset value and using software scheduling the tasks on the respective processors to refer to the offset value in order to adjust scheduling times ([0065]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the first time to a second time for executing the operation based on the latency measurement, wherein the first time is modified to the second time by subtracting the latency measurement from the first time to compensate for a latency of executing the operation. One would be motivated by the desire to control any process which relies on a common view of time as taught by Paterson.
Regarding claim 3, Arunachalam teaches wherein the processing device is to: transmit a request for the latency measurement associated with the work execution agent of the plurality of work execution agents (col 9 lines 14-27, wherein it is inherent that a request for latency measurement is transmitted).
Regarding claim 4, Arunachalam teaches wherein the processing device is a host system, a software component, or a remote node (Fig 1; Fig 3).
Regarding claim 5, Paterson teaches wherein the processing device is to: transmit a request to perform the operation at the second time responsive to modifying the first time to the second time ([0065]).
Regarding claim 9, Arunachalam does not teach wherein the latency measurement is at least one of a maximum latency, minimum latency, or average latency associated with the work execution agent.
It is old and well known to express any monitored metric as a maximum, minimum or average value. Therefore, it would have been obvious that the latency measurement is at least one of a maximum latency, minimum latency, or average latency. A patent claim can be proved obvious merely by showing that the combination of elements was obvious to try. When there is a design need or market pressure to solve a problem and there are a finite number of identified, predictable solutions, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely the product is not of innovation but of ordinary skill and common sense. KSR v. Teleflex
Regarding claim 10, Arunachalam teaches wherein the latency measurement is associated with a type of operation or a location of the operation (col 9 lines 29-39).
Regarding claims 12-16, they are the device claims of claims 1 and 9-10 above. Therefore, they are rejected for the same reasons as claims 1 and 9-10 above.
Regarding claim 17, Arunachalam teaches a system comprising: a first device coupled to a link (Fig 1), the first device to:
transmit a request for a latency measurement associated with a work execution agent of a plurality of work execution agent (col 9 lines 14-27, wherein it is inherent that a request for latency measurement is transmitted); and
a second device coupled to the link (Fig 1), the second device to: receive the request for the latency measurement; determine the latency measurement, wherein the latency measurement is calculated based on executing a first operation associated with the work execution agent at the second device (col 9 lines 14-27, wherein historical data including the latency associated with a specified host computing node is used to determine the estimated time for completion of a requested task); and
transmit the latency measurement associated with the work execution agent responsive to determining the latency measurement (col 9 lines 14-27, wherein it is inherent that the latency measurement is communicated);
Arunachalam does not teach wherein the first device is to modify a time for executing a second operation responsive to receiving the latency measurement, wherein the modified time is determined by subtracting the latency measurement from an original time for executing the second operation to compensate for a latency of executing the second operation.
Paterson teaches using a latency measurement to determine an offset value and using the offset value and using software scheduling the tasks on the respective processors to refer to the offset value in order to adjust scheduling times ([0065]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the first time to a second time for executing the operation based on the latency measurement, wherein the first time is modified to the second time by subtracting the latency measurement from the first time to compensate for a latency of executing the operation. One would be motivated by the desire to control any process which relies on a common view of time as taught by Paterson.
Regarding claim 20, Paterson teaches wherein the second device is to: execute the second operation at the modified time responsive to initiating the second operation at the modified time ([0065]).
Claim(s) 2, 7, and 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Arunachalam (US Pat No. 11,188,437) in view of Paterson et al. (US PG Pub No. 2018/0309565 A1), further in view of Dunsmore et al. (US PG Pub No. 2022/0061059 A1).
Regarding claim 2, Arunachalam and Paterson do not teach wherein the processing device is to: store the second time in a work descriptor of the work execution agent, the work descriptor corresponding to executing the operation.
Dunsmore teaches storing the executing time of a command by an agent as metadata ([0032]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to store the second time in a work descriptor of the work execution agent, the work descriptor corresponding to executing the operation. One would be motivated by the desire to store metric data as taught by Dunsmore.
Regarding claim 7, Dunsmore teaches wherein the device is to: read a work descriptor of the work execution agent; schedule to execute the operation at the second time responsive to reading the work descriptor; and execute the operation at the second time responsive to scheduling the operation ([0032]).
Regarding claims 18-19, they are the system claims of claims 2 and 7 above. Therefore, they are rejected for the same reasons as claims 2 and 7 above.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Arunachalam (US Pat No. 11,188,437) in view of Paterson et al. (US PG Pub No. 2018/0309565 A1), further in view of White et al. (US PG Pub No. 2022/0318040 A1).
Regarding claim 11, Arunachalam and Paterson do not teach wherein the latency measurement is associated with two or more memory regions and includes the latency measurement associated with each region, and wherein the processing device is to modify from the first time to the second time responsive to receiving the latency measurement associated with each region.
White teaches that computer systems are typically composed of tiered memory systems comprising two or more regions of memory with different latency characteristics ([0002]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention that the latency measurement is associated with two or more memory regions and includes the latency measurement associated with each region. One would be motivated by the desire to account for differences in memory characteristics as taught by White.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-5, 7 and 9-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC C WAI whose telephone number is (571)270-1012. The examiner can normally be reached Monday - Friday 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Aimee Li can be reached at (571) 272-4169. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Eric C Wai/Primary Examiner, Art Unit 2195