DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claims 1-20 are rejected in the Instant Application. Information Disclosure Statement The information disclosure statement(s) (IDS) submitted on 2/21/23 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered if signed and initialed by the Examiner. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.— The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112(d): (d) REFERENCE IN DEPENDENT FORMS.— Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. Claim s 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. The term " copy circuitry " and “frequency tuned processor” in claim s 1, 8, 14 are relative term s which renders the claim indefinite. The term s " copy circuitry " and “frequency tuned processor” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Examiner interprets the copy circuitry to be circuitry attached to memory and frequency tuned processor to be a modified processor . The above cited rejections are merely exemplary. The Applicant(s) are respectfully requested to correct all similar errors. Claims not specifically mentioned are rejected by virtue of their dependency. Claim Rejections - 35 USC § 103 A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim s 1-6, 8-20 are rejected under 35 U.S.C. 103 as being unpatentable over DiFerdinando ( US20220321499A1 ) hereinafter DiFerdinando in view of Nguyen et al. ( US20200387409A1) hereinafter Nguyen . Regarding claims 1, 8, 14. DiFerdinando least one non-transitory computer-readable medium comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to (¶0044 see microprocessors or microcontrollers, DSPs, graphics processor (GPU), on chip memory, hardware accelerators, peripheral device functionality such as Ethernet and PCIE controllers, and the like, for implementation as a system ) : execute an ingress service to select at least one service to process at least one received p acket, wherein the ingress service is executed on a frequency tuned processor of the one or more processors, accessing a forwarding table from high bandwidth memory (HBM) (¶0008 the forwarding engine receives a network address identifier in a data packet at an I/O port for transmission to a destination I/O port, and determines an internal port number for routing by the switch engine out from the switch flow module ¶0050 see data packets in the I/O SFM ingress FIFO queue exceeds a predetermined threshold, the I/O SFM sequencer raises a request to establish connection with another switch flow module for transferring data packets from the FIFO queue into high bandwidth memory via the another switch flow module upon grant of the connection request ) , and utilizing data copy circuitry to copy portions of received packets to memory accessible to the s elected at least one service (¶0040 see Each silicon switching element contains therein a forwarding and routing engine for routing data packets according to a packet address header such as a MAC header via the printed circuit backplane of point-to-point direct electrical interconnections from a source peripheral device connected to the network switch, to a destination peripheral device. The fo rwarding and routing is performed within the transmitting ASIC or FPGA (or SoC) according to a lookup table containing routing information stored thereon [note: the routing engine and forwarding engine inherently comprise memory see ¶0044 see components including one or more processor cores, microprocessors or microcontrollers, DSPs, graphics processor (GPU), on chip memory , hardware accelerators, peripheral device functionality such as Ethernet and PCIE controllers, and the like, for implementation as a system on a chip (SoC) in connection with communication via the direct point-to-point electrical interconnect structure ] ) DiFerdinando does not explicitly teach frequency tuned processor Nguyen however in the same field of computer networking teaches frequency tuned processors (¶0026 see instruct all of the processors of the cluster to set their core and un-core operating frequencies to the same respective frequencies as the lead processor; and for this purpose, the appropriate slope values may be used to adjust, or tune , the core and un-core operating frequencies of each processor to the respective core and un-core operating frequencies of the lead processor ) Accordingly, it would have been obvious to one of ordinary skill in the art of computer networking at the effective filing date of the claimed invention given the processors of DiFerdinando and the teachings of Nguyen for utilizing tuned processors to combine the teachings such that DiFerdinando utilizes tuned processors . One of ordinary skill in the art would recognize that the results of the combination are predictable because each element in the combination is merely performing the same function it would perform separately. One would be motivated to combine these teachings because doing so will be beneficial for the processors of the server to have similar performances, as threads that finish tasks slower may add to the total duration for finishing the jo (¶000 2 Nguyen ) . Further regarding claim 8 : DiFerdinando further teaches a method ( DiFerdinando ¶0194 see embodiments are provided by way of example only, and other embodiments for implementing the systems and method ) Further regarding claim 14 : DiFerdinando further teaches a system comprising: at least one memory, wherein the at least one memory comprises high bandwidth memory (HBM) ( DiFerdinando ¶0050 see flow module for transferring data packets from the FIFO queue into high bandwidth memory ) and at least one processor, wherein the at least one processor is to access instructions from the at least one memory that cause the at least one processor ( DiFerdinando ¶0053 see plane processor to accept routing information and LAN topology according to updates in the routing table as an alternative to an Openflow routing, wherein the sequencer module interfaces with a control plane processor ) Regarding claims 2 , 9, 15 . The already combined references teach the computer-readable medium of claim 1, wherein the ingress service performs load balancing of received packets among the at least one service ( DiFerdinando ¶0088 see Servers may be can be connected to two different leaf 110′ or TOR 101 switches in order to have redundancy and load balancing capability ) Regarding claims 3 , 10, 16 . The already combined references teach the computer-readable medium of claim 1, wherein the ingress service identifies an Internet Protocol (IP) address of services to process the received packet ( DiFerdinando ¶0100 see Each data packet delivered to and detected by an external I/O port of a semiconductor crossbar switch element includes a header comprising an identifier of the source peripheral processing device (e.g., an Internet Protocol (IP) address or a medium access control (MAC) address of the peripheral processing device), and an identifier of the destination peripheral processing device (e.g., an IP address or a MAC address of the peripheral processing device) ) . Regarding claims 4 , 11, 17 . The already combined references teach the computer-readable m e dium of claim 1, wherein the ingress service is to access the forwarding table to determine a destination service to process the received packet ( DiFerdinando ¶0008 see forwarding engine; wherein the forwarding engine receives a network address identifier in a data packet at an I/O port for transmission to a destination I/O port, and determines an internal port number for routing by the switch engine out from the switch flow module , according to a router table which maps internal port numbers of the switch flow module with destination I/O ports ) . Regarding claim s 5 , 12, 18 . The already combined references teach the computer-readable medium of claim 1, DiFerdinando does not explicitly teach wherein the frequency tuned processor of t he one or more processors comprises a core operating at a higher frequency Nguyen however in the same field of computer networking teaches wherein the frequency tuned processor of t he one or more processors comprises a core operating at a higher frequency (¶0046 see the two core frequencies 306 and 308 of the two processors 132 are unequal, with the core frequency 306 being at 3200 Mega Hertz (MHz) and being higher than the core frequency 308 ) Accordingly, it would have been obvious to one of ordinary skill in the art of computer networking at the effective filing date of the claimed invention given the processors of DiFerdinando and the teachings of Nguyen for utilizing tuned processors to combine the teachings such that DiFerdinando utilizes tuned processors . One of ordinary skill in the art would recognize that the results of the combination are predictable because each element in the combination is merely performing the same function it would perform separately. One would be motivated to combine these teachings because doing so will be beneficial for the processors of the server to have similar performances, as threads that finish tasks slower may add to the total duration for finishing the jo (¶0002 Nguyen) . Regarding claims 6 , 13, 19 . The already combined references teach the computer-readable medium of claim 1, wherein the ingress service is to utilize the data copy circuitry to copy the received packet to memory accessible to the selected at least one s ervice to process the received packet ( DiFerdinando ¶0165 see DDR Engine action of transferring packets to and from the high bandwidth memory consists of Layer-2 DDR SFM which accumulates packets [copy packets] from several Layer-1 DDR SFM streams (Hyper Cylinder) sending packets in a FIFO fashion and optionally under control of the QOS setting in the packet via the singular high-bandwidth memory data bu ) . Regarding claim 20. The already combined references teach the system of claim 14, wherein the high bandwidth memory (HBM) comprises a cache device ( DiFerdinando ¶0165 see DDR Engine action of transferring packets to and from the high bandwidth memory consists of Layer-2 DDR SFM which accumulates packets from several Layer-1 DDR SFM streams (Hyper Cylinder) sending packets in a FIFO fashion and optionally under control of the QOS setting in the packet via the singular high-bandwidth memory data bu s [well understood that stacked DRAM utilizes high speed cache]) Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over DiFerdinando -Nguyen further in view of Holt et al. ( US20230251910A1 ) hereinafter Holt . Regarding claim 7. DiFerdinando -Nguyen teach the computer-readable medium of claim 1, DiFerdinando -Nguyen does not explicitly teach wherein the forwarding table comprises a Kubernetes IP table and the ingress service is to operate in a manner consistent with K ubernetes Holt however in the same field of computer networking teaches wherein the forwarding table comprises a Kubernetes IP table (¶0033 see a user of the client computing device 102 may set up or stand up a KUBERNETES computing cluster 202 using the visual cluster deployment and operation application 106. The user may deploy software to the computing cluster 204, create/update an ingress route [table] to the computing cluster 206, create/update a ConfigMap 208 ) and the ingress service is to operate in a manner consistent with K ubernetes (¶0046 see the method 300 may include receiving a request to set up an ingress route element comprising a Kubernetes Ingress Route that is attached to the at least one of the git element and the container element ) Accordingly, it would have been obvious to one of ordinary skill in the art of computer networking at the effective filing date of the claimed invention given the routing DiFerdinando -Nguyen and the teachings of Holt for utilizing Kubernetes routing to combine the teachings such that DiFerdinando utilizes Kubernetes routing . One of ordinary skill in the art would recognize that the results of the combination are predictable because each element in the combination is merely performing the same function it would perform separately. One would be motivated to combine these teachings because doing so will allow for visual cluster deployment and management (¶0004 Holt) . Conclusion References are cited not only for their quoted language but for all that they teach. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Atta Khan whose telephone number is 571-270-7364 . The examiner can normally be reached on M-F 09:00-6:00 . If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Vivek Srivastava FILLIN "SPE Name?" \* MERGEFORMAT can be reached on (571) 272-7304 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ATTA KHAN/ Examiner, Art Unit 2449