Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
A notice to file missing parts was filed on 03/21/2023, with one of the listed missing parts being the inventor’s oath or declaration. The Examiner respectfully notes that no inventor’s oath or declaration has yet been filed. The Examiner respectfully reminds the applicant to file the inventor’s oath or declaration.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in GB on 02/17/2022. It is noted, however, that applicant has not filed a certified copy of the 2202126.5 or 2202128.1 application as required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/17/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 1-3, 10-14, and 16-18 are objected to because of the following informalities:
Claims 1-3, and 10-11, claims 12-14, and claim 18 use the terms “floating point”, and “floating-point” interchangeably. For purposes of clarification, the Examiner suggests amending the claims to either recite “floating point” or “floating-point” for consistency.
Furthermore, claim 1 appears to contain a grammatical error and should be changed to: “A method of performing a dot product”.
Claim 7 appears to contain a grammatical error and should be changed to: “k exponent sums (eabi) [[is]] are obtained”.
Claim 12 appears to contain a grammatical error and should be changed to: “performing a dot product”.
Claim 12 appears to contain a grammatical error and should be changed to: “a multiplication unit comprising a plurality of multipliers”.
Claim 16 appears to contain a grammatical error and should be changed to: “performing the dot product having an output”.
Claim 17 appears to contain a grammatical error and should be changed to: “performing the dot product having an output”.
Appropriate correction is required.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: Figure 3 reference number 305 within reference number 301. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 8 of copending Application No. 18/111178 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because claim 8 of patent application 18/111178 would anticipate claim 1 with the following mapping between representative claim 1 of the present application and claim 8 of patent application 18/111178.
18/111033 (Claim 1)
18/111178 (Claim 1)
18/111178 (Claim 8)
A method of performing dot product of an array of '2k' floating point numbers,
A method of performing dot product of an array of '2k' floating point numbers,
The method as claimed in claim 1,
k ≥ 3, using a hardware implementation,
k ≥ 3, using a hardware implementation,
The method as claimed in claim 1,
the array comprising a first set of k floating-point numbers ao, ai..., ak-1,
the array comprising a first set of k floating-point numbers ao, ai..., ak-1,
The method as claimed in claim 1,
and a second set of k floating-point numbers bo, b1..., bk-1,
and a second set of k floating-point numbers bo, b1..., bk-1,
The method as claimed in claim 1,
wherein the method comprises: receiving both sets of 'k' floating point numbers;
wherein the method comprises: receiving both sets of 'k' floating point numbers;
The method as claimed in claim 1,
multiplying each floating point number ai with a floating point number bi to generate k product numbers (zi),
multiplying each floating point number ai with a floating point number bi to generate k product numbers (zi),
The method as claimed in claim 1,
each product number (zi) having a mantissa bit length of 'r' bits;
each product number (zi) having a mantissa bit length of 'r+log(k-1)+1' bits;
The method as claimed in claim 1,
creating a set of 'k' numbers (yi) based on the k product numbers (zi),
creating a set of 'k' numbers (yi) based on the k product numbers (zi),
The method as claimed in claim 1,
the numbers (yi) having a bit-length of 'n' bits obtained by adding both extra most-significant bits and extra least-significant bits to the mantissa bit length 'r' of the product numbers (zi),
the numbers (yi) having a bit-length of 'n' bits obtained by adding at least extra most-significant bits to the mantissa bit length 'r' of the product numbers (zi),
The method as claimed in claim 1, wherein adding at least extra most-significant bits to the bit length of the product numbers (zi) further comprises adding one or more least- significant bits to the bit length of the product numbers (zi).
wherein the 'n' bits comprises a number of magnitude bits,
wherein the 'n' bits comprises a number of magnitude bits,
The method as claimed in claim 1,
wherein 'n' is r + [log2(k)] + [log2(k - 1)] + x bits, where x is an integer, and x≥ 1;
wherein 'n' is r + [log2(k)] + [log2(k - 1)] + x bits, where x is an integer, and x≥ 1;
The method as claimed in claim 1,
identifying a maximum exponent sum (emax) among k exponent sums (eabi),
identifying a maximum exponent sum (emax) among k exponent sums (eabi),
The method as claimed in claim 1,
each exponent sum is the sum of exponents of the floating point number ai and the floating point number bi;
each exponent sum is the sum of exponents of the floating point number ai and the floating point number bi;
The method as claimed in claim 1,
aligning the magnitude bits of the numbers (yi) based on the maximum exponent sum (emax);
aligning the magnitude bits of the numbers (yi) based on the maximum exponent sum (emax);
The method as claimed in claim 1,
and adding the set of 'k' numbers concurrently.
and adding the set of 'k' numbers concurrently.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claims 2-4, 6-8, and 10-11 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 2-4, 5-7, and 9-10, respectively, of copending Application No. 18/111178. It would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the limitations set forth in claim 1 of Patent 18/111178 with the limitation of adding extra least-significant bits to the mantissa bit length 'r' of the product numbers (zi) because, “the extra LSBs added to the product numbers (Zi) increase the precision of the result obtained and reduce underflow bits of the product number” (Application 18/111178 specification page 21 paragraph 89).
Claims 12-16 and 19-20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 11-15 and 19-20, respectively, of copending Application No. 18/111178. It would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the limitations set forth in claim 11 of Patent 18/111178 with the limitation of adding extra least-significant bits to the mantissa bit length 'r' of the product numbers (zi) because, “the extra LSBs added to the product numbers (Zi) increase the precision of the result obtained and reduce underflow bits of the product number” (Application 18/111178 specification page 21 paragraph 89).
This is a provisional nonstatutory double patenting rejection.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“format conversion unit” of claim 12. Figures 3 and 5 reference number 302 shows a format conversion unit as a black box without sufficient structure to perform the claimed functions. The applicant’s specification, [0027], [0039], [0082]-[0083], [0087], [00111], [00120], [00124] describes functions of a format conversion unit, but does not describe sufficient structure to perform the claimed functions.
“maximum exponent detection unit” of claim 12. Figures 3 and 5 reference number 304 shows a maximum exponent detective unit as a black box without sufficient structure to perform the claimed functions. The applicant’s specification, [0097]-[0099], [00101], [00120] describes functions of a maximum exponent detection unit, but does not describe sufficient structure to perform the claimed functions. The applicant’s specification, [00113] describes a maximum exponent detection unit as two function logics, but does not describe sufficient structure to perform the claimed functions. The applicant’s specification, [00115] describes a maximum exponent detection unit as a binary search tree, however, this does not describe sufficient structure to perform the claimed functions. The applicant’s specification, [00142] describes a maximum exponent detection unit as performing an algorithm for identifying a maximum value, but does not describe sufficient structure to perform the claimed functions. The applicant’s specification [00156] describes a maximum exponent detection unit implementation with O(logic(k)logic(t)) gates, but does not describe sufficient structure to perform the claimed functions.
“alignment unit” of claim 12. Figure 5 shows an alignment unit with the structure of a plurality of subtractors (505), a plurality of shifters (506), and a plurality of two’s complementors (507). The applicant’s specification further describes the structure of the alignment unit as comprising a plurality of subtractors (505), a plurality of shifters (506), and a plurality of two’s complementors (507), [00119]-[00123].
“processing unit” of claim 12. Figure 5 shows a processing unit of figure 3 (308) as an adder (508). The applicant’s specification, [00125], [00128]-[00129], [00156] describes the structure of a processing unit as an adder.
“renormalization unit” of claim 13. Figure 5 shows a renormalization unit (310) of figure 3 (310) as comprising a shifter (510a) and a subtractor (510b). The applicant’s specification, [00127] further describes a renormalization unit having the structure of a subtractor and a shifter. However, the applicant’s specification and drawings fail to provide sufficient structure to perform the function of rounding. The applicant’s specification, [00127], [00130] and [00145] describes a rounding operation performed after normalization on (nk). The applicant’s specification, [00128] describes the step of rounding performed by implementing any rounding up/down method. Therefore, the specification does not describe sufficient structure to perform the entire claimed functions of renormalizing and rounding.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 12-17, and 19-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The claim limitations of “format conversion unit”, and “maximum exponent detection unit” of claim 12, and the claim limitation of “renormalizing unit” of claim 13 invoke 35 USC 112(f) or pre- AIA 35 USC 112, sixth paragraph. However, the written description fails to provide an adequate description of the structure, material, or acts to perform the claimed functions of these limitations. See rejection under 35 USC 112(b) below for further details as to the lack of structure.
Claims 13-17, and 19-20 inherit the same deficiencies as claim 12 based on dependence.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With regards to claim 1, claim 1 recites the limitations of: “adding the set of 'k' numbers concurrently”. Claim 1 also recites, “a first set of k floating-point numbers”, ”a second set of k floating-point numbers”, and “creating a set of 'k' numbers (yi)”. It is unclear which set the claim limitation “adding the set of 'k' numbers concurrently” is referring to. For purposes of examination, the Examiner interprets the limitation to be referring to the set, (yi).
Furthermore, claim 1 recites the limitations of: “the sum of exponents”. There is a lack of antecedent basis for this claimed limitation. For purposes of examination, the Examiner interprets the limitation to be “a sum of exponents”.
Claims 2-11 inherit the same deficiencies as claim 1 based on dependence.
With regards to claim 4, claim 4 recites the limitation of: “the method of performing a dot product”. Claim 4 is dependent on claim 1, claim 1 recites the limitation of, “performing dot product”. It is unclear if performing a dot product of claim 4 is the same as the dot product calculation as of claim 1. For purposes of examination, the Examiner interprets the limitation of claim 4 to be understood as, “performing [[a]] the dot product”.
Furthermore, claim 4 recites the limitation of: “the precision”. There is insufficient antecedent basis for this claimed limitation. For purposes of examination, the Examiner interprets the limitation to be, “a precision”.
With regards to claim 5, claim 5 recites the limitation of: “the precision”. There is insufficient antecedent basis for this claimed limitation. For purposes of examination, the Examiner interprets the limitation to be, “a precision”.
Furthermore, claim 5 recites the limitation of: “r= max (Q+2, p+q+3)”. There is insufficient antecedent basis for ‘p’, and ‘q’ in the limitation.
With regards to claim 6, claim 6 recites the limitation of: “the bits of the intermediate mantissa product (mabi)”. There is insufficient antecedent basis for this claimed limitation.
Furthermore, claim 6 recites the limitation of: “the bit length of the intermediate mantissa product (mabi)”. There is insufficient antecedent basis for this claimed limitation.
Furthermore, claim 6 recites the limitation of: “p+q+2>r”. There is insufficient antecedent basis for ‘p’, and ‘q’ in the limitations.
Furthermore, claim 6 recites the limitation of: “p+q+2 < r”. There is insufficient antecedent basis for ‘p’, and ‘q’ in the limitations.
Furthermore, claim 6 recites the limitations of: “rounding, the bits of the intermediate mantissa product (mabi) to r bits, if p+q+2>r bits; or padding, extra least-significant bits to the bit length of the intermediate mantissa product (mabi) to generate r bits, if p+q+2 < r bits”. The limitations describe what to do if p+q+2 is greater than or less than ‘r’ but does not describe what to do if r=p+q+2. The claim is describing generating numbers having the mantissa bit length of ‘r’ bits. Therefore, as interpreted by the Examiner, the limitations are meant to be understood as performing rounding if p+q+2>r, perform padding if p+q+2<2, and do nothing if p+q+2=r.
With regards to claim 7, claim 7 recites the limitation of: “wherein identifying a maximum exponent sum (emax)”. Claim 7 is dependent on claim 1, claim 1 recites the limitation of, “identifying a maximum exponent sum (emax)”. It is unclear if the limitation of claim 7 is meant to be understood as another identification of a maximum exponent sum, or if it is meant to be understood as, identifying the maximum exponent sum as of claim 1. For purposes of examination, the Examiner interprets the limitation of claim 7 to be understood as, “wherein identifying [[a]] the maximum exponent sum (emax)”.
Furthermore, claim 7 recites the limitation of: “the maximum value”. There is insufficient antecedent basis for the limitation. For purposes of examination, the Examiner interprets the limitation to be, “a maximum value”.
With regards to claim 10, claim 10 recites the limitations of: “calculating an output value by adding 'k' numbers (yi)”. Claim 10 is dependent on claim 1, claim 1 recites (yi) as a set of numbers. It is unclear if “calculating an output value by adding 'k' numbers (yi)” is meant to be understood as all of the values in the set, (yi), are added together, or if it is meant to be understood as adding some other value or set of values to the set of (yi). For purposes of examination, the Examiner interprets the limitation to mean that the values of the set, (yi), are summed together into a singular output value.
With regards to claim 11, claim 11 recites the limitations of: “for each floating-point number (i)”. There is insufficient antecedent basis for a floating point number (i).
Furthermore, claim 11 recites the limitations of: “calculating the difference (ed)”. There is insufficient antecedent basis for the limitation. For purposes of examination, the Examiner interprets the limitation to be understood as, “calculating a difference (ed)”.
Furthermore, claim 11 recites the limitations of: “the LSB side”. There is insufficient antecedent basis for the limitation. For purposes of examination, the Examiner interprets the limitation as, “a least significant bit (LSB) side”.
Furthermore, claim 11 recites the limitation of “the maximum exponent (emax)”. It is unclear if the maximum exponent (emax) is meant to be understood as the maximum exponent sum (emax) as of claim 1 which claim 11 is dependent upon, or if the limitation is meant to be understood as referring to another (emax), one where it itself is a maximum exponent. For purposes of examination, the Examiner interprets the limitation to be understood as “the maximum exponent sum (emax)”.
With regards to claim 12, claim 12 recites the limitations of: “add the set of 'k' numbers concurrently”. Claim 12 also recites, “a first set of k floating-point numbers”, ” a second set of k floating-point numbers”, and “create a set of 'k' numbers (yi)”. It is unclear which set the claim limitation “add the set of 'k' numbers concurrently” is referring to. For purposes of examination, the Examiner interprets the limitation to be referring to the set, (yi).
Furthermore, claim 12 recites the limitations of: “the sum of exponents”. There is a lack of antecedent basis for this claimed limitation. For purposes of examination, the Examiner interprets the limitation to be “a sum of exponents”.
Furthermore, claim 12 recites limitations regarding “format conversion unit”, and “maximum exponent detection unit” which invokes 35 USC 112(f) or pre-AIA 35 USC 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material or acts for performing the entire claimed function. Regarding the “format conversion unit”, Figures 3 and 5 reference number 302 shows a format conversion unit as a black box without sufficient structure to perform the claimed functions. The applicant’s specification, [0027], [0039], [0082]-[0083], [0087], [00111], [00120], [00124] describes functions of a format conversion unit, but does not describe sufficient structure to perform the claimed functions. Regarding the “maximum exponent detection unit”, Figures 3 and 5 reference number 304 shows a maximum exponent detective unit as a black box without sufficient structure to perform the claimed functions. The applicant’s specification, [0097]-[0099], [00101], [00120] describes functions of a maximum exponent detection unit, but does not describe sufficient structure to perform the claimed functions. The applicant’s specification, [00113] describes a maximum exponent detection unit as two function logics, but does not describe sufficient structure to perform the claimed functions. The applicant’s specification, [00115] describes a maximum exponent detection unit as a binary search tree, however, this does not describe sufficient structure to perform the claimed functions. The applicant’s specification, [00142] describes a maximum exponent detection unit as performing an algorithm for identifying a maximum value, but does not describe sufficient structure to perform the claimed functions. The applicant’s specification [00156] describes a maximum exponent detection unit implementation with O(logic(k)logic(t)) gates, but does not describe sufficient structure to perform the claimed functions. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
With regards to claim 13, claim 13 recites a limitation of regarding a “renormalization unit”. which invokes 35 USC 112(f) or pre-AIA 35 USC 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material or acts for performing the entire claimed function. Figure 5 shows a renormalization unit (310) of figure 3 (310) as comprising a shifter (510a) and a subtractor (510b). The applicant’s specification, [00127] further describes a renormalization unit having the structure of a subtractor and a shifter. However, the applicant’s specification and drawings fail to provide sufficient structure to perform the function of rounding. The applicant’s specification, [00127], [00130] and [00145] describes a rounding operation performed after normalization on (nk). The applicant’s specification, [00128] describes the step of rounding performed by implementing any rounding up/down method. Therefore, the specification does not describe sufficient structure to perform the entire claimed functions of renormalizing and rounding. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claims 13-17, and 19-20 inherit the same deficiencies as claim 12 based on dependence.
With regards to claim 15, claim 15 recites the limitations of: “each mantissa (mai)”. There is insufficient antecedent basis for the limitation.
Furthermore, claim 15 recites the limitations of: “corresponding mantissa (mbi)”. There is insufficient antecedent basis for the limitation.
With regards to claim 16, claim 16 recites the limitation of: “the precision”. There is insufficient antecedent basis for this claimed limitation. For purposes of examination, the Examiner interprets the limitation to be, “a precision”.
Furthermore, claim 16 recites the limitation of: “the hardware implementation for performing a dot product operation”. Claim 16 is dependent on claim 12, claim 12 recites the limitations of, “A hardware implementation for performing dot product”. It is unclear if “performing a dot product operation” is the same as claim 12’s “performing dot product”, or a different dot product. For purposes of examination, the Examiner interprets the limitation of claim 16 to be understood as, “the hardware implementation for performing [[a]] the dot product operation”.
With regards to claim 17, claim 17 recites the limitation of: “the precision”. There is insufficient antecedent basis for this claimed limitation. For purposes of examination, the Examiner interprets the limitation to be, “a precision”.
Furthermore, claim 17 recites the limitation of: “r= max (Q+2, p+q+3)”. There is insufficient antecedent basis for ‘p’, and ‘q’ in the limitation.
Furthermore, claim 17 recites the limitation of: “the hardware implementation for performing a dot product operation”. Claim 17 is dependent on claim 12, claim 12 recites the limitations of, “A hardware implementation for performing dot product”. It is unclear if “performing a dot product operation” is the same as claim 12’s “performing dot product”, or a different dot product. For purposes of examination, the Examiner interprets the limitation of claim 17 to be understood as, “the hardware implementation for performing [[a]] the dot product ”.
With regards to claim 20, claim 20 recites the limitation of: “a hardware implementation as set forth in claim 12”. Claim 20 is referring to claim 12. Claim 12 recites the limitation of, “A hardware implementation”. It is unclear if the limitation of claim 12 is intended to be implying there are multiple possible hardware implementations set forth in claim 12 and the limitation of claim 12 is referring to a single one of the hardware implementations, or if the limitation of claim 12 is meant to be understood as the hardware implementation as set forth in claim 12. For purposes of examination, the Examiner interprets the limitation to be understood as, “[[a]] the hardware implementation as set forth in claim 12”.
With regards to claim 18, claim 18 recites the limitations of: “comprising k first intermediate product numbers (zi') and k second intermediate product numbers (zi"), each having a mantissa bit length of 'r+1' bits”. It is unclear if “each having a mantissa bit length of 'r+1' bits” is referring to each of the product numbers (zi’) or each of the product numbers (zi’’), or each of both sets of product numbers (zi’) and (zi’’). For purposes of examination, the Examiner interprets the limitation to be referring to each of the product numbers (zi’) and each of the product numbers (zi’’).
Furthermore, claim 18 recites the limitations of: “comprising k first numbers (yi') and k second numbers (yi"), based on the 2k product numbers, each having a bit-length of 'n' bits obtained by adding both extra most-significant bits and extra least-significant bits to the mantissa bit length of the product numbers (zi and zi")”. It is unclear if “each having a bit-length of 'n' bits obtained by adding both extra most-significant bits and extra least-significant bits to the mantissa bit length of the product numbers (zi and zi")” is referring to each of the k first numbers (yi’), or each of the k second numbers (yi’’), or each of both the k first numbers (yi’) and (yi’’). For purposes of examination, the Examiner interprets the limitation to be referring to both the k first numbers (yi’) and (yi’’).
Furthermore, claim 18 recites the limitations of: “(zi and zi")”. There is insufficient antecedent basis for “zi” in the claim. For purposes of examination, the Examiner interprets the limitation to be, “([[zi]] zi’ and zi")”.
Furthermore, claim 18 recites the limitations of: “the 'n' bits”. It is unclear if “the 'n' bits” is referring to the ‘n’ bits of (yi’), or the ‘n’ bits of (yi’’), or if it is meant to be understood as the ‘n’ bits of both (yi’) and (yi’’). For purposes of examination, the Examiner interprets the limitation to be referring to the ‘n’ bits of both (yi’) and (yi’’).
Furthermore, claim 18 recites the limitation of: “adding the set of '2k' numbers concurrently”. Claim 18 also recites the limitations of, “an array of '2k' floating point numbers”, “the array comprising a first set of k floating-point numbers … and a second set of k floating-point numbers”. Claim 18 recites further limitations of, “a set of '2k' numbers comprising k first numbers (yi') and k second numbers (yi")”, and “generating 2k product numbers comprising k first intermediate product numbers (zi') and k second intermediate product numbers (zi")”. It is unclear what numbers are being referred to as “the set of '2k' numbers”. For purposes of examination, the Examiner interprets the limitation to be referring to, the set of 2k numbers comprising (yi’) and (yi’’).
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 19 rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because the claim is directed to an integrated circuit definition dataset, which is merely information or data (e.g., data per se) being received as illustrated in figure 10. [00177] also describes that an integrated circuit definition dataset may be in form of computer code (e.g., software per se). Thus, it does not fall within a statutory category.
Claims 1-11, and 18 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more.
Regarding claim 1, under the Alice Framework Step 1, claim 1 falls within the four statutory categories of patentable subject matter identified by 35 USC 101: a process, machine, manufacture, or a composition of matter.
Under the Alice Framework Step 2A prong 1, claim 1 recites an abstract idea, including mathematical concept. Specifically, claim 1 recites the following, mathematical relationships, calculations, formulas:
A method of performing dot product of an array of '2k' floating point numbers, k ≥ 3, the array comprising a first set of k floating-point numbers ao, ai..., ak-1, and a second set of k floating-point numbers bo, b1..., bk-i, wherein the method comprises: both sets of 'k' floating point numbers; multiplying each floating point number ai with a floating point number bi to generate k product numbers (zi), each product number (zi) having a mantissa bit length of 'r' bits; creating a set of 'k' numbers (yi) based on the k product numbers (zi), the numbers (yi) having a bit-length of 'n' bits obtained by adding both extra most-significant bits and extra least-significant bits to the mantissa bit length 'r' of the product numbers (zi), wherein the 'n' bits comprises a number of magnitude bits, wherein 'n' is r + ⌈ log2(k) ⌉ + ⌈ log2(k - 1) ⌉ + x bits, where x is an integer, and x ≥ 1; identifying a maximum exponent sum (emax) among k exponent sums (eabi), each exponent sum is the sum of exponents of the floating point number ai and the floating point number bi; aligning the magnitude bits of the numbers (yi) based on the maximum exponent sum (emax); and adding the set of 'k' numbers concurrently.
Under the Alice Framework Step 2A prong 2 analysis, claim 1 recites the additional elements of, “hardware implementation”, and “receiving”. The additional element of “hardware implementation” is described in the manner of a generic computer used as a tool to perform the abstract idea, MPEP 2106.04(d)(I). The additional element of “receiving” is insignificant extra-solution activity regarding mere data gathering, see MPEP 2106.04(d)(I), 2106.05(g). For these reasons claim 1 is not integrated into a practical application.
Under the Alice Framework Step 2B analysis, the additional element of “hardware implementation” is merely describing a generic computer used as a tool to perform an abstract idea, MPEP 2106.05(I)(A) regarding limitations the courts have found not to be enough to qualify as “significantly more” when recited in a claim with judicial exception, MPEP 2106.05(f) regarding mere instructions to implement an abstract idea on a computer. The additional element of “receiving” is well-understood, routine, conventional activity, see MPEP 2106.05(d)(II)(i) regarding transmitting/receiving data over a network. For these reasons, claim 1 is not amounting to significantly more than the abstract idea.
Claim 2 is rejected for at least the reasons set forth with respect to claim 1. Claim 2 merely further limits the mathematical concept set forth in claim 1.
Under the Alice Framework Step 2A prong 1, claim 2 recites an abstract idea, including a mathematical concept. Specifically, claim 2 recites the following mathematical relationships, calculations, formulas:
The method as claimed in claim 1, wherein each number in the first set of k floating- point numbers ao, ai..., ak-i comprises a mantissa (mai) and an exponent (eai) and each number in the second set of k floating-point numbers bo, bi..., bk-i comprises a mantissa (mbi) and an exponent (ebi), where each mantissa (mai) is having a bit length of 'p' bits and each mantissa (mbi) is having a bit length of 'q' bits.
Claim 2 recites no further additional elements in the claim limitations which require a Step 2A prong 2 or Step 2B analysis. For these reasons, claim 2 is neither integrated into a practical application nor amounting to significantly more than the abstract idea.
Claim 3 is rejected for at least the reasons set forth with respect to claim 2. Claim 3 merely further limits the mathematical concept set forth in claim 2.
Under the Alice Framework Step 2A prong 1, claim 3 recites an abstract idea, including a mathematical concept. Specifically, claim 3 recites the following mathematical relationships, calculations, formulas:
The method as claimed in claim 2, wherein multiplying each floating point number ai with the corresponding floating point number bi comprises multiplying mantissa (mai) and mantissa (mbi) to obtain an intermediate mantissa product (mabi).
Claim 3 recites no further additional elements in the claim limitations which require a Step 2A prong 2 or Step 2B analysis. For these reasons, claim 3 is neither integrated into a practical application nor amounting to significantly more than the abstract idea.
Claim 4 is rejected for at least the reasons set forth with respect to claim 1. Claim 4 merely further limits the mathematical concept set forth in claim 1.
Under the Alice Framework Step 2A prong 1, claim 4 recites an abstract idea, including a mathematical concept. Specifically, claim 4 recites the following mathematical relationships, calculations, formulas:
The method as claimed in claim 1, wherein the method of performing a dot product emulates the precision obtained using separate multiplication and addition units, for performing dot product having an output mantissa bit length of P bits, by setting the mantissa bit length of 'r' bits as 'r=P+2' bits.
The Examiner notes, claim 4 recites “multiplication and addition units”. However, the claimed limitation refers to the “multiplication and addition units” as merely part of an emulation, not positively reciting the use/structure of “multiplication and addition units” themselves. Therefore, the “multiplication and addition units” are characterized as part of the mathematical algorithm, an intended result of the algorithm to emulate “multiplication and addition units”.
Claim 4 recites no further additional elements in the claim limitations which require a Step 2A prong 2 or Step 2B analysis. For these reasons, claim 4 is neither integrated into a practical application nor amounting to significantly more than the abstract idea.
Claim 5 is rejected for at least the reasons set forth with respect to claim 1. Claim 5 merely further limits the mathematical concept set forth in claim 1.
Under the Alice Framework Step 2A prong 1, claim 5 recites an abstract idea, including a mathematical concept. Specifically, claim 5 recites the following mathematical relationships, calculations, formulas:
The method as claimed in claim 1, wherein the method emulates the precision obtained using fused multiplication and addition units, for performing dot product having an output mantissa bit length of Q bits, by setting the mantissa bit length of 'r' bits as 'r= max (Q+2, p+q+3)' bits.
The Examiner notes, claim 5 recites “multiplication and addition units”. However, the claimed limitation refers to the “multiplication and addition units” as merely part of an emulation, not positively reciting the use/structure of “multiplication and addition units” themselves. Therefore, the “multiplication and addition units” are characterized as part of the mathematical algorithm, an intended result of the algorithm to emulate “multiplication and addition units”.
Claim 5 recites no further additional elements in the claim limitations which require a Step 2A prong 2 or Step 2B analysis. For these reasons, claim 5 is neither integrated into a practical application nor amounting to significantly more than the abstract idea.
Claim 6 is rejected for at least the reasons set forth with respect to claim 1. Claim 6 merely further limits the mathematical concept set forth in claim 1.
Under the Alice Framework Step 2A prong 1, claim 6 recites an abstract idea, including a mathematical concept. Specifically, claim 6 recites the following mathematical relationships, calculations, formulas:
The method as claimed in claim 1, wherein generating k product numbers (zi) having the mantissa bit length of 'r' bits comprises: rounding, the bits of the intermediate mantissa product (mabi) to r bits, if p+q+2>r bits; or padding, extra least-significant bits to the bit length of the intermediate mantissa product (mabi) to generate r bits, if p+q+2 < r bits.
Claim 6 recites no further additional elements in the claim limitations which require a Step 2A prong 2 or Step 2B analysis. For these reasons, claim 6 is neither integrated into a practical application nor amounting to significantly more than the abstract idea.
Claim 7 is rejected for at least the reasons set forth with respect to claim 1. Claim 7 merely further limits the mathematical concept set forth in claim 1.
Under the Alice Framework Step 2A prong 1, claim 7 recites an abstract idea, including a mathematical concept. Specifically, claim 7 recites the following mathematical relationships, calculations, formulas:
The method as claimed in claim 1, wherein identifying a maximum exponent sum (emax) includes identifying the maximum value among k exponent sums (eabi) where k exponent sums (eabi) is obtained by summing exponent (eal) and exponent (ebi).
Claim 7 recites no further additional elements in the claim limitations which require a Step 2A prong 2 or Step 2B analysis. For these reasons, claim 7 is neither integrated into a practical application nor amounting to significantly more than the abstract idea.
Claim 8 is rejected for at least the reasons set forth with respect to claim 1. Claim 8 merely further limits the mathematical concept set forth in claim 1.
Under the Alice Framework Step 2A prong 1, claim 8 recites an abstract idea, including a mathematical concept. Specifically, claim 8 recites the following mathematical relationships, calculations, formulas:
The method as claimed in claim 1, wherein adding extra most-significant bits to the mantissa bit length 'r' of the product numbers (zi) comprises adding at least ⌈log2(k)⌉ number of the most-significant bits.
Claim 8 recites no further additional elements in the claim limitations which require a Step 2A prong 2 or Step 2B analysis. For these reasons, claim 8 is neither integrated into a practical application nor amounting to significantly more than the abstract idea.
Claim 9 is rejected for at least the reasons set forth with respect to claim 1. Claim 9 merely further limits the mathematical concept set forth in claim 1.
Under the Alice Framework Step 2A prong 1, claim 9 recites an abstract idea, including a mathematical concept. Specifically, claim 9 recites the following mathematical relationships, calculations, formulas:
The method as claimed in claim 1, wherein adding extra least-significant bits to the mantissa bit length 'r' of the product numbers (zi) comprises adding at least ⌈log2(k - 1) ⌉ + 1 number of the least-significant bits.
Claim 9 recites no further additional elements in the claim limitations which require a Step 2A prong 2 or Step 2B analysis. For these reasons, claim 9 is neither integrated into a practical application nor amounting to significantly more than the abstract idea.
Claim 10 is rejected for at least the reasons set forth with respect to claim 1. Claim 10 merely further limits the mathematical concept set forth in claim 1.
Under the Alice Framework Step 2A prong 1, claim 10 recites an abstract idea, including a mathematical concept. Specifically, claim 10 recites the following mathematical relationships, calculations, formulas:
The method as claimed in claim 1, wherein the method further comprises: calculating an output value by adding 'k' numbers (yi); renormalizing the output value; and rounding the output value to represent the output value as a floating-point number.
Claim 10 recites no further additional elements in the claim limitations which require a Step 2A prong 2 or Step 2B analysis. For these reasons, claim 10 is neither integrated into a practical application nor amounting to significantly more than the abstract idea.
Claim 11 is rejected for at least the reasons set forth with respect to claim 1. Claim 11 merely further limits the mathematical concept set forth in claim 1.
Under the Alice Framework Step 2A prong 1, claim 11 recites an abstract idea, including a mathematical concept. Specifically, claim 11 recites the following mathematical relationships, calculations, formulas:
The method as claimed in claim 1, wherein aligning the magnitude bits of the numbers (yi) to be based on the maximum exponent (emax) comprises the steps of, for each floating-point number (i): calculating the difference (ed) between the maximum exponent sum (emax) and each exponent sum (eabi); and shifting the magnitude bits of the corresponding number (yi), to the LSB side, based on the calculated difference (ed).
Claim 11 recites no further additional elements in the claim limitations which require a Step 2A prong 2 or Step 2B analysis. For these reasons, claim 11 is neither integrated into a practical application nor amounting to significantly more than the abstract idea.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Finch (U.S. Patent Application Publication 2022/0405051A1), hereinafter, “Finch”.
With regards to claim 1, Finch teaches:
A method of performing dot product of an array of '2k' floating point numbers, k ≥ 3, using a hardware implementation, (Fig. 1A regarding hardware implementation; [0070]-[0073] regarding performing dot product operations on two N sets of numbers; [0098] regarding N=16);
the array comprising a first set of k floating-point numbers ao, ai..., ak-1, (Fig. 1A regarding reference number 101 (input) as 16bxN; [0098] regarding a floating point input of N pairs input into Fig. 1A, N=16; [0070] regarding input [a1, a2, …, an]);
and a second set of k floating-point numbers bo, b1..., bk-1, (Fig. 1A regarding reference number 103 (coeff) as 16bxN; [0098] regarding a floating point input of N pairs input into Fig. 1A, N=16; [0070] regarding coefficient input [b1k, …, bnk]);
wherein the method comprises: receiving both sets of 'k' floating point numbers; (Fig. 1A regarding reference numbers 101 (input), and 103 (coeff); [0098] regarding a floating point input of N pairs input into Fig. 1A, N=16; [0070] regarding input regarding input [a1, a2, …, an] and coefficient input [b1k, …, bnk]);
multiplying each floating point number ai with a floating point number bi to generate k product numbers (zi), (Fig. 1A regarding reference numbers 101 (input), and 103 (coeff) processed by reference number 104 (mantissa processor) and output from 104, 109 (fraction output)as 16bXN; Fig. 3 regarding input and coefficient multiplied together; [0070]-[0073] regarding performing dot product operations on two N sets of numbers; [0070] regarding multiplying and accumulating the inputs by the coefficients, furthermore regarding [a1, a2, …, an]*[b1k, …, bnk] = [a1b1k + a2b2k + ... + anbnk]; [0098] regarding Fig. 1 as described as N pairs of floating point values comprised of the floating point input, and the floating point coefficient, are processed simultaneously by N first stages, N second stages, and adder stages);
each product number (zi) having a mantissa bit length of 'r' bits; (Fig. 1A regarding reference numbers 101 (input), and 103 (coeff) processed by reference number 104 (mantissa processor) and output from 104, 109 (fraction output)as 16bits (as 'r'); Fig. 3 regarding input and coefficient multiplied together generating a product; [0070]-[0073] regarding performing dot product operations on two N sets of numbers; [0070] regarding multiplying and accumulating the inputs by the coefficients, furthermore regarding [a1, a2, …, an]*[b1k, …, bnk] = [a1b1k + a2b2k + ... + anbnk]; [0098] regarding Fig. 1 as described as N pairs of floating point values comprised of the floating point input, and the floating point coefficient, are processed simultaneously by N first stages, N second stages, and adder stages);
creating a set of 'k' numbers (yi) based on the k product numbers (zi), the numbers (yi) having a bit-length of 'n' bits obtained by adding both extra most-significant bits and extra least-significant bits to the mantissa bit length 'r' of the product numbers (zi), (Fig. 1A regarding reference numbers 109 (fraction outputs 16bXN), 122 (Pad, Complement, Shift (PCS) Processor); Fig. 5 regarding reference number 502 (0s padding), and the output as (yi); [0088] regarding the PCS processor adding leading extra leading 0s, and extra trailing 0s to the mantissa input, padding the mantissa to 32bits; [0098] regarding Fig. 1 as described as N pairs of floating point values comprised of the floating point input, and the floating point coefficient, are processed simultaneously by N first stages, N second stages, and adder stages);
wherein the 'n' bits comprises a number of magnitude bits, wherein 'n' is r + ⌈log2(k)⌉ + ⌈log2(k - 1)⌉ + x bits, where x is an integer, and x≥ 1; (Fig. 1A regarding reference numbers 109 (fraction outputs 16bXN), 122 (Pad, Complement, Shift (PCS) Processor); Fig. 5 regarding reference number 502 (0s padding); [0088] regarding the PCS processor adding leading extra leading 0s, and extra trailing 0s to the mantissa input, padding the mantissa to 32bits; [0098] regarding Fig. 1 as described as N pairs of floating point values comprised of the floating point input, and the floating point coefficient, are processed simultaneously by N first stages, N second stages, and adder stages; As interpreted by the Examiner, r = 16 (as referenced above), k = 16 (as referenced above), thus r + [log2(k)] + [log2(k - 1)] + x is equal to, 16 + [log2(16)]+[log2(16-1)] + x, which is 16 + 4 + 4 + x = 'n'. 'n' is 32 bits, thus 16 + 4 + 4 + x = 32 which shows x = 8);
identifying a maximum exponent sum (emax) among k exponent sums (eabi), each exponent sum is the sum of exponents of the floating point number ai and the floating point number bi; (Fig. 1A regarding reference number 106 (exponent processors); [0098] regarding Fig. 1 as described as N pairs of floating point values comprised of the floating point input, and the floating point coefficient, are processed simultaneously by N first stages, N second stages, and adder stages; [0072] regarding a central find exponent processor (112) receiving inputs from all of the exponent processors to generate a maximum exponent sum (164); [0079] regarding Exponent processor (104) of the N exponent processors summing exponents from the input (101) and the coefficient (103), each Exponent processor of the N exponent processors are connected to a shared find max exponent finder (112) which receives exponent sums from all N first pipeline stages and outputs the largest exponent from among all first stage exponent sums; Fig 4 regarding reference numbers 101 (input exponent), 103 (coefficient exponent), 104 (exponent processor using an adder), 422 (other stages), 112 (central max exponent finder), 164 (max exponent));
aligning the magnitude bits of the numbers (yi) based on the maximum exponent sum (emax); (Fig. 1A regarding reference numbers 114 (mantissa), 106 (exponent processor), 115 (Exp_diff/shift amount), 110 (control/exponent registers), 118 (Exp_diff/shift amount), 122 (PCS processor); Fig. 4 regarding reference numbers 164 (maximum exponent), 406 (exponent difference adjustment), 115 (exponent difference), and 110 (control/exponent registers) outputting 118 (exponent difference) based on 115(exponent difference); Fig. 5 regarding reference numbers 118 (exponent difference/shift amount), 114 (mantissa), 506 (shift processor); [0079] regarding initial difference 404 being the difference between the current exponent and the max exponent; [0080] regarding generating exp_diff output 115 based on initial difference 404; [0090] regarding shifting the mantissa based on the exponential difference (118));
and adding the set of 'k' numbers concurrently. ([0098] regarding Fig. 1 as described as N pairs of floating point values comprised of the floating point input, and the floating point coefficient, are processed simultaneously by N first stages, N second stages, and adder stages; Fig. 1A regarding reference numbers 114 (fraction outputs 16bXN), 122 ((PCS) Processor), 156 (integer form fractions), 154 (adder stage); Fig. 5 regarding the output as (yi); [0072] regarding the common adder stage (154) receiving integer form fractions from all of the MAC processors and forms the single accumulated floating point output value (148); [0087] regarding adder (124) as operating on 8 pairs of 32 bit values (8 pairs, meaning 16, k, total numbers); Fig. 1B regarding the adder stage (154) operating on the 8 pairs of values, adding the values to generate an output value (148) the single accumulated floating point output value; [0102] regarding pipeline stages operating concurrently).
With regards to claim 2, Finch teaches the method as claimed in claim 1, as referenced above.
Finch further teaches:
wherein each number in the first set of k floating- point numbers ao, ai..., ak-i comprises a mantissa (mai) and an exponent (eal) and each number in the second set of k floating-point numbers bo, bi..., bk-i comprises a mantissa (mbi) and an exponent (ebi), where each mantissa (mai) is having a bit length of 'p' bits and each mantissa (mbi) is having a bit length of 'q' bits. (Fig. 1A regarding input and coefficient values having a mantissa and an exponent; [0098] regarding Fig. 1 as described as N pairs of floating point values comprised of the floating point input, and the floating point coefficient, are processed simultaneously by N first stages, N second stages, and adder stages; Fig. 3 regarding the mantissa processor processing the mantissa of the input and coefficient values; [0078] regarding the mantissa processor (104) inputting a pair of 7 (bit) components from floating point input (101) and coefficient (103); Fig. 4 regarding the exponent processor operating on the input exponent and coefficient exponent, each being 7 bits).
With regards to claim 3, Finch teaches the method as claimed in claim 2, as referenced above.
Finch further teaches:
wherein multiplying each floating point number ai with the corresponding floating point number bi comprises multiplying mantissa (mai) and mantissa (mbi) to obtain an intermediate mantissa product (mabi). (Fig. 1A regarding input and coefficient values having a mantissa; [0098] regarding Fig. 1 as described as N pairs of floating point values comprised of the floating point input, and the floating point coefficient, are processed simultaneously by N first stages, N second stages, and adder stages; Fig. 3 regarding the mantissa processor processing the mantissa of the input and coefficient values, and a result of the mantissa processor being 16 bits).
With regards to claim 4, Finch teaches the method as claimed in claim 1, as referenced above.
Finch further teaches:
wherein the method of performing a dot product emulates the precision obtained using separate multiplication and addition units, for performing dot product having an output mantissa bit length of P bits, by setting the mantissa bit length of 'r' bits as 'r=P+2' bits. (Fig. 1A regarding reference numbers 101 (input), and 103 (coeff) processed by reference number 104 (mantissa processor) and output from 104, 109 (fraction output)as 16bits (as 'r'); Fig. 3 regarding input and coefficient multiplied together generating a product; [0070]-[0073] regarding performing dot product operations on two N sets of numbers; [0070] regarding multiplying and accumulating the inputs by the coefficients, furthermore regarding [a1, a2, …, an]*[b1k, …, bnk] = [a1b1k + a2b2k + ... + anbnk]; As interpreted by the Examiner, r is equal to 16 bits (as referenced above), so, r = P + 2 becomes 16 = P + 2, P =14. Furthermore, emulation of the precision obtained using separate multiplication and addition units, for performing dot product having an output mantissa bit length of P bits is a natural consequence of setting the mantissa bit length of ‘r’ bits as ‘r=P+2’ bits).
With regards to claim 5, Finch teaches the method as claimed in claim 1, as referenced above.
Finch further teaches:
wherein the method emulates the precision obtained using fused multiplication and addition units, for performing dot product having an output mantissa bit length of Q bits, by setting the mantissa bit length of 'r' bits as 'r= max (Q+2, p+q+3)' bits. Fig. 1A regarding reference numbers 101 (input), and 103 (coeff) processed by reference number 104 (mantissa processor) and output from 104, 109 (fraction output)as 16bits (as 'r'); Fig. 3 regarding input and coefficient multiplied together generating a product; [0070]-[0073] regarding performing dot product operations on two N sets of numbers; [0070] regarding multiplying and accumulating the inputs by the coefficients, furthermore regarding [a1, a2, …, an]*[b1k, …, bnk] = [a1b1k + a2b2k + ... + anbnk]; As interpreted by the Examiner, r is equal to 16 bits (as referenced above), so, r = max (Q+2, p+q+3) becomes 16 = max(Q+2, p+q+3). Here, r is either Q+2 or p+q+3, whichever is larger. As referenced above, r is 16, so 16 = Q+2 OR 16 = p+q+3. As interpreted by the Examiner, Q+2 is larger, so 16=Q+2, which gives Q=14. Furthermore, emulation of the precision obtained using fused multiplication and addition units, for performing dot product having an output mantissa bit length of Q bits is a natural consequence of setting the mantissa bit length of ‘r’ as ‘r=max(Q+2, P+Q+3)’ bits).
With regards to claim 6, Finch teaches the method as claimed in claim 1, as referenced above.
Finch further teaches:
wherein generating k product numbers (zi) having the mantissa bit length of 'r' bits comprises: rounding, the bits of the intermediate mantissa product (mabi) to r bits, if p+q+2>r bits; or padding, extra least-significant bits to the bit length of the intermediate mantissa product (mabi) to generate r bits, if p+q+2 < r bits. (Fig. 1A regarding input and coefficient values having a mantissa and an exponent; [0098] regarding Fig. 1 as described as N pairs of floating point values comprised of the floating point input, and the floating point coefficient, are processed simultaneously by N first stages, N second stages, and adder stages; Fig. 3 regarding the mantissa processor processing the mantissa of the input and coefficient values; [0078] regarding the mantissa processor (104) inputting a pair of 7 (bit) components from floating point input (101) and coefficient (103); As interpreted by the Examiner, p = 7, q = 7, and p+q+2 = 16 ='r').
With regards to claim 7, Finch teaches the method as claimed in claim 1, as referenced above.
Finch further teaches:
wherein identifying a maximum exponent sum (emax) includes identifying the maximum value among k exponent sums (eabi) where k exponent sums (eabi) is obtained by summing exponent (eai) and exponent (ebi). (Fig. 1A regarding reference number 106 (exponent processors); [0098] regarding Fig. 1 as described as N pairs of floating point values comprised of the floating point input, and the floating point coefficient, are processed simultaneously by N first stages, N second stages, and adder stages; [0072] regarding a central find exponent processor (112) receiving inputs from all of the exponent processors to generate a maximum exponent sum (164); [0079] regarding Exponent processor (104) of the N exponent processors summing exponents from the input (101) and the coefficient (103), each Exponent processor of the N exponent processors are connected to a shared find max exponent finder (112) which receives exponent sums from all N first pipeline stages and outputs the largest exponent from among all first stage exponent sums; Fig 4 regarding reference numbers 101 (input exponent), 103 (coefficient exponent), 104 (exponent processor using an adder), 422 (other stages), 112 (central max exponent finder), 164 (max exponent)).
With regards to claim 8, Finch teaches the method as claimed in claim 1, as referenced above.
Finch further teaches:
wherein adding extra most-significant bits to the mantissa bit length 'r' of the product numbers (zi) comprises adding at least [log2(k)] number of the most-significant bits. (Fig. 1A regarding reference numbers 109 (fraction outputs 16bXN), 122 (Pad, Complement, Shift (PCS) Processor); Fig. 5 regarding reference number 502 (0s padding), and the output as (yi); [0088] regarding the PCS processor adding leading extra leading 0s, and extra trailing 0s to the mantissa input, padding the mantissa to 32bits; [0098] regarding Fig. 1 as described as N pairs of floating point values comprised of the floating point input, and the floating point coefficient, are processed simultaneously by N first stages, N second stages, and adder stages. As interpreted by the Examiner, [log2(k)] = [log2(16)] = 4. The mantissa (114) is 16 bits, and is padded with most-significant bits to be 32 bits [0088], thus adding at least 4 most significant bits).
With regards to claim 9, Finch teaches the method as claimed in claim 1, as referenced above.
Finch further teaches:
wherein adding extra least-significant bits to the mantissa bit length 'r' of the product numbers (zi) comprises adding at least [log2(k - 1)1 + 1 number of the least-significant bits. (Fig. 1A regarding reference numbers 109 (fraction outputs 16bXN), 122 (Pad, Complement, Shift (PCS) Processor); Fig. 5 regarding reference number 502 (0s padding), and the output as (yi); [0088] regarding the PCS processor adding leading extra leading 0s, and extra trailing 0s to the mantissa input, padding the mantissa to 32bits; [0098] regarding Fig. 1 as described as N pairs of floating point values comprised of the floating point input, and the floating point coefficient, are processed simultaneously by N first stages, N second stages, and adder stages. As interpreted by the Examiner, [log2(k-1)]+1 = [log2(16-1)]+1 = 5. The mantissa (114) is 16 bits, and is padded with trailing 0's to be 32 bits [0088], thus adding at least 4 most significant bits).
With regards to claim 10, Finch teaches the method as claimed in claim 1, as referenced above.
Finch further teaches:
wherein the method further comprises: calculating an output value by adding 'k' numbers (yi); ([0098] regarding Fig. 1 as described as N pairs of floating point values comprised of the floating point input, and the floating point coefficient, are processed simultaneously by N first stages, N second stages, and adder stages; Fig. 1A regarding reference numbers 114 (fraction outputs 16bXN), 122 ((PCS) Processor), 156 (integer form fractions), 154 (adder stage); Fig. 5 regarding the output as (yi); [0072] regarding the common adder stage (154) receiving integer form fractions from all of the MAC processors and forms the single accumulated floating point output value (148); [0087] regarding adder (124) as operating on 8 pairs of 32 bit values (8 pairs, meaning 16, k, total numbers); Fig. 1B regarding the adder stage (154) operating on the 8 pairs of values, adding the values to generate an output value (148) the single accumulated floating point output value; [0102] regarding pipeline stages operating concurrently);
renormalizing the output value; and rounding the output value to represent the output value as a floating-point number. (Fig. 1B regarding normalizing the output value using reference number 146 (Normalize, Adjust, Round exponent); [0092] regarding a normalization and rounding step in generating the final floating point output from the adder stage 154).
With regards to claim 11, Finch teaches the method as claimed in claim 1, as referenced above.
Finch further teaches:
wherein aligning the magnitude bits of the numbers (yi) to be based on the maximum exponent (emax) comprises the steps of, for each floating-point number (i): calculating the difference (ed) between the maximum exponent sum (emax) and each exponent sum (eabi); and shifting the magnitude bits of the corresponding number (yi), to the LSB side, based on the calculated difference (ed). (Fig. 1A regarding reference numbers 114 (mantissa), 106 (exponent processor), 115 (Exp_diff/shift amount), 110 (control/exponent registers), 118 (Exp_diff/shift amount), 122 (PCS processor); Fig. 4 regarding reference numbers 164 (maximum exponent), 406 (exponent difference adjustment), 115 (exponent difference), and 110 (control/exponent registers) outputting 118 (exponent difference) based on 115(exponent difference); Fig. 5 regarding reference numbers 118 (exponent difference/shift amount), 114 (mantissa), 506 (shift processor); [0079] regarding initial difference 404 being the difference between the current exponent and the max exponent; [0080] regarding generating exp_diff output 115 based on initial difference 404; [0090] regarding right shifting (the LSB side) the mantissa based on the exponential difference (118)).
With regards to claim 12, Finch teaches:
A hardware implementation for performing dot product of an array of '2k' floating point numbers, k ≥ 3, (A hardware implementation for performing dot product of an array of '2k' floating point numbers, k ≥ 3,);
the array comprising a first set of k floating-point numbers ao, ai..., ak-1, (Fig. 1A regarding reference number 101 (input) as 16bxN; [0098] regarding a floating point input of N pairs input into Fig. 1A, N=16; [0070] regarding input [a1, a2, …, an]);
and a second set of k floating-point numbers bo, b1..., bk-1, (Fig. 1A regarding reference number 103 (coeff) as 16bxN; [0098] regarding a floating point input of N pairs input into Fig. 1A, N=16; [0070] regarding coefficient input [b1k, …, bnk]);
wherein the hardware implementation comprises: a multiplication unit comprising a plurality of multiplier configured to: receive both sets of 'k' floating point numbers; (Fig. 1A regarding reference numbers 101 (input), and 103 (coeff) input into 104 (mantissa processor) as a multiplication unit; [0098] regarding a floating point input of N pairs input into Fig. 1A, N=16; [0070] regarding input regarding input [a1, a2, …, an] and coefficient input [b1k, …, bnk]); Fig. 3 regarding the mantissa processor performing multiplication;
multiply each floating point number ai with a corresponding floating point number bi to generate k product numbers (zi), (Fig. 1A regarding reference numbers 101 (input), and 103 (coeff) processed by reference number 104 (mantissa processor) and output from 104, 109 (fraction output)as 16bXN; Fig. 3 regarding input and coefficient multiplied together; [0070]-[0073] regarding performing dot product operations on two N sets of numbers; [0070] regarding multiplying and accumulating the inputs by the coefficients, furthermore regarding [a1, a2, …, an]*[b1k, …, bnk] = [a1b1k + a2b2k + ... + anbnk]; [0098] regarding Fig. 1 as described as N pairs of floating point values comprised of the floating point input, and the floating point coefficient, are processed simultaneously by N first stages, N second stages, and adder stages);
each product number (zi) having a mantissa bit length of 'r' bits; (Fig. 1A regarding reference numbers 101 (input), and 103 (coeff) processed by reference number 104 (mantissa processor) and output from 104, 109 (fraction output)as 16bits (as 'r'); Fig. 3 regarding input and coefficient multiplied together generating a product; [0070]-[0073] regarding performing dot product operations on two N sets of numbers; [0070] regarding multiplying and accumulating the inputs by the coefficients, furthermore regarding [a1, a2, …, an]*[b1k, …, bnk] = [a1b1k + a2b2k + ... + anbnk]; [0098] regarding Fig. 1 as described as N pairs of floating point values comprised of the floating point input, and the floating point coefficient, are processed simultaneously by N first stages, N second stages, and adder stages);
a format conversion unit configured to: create a set of 'k' numbers (yi) based on the k product numbers (zi), the numbers (yi) having a bit-length of 'n' bits obtained by adding both extra most- significant bits and extra least-significant bits to the mantissa bit length 'r' of the product numbers (zi), (Fig. 1A regarding reference numbers 109 (fraction outputs 16bXN), 122 (Pad, Complement, Shift (PCS) Processor) (which comprises a format conversion unit); Fig. 5 regarding reference number 502 (0s padding), and the output as (yi); [0088] regarding the PCS processor adding leading extra leading 0s, and extra trailing 0s to the mantissa input, padding the mantissa to 32bits; [0098] regarding Fig. 1 as described as N pairs of floating point values comprised of the floating point input, and the floating point coefficient, are processed simultaneously by N first stages, N second stages, and adder stages);
wherein the 'n' bits comprises a number of magnitude bits, wherein 'n' is r + ⌈log2(k)⌉ + ⌈log2(k - 1)⌉ + x bits, where x is an integer, and x≥ 2; (Fig. 1A regarding reference numbers 109 (fraction outputs 16bXN), 122 (Pad, Complement, Shift (PCS) Processor); Fig. 5 regarding reference number 502 (0s padding); [0088] regarding the PCS processor adding leading extra leading 0s, and extra trailing 0s to the mantissa input, padding the mantissa to 32bits; [0098] regarding Fig. 1 as described as N pairs of floating point values comprised of the floating point input, and the floating point coefficient, are processed simultaneously by N first stages, N second stages, and adder stages; As interpreted by the Examiner, r = 16 (as referenced above), k = 16 (as referenced above), thus r + [log2(k)] + [log2(k - 1)] + x is equal to, 16 + [log2(16)]+[log2(16-1)] + x, which is 16 + 4 + 4 + x = 'n'. 'n' is 32 bits, thus 16 + 4 + 4 + x = 32 which shows x = 8);
a maximum exponent detection unit configured to identify a maximum exponent sum (emax) among k exponent sums (eabi), each exponent sum is the sum of exponents of the floating point number ai and the floating point number bi; (Fig. 1A regarding reference number 106 (exponent processors) (as a maximum exponent detection unit); [0098] regarding Fig. 1 as described as N pairs of floating point values comprised of the floating point input, and the floating point coefficient, are processed simultaneously by N first stages, N second stages, and adder stages; [0072] regarding a central find exponent processor (112) receiving inputs from all of the exponent processors to generate a maximum exponent sum (164); [0079] regarding Exponent processor (104) of the N exponent processors summing exponents from the input (101) and the coefficient (103), each Exponent processor of the N exponent processors are connected to a shared find max exponent finder (112) which receives exponent sums from all N first pipeline stages and outputs the largest exponent from among all first stage exponent sums; Fig 4 regarding reference numbers 101 (input exponent), 103 (coefficient exponent), 104 (exponent processor using an adder), 422 (other stages), 112 (central max exponent finder), 164 (max exponent));
an alignment unit configured to align the magnitude bits of the numbers based on the maximum exponent sum (emax); (Fig. 1A regarding reference numbers 114 (mantissa), 106 (exponent processor), 115 (Exp_diff/shift amount), 110 (control/exponent registers), 118 (Exp_diff/shift amount), 122 (PCS processor) (as an alignment unit); Fig. 4 regarding reference numbers 164 (maximum exponent), 406 (exponent difference adjustment), 115 (exponent difference), and 110 (control/exponent registers) outputting 118 (exponent difference) based on 115(exponent difference); Fig. 5 regarding reference numbers 118 (exponent difference/shift amount), 114 (mantissa), 506 (shift processor); [0079] regarding initial difference 404 being the difference between the current exponent and the max exponent; [0080] regarding generating exp_diff output 115 based on initial difference 404; [0090] regarding shifting the mantissa based on the exponential difference (118));
and a processing unit configured to add the set of 'k' numbers concurrently to generate an output value. ([0098] regarding Fig. 1 as described as N pairs of floating point values comprised of the floating point input, and the floating point coefficient, are processed simultaneously by N first stages, N second stages, and adder stages (as a processing unit); Fig. 1A regarding reference numbers 114 (fraction outputs 16bXN), 122 ((PCS) Processor), 156 (integer form fractions), 154 (adder stage); Fig. 5 regarding the output as (yi); [0072] regarding the common adder stage (154) receiving integer form fractions from all of the MAC processors and forms the single accumulated floating point output value (148); [0087] regarding adder (124) as operating on 8 pairs of 32 bit values (8 pairs, meaning 16, k, total numbers); Fig. 1B regarding the adder stage (154) operating on the 8 pairs of values, adding the values to generate an output value (148) the single accumulated floating point output value; [0102] regarding pipeline stages operating concurrently).
With regards to claim 13, Finch teaches the hardware implementation as claimed in claim 12, as referenced above.
Finch further teaches:
further comprising a renormalizing unit configured to: renormalize the output value; and round the output value to represent the output value as a floating-point number. (Fig. 1B regarding normalizing the output value using reference number 146 (Normalize, Adjust, Round exponent); [0092] regarding a normalization and rounding step in generating the final floating point output from the adder stage 154).
With regards to claim 14, Finch teaches the hardware implementation as claimed in claim 12, as referenced above.
Finch further teaches:
wherein each number in the first set of k floating-point numbers ao, ai..., ak-1 comprises a mantissa (mai) having a bit length of 'p' bits and an exponent (eai) having a bit length of 'a' bits and each number in the second set of k floating-point numbers bo, bi..., bk-1 comprises a mantissa (mbi) having a bit length of 'q' bits and an exponent (ebi) having a bit length of 'b' bits. (Fig. 1A regarding input and coefficient values having a mantissa and an exponent; [0098] regarding Fig. 1 as described as N pairs of floating point values comprised of the floating point input, and the floating point coefficient, are processed simultaneously by N first stages, N second stages, and adder stages; Fig. 3 regarding the mantissa processor processing the mantissa of the input and coefficient values; [0078] regarding the mantissa processor (104) inputting a pair of 7 (bit) components from floating point input (101) and coefficient (103) (i.e, p=7, q=7); Fig. 4 regarding the exponent processor operating on the input exponent and coefficient exponent, each being 7 bits (i.e, a=7, b=7)).
With regards to claim 15, Finch teaches the hardware implementation as claimed in claim 12, as referenced above.
Finch further teaches:
wherein the multiplication unit comprises a plurality of multiplier units configured to multiply concurrently each mantissa (mai) with corresponding mantissa (mbi) to obtain an intermediate mantissa product (mabi). (Fig. 1A regarding input and coefficient values having a mantissa and input into the mantissa processor (as a multiplication unit); [0098] regarding Fig. 1 as described as N pairs of floating point values comprised of the floating point input, and the floating point coefficient, are processed simultaneously by N first stages, N second stages, and adder stages; Fig. 3 regarding the mantissa processor multiplying the mantissa of the input and coefficient values, and a result of the mantissa processor being 16 bits).
With regards to claim 16, Finch teaches the hardware implementation as claimed in claim 12, as referenced above.
Finch further teaches:
wherein the hardware implementation for performing a dot product operation emulates the precision obtained using separate multiplication and addition units, for performing dot product having an output mantissa bit length of P bits, by setting the mantissa bit length of 'r' bits as 'r= P+2' bits. (Fig. 1A regarding reference numbers 101 (input), and 103 (coeff) processed by reference number 104 (mantissa processor) and output from 104, 109 (fraction output)as 16bits (as 'r'); Fig. 3 regarding input and coefficient multiplied together generating a product; [0070]-[0073] regarding performing dot product operations on two N sets of numbers; [0070] regarding multiplying and accumulating the inputs by the coefficients, furthermore regarding [a1, a2, …, an]*[b1k, …, bnk] = [a1b1k + a2b2k + ... + anbnk]; As interpreted by the Examiner, r is equal to 16 bits (as referenced above), so, r = P + 2 becomes 16 = P + 2, P =14. Furthermore, emulation of the precision obtained using separate multiplication and addition units, for performing dot product having an output mantissa bit length of P bits is a natural consequence of setting the mantissa bit length of ‘r’ bits as ‘r=P+2’ bits).
With regards to claim 17, the Examiner notes that the limitation “emulates the precision obtained using fused multiplication and addition units for performing dot product having an output mantissa bit length of Q bits,” is not positively recited, and is recited as merely an intended result of the limitation “by setting the mantissa bit length of 'r' bits as 'r= max (Q+2, p+q+3)' bits.”. Therefore, the Examiner does not give patentable weight to the limitations of “emulates the precision obtained using fused multiplication and addition units for performing dot product having an output mantissa bit length of Q bits,” of claim 17.
Finch teaches the hardware implementation as claimed in claim 12, as referenced above.
Finch further teaches:
wherein the hardware implementation for performing a dot product operation emulates the precision obtained using fused multiplication and addition units for performing dot product having an output mantissa bit length of Q bits, by setting the mantissa bit length of 'r' bits as 'r= max (Q+2, p+q+3)' bits. (Fig. 1A regarding reference numbers 101 (input), and 103 (coeff) processed by reference number 104 (mantissa processor) and output from 104, 109 (fraction output)as 16bits (as 'r'); Fig. 3 regarding input and coefficient multiplied together generating a product; [0070]-[0073] regarding performing dot product operations on two N sets of numbers; [0070] regarding multiplying and accumulating the inputs by the coefficients, furthermore regarding [a1, a2, …, an]*[b1k, …, bnk] = [a1b1k + a2b2k + ... + anbnk]; As interpreted by the Examiner, r is equal to 16 bits (as referenced above), so, r = max (Q+2, p+q+3) becomes 16 = max(Q+2, p+q+3). Here, r is either Q+2 or p+q+3, whichever is larger. As referenced above, r is 16, so 16 = Q+2 OR 16 = p+q+3. As interpreted by the Examiner, Q+2 is larger, so 16=Q+2, which gives Q=14. Furthermore, emulation of the precision obtained using fused multiplication and addition units, for performing dot product having an output mantissa bit length of Q bits is a natural consequence of setting the mantissa bit length of ‘r’ as ‘r=max(Q+2, P+Q+3)’ bits).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Finch in view of Martin (U.S. Patent Application Publication 2019/0147327A1), hereinafter, “Martin”.
With regards to claim 19, Finch teaches:
the hardware implementation as set forth in claim 12. (as referenced above regarding claim 12).
Finch does not explicitly teach:
An integrated circuit definition dataset that, when processed in an integrated circuit manufacturing system, configures the integrated circuit manufacturing system to manufacture
However, Martin teaches:
An integrated circuit definition dataset that, when processed in an integrated circuit manufacturing system, configures the integrated circuit manufacturing system to manufacture (Fig. 9 and [0226] regarding a definition dataset input into a manufacturing system (1002) which processes the dataset and produces an integrated circuit)
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to combine Finch with Martin because Both Finch and Martin disclose multiply and accumulate operations using floating point values, and a dataset “when processed in an integrated circuit manufacturing system, causes the method of manufacturing hardware to be performed” (Martin:[0263]).
With regards to claim 20, Finch teaches:
a hardware implementation as set forth in claim 12. (as referenced above regarding claim 12).
Finch does not explicitly teach:
A non-transitory computer readable storage medium having stored thereon a computer readable dataset description of a hardware implementation that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit embodying the hardware implementation.
However, Martin teaches:
A non-transitory computer readable storage medium having stored thereon a computer readable dataset description of a hardware implementation that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit embodying the hardware implementation. ([0068] regarding non-transitory computer readable storage medium having stored a computer readable description of hardware that when processed in an integrated circuit manufacturing system, causes the manufacturing system to manufacture an integrated circuit embodying the hardware; Fig. 9 and [0226] regarding a definition dataset input into a manufacturing system (1002) which processes the dataset and produces an integrated circuit;)
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to combine Finch with Martin because Both Finch and Martin disclose multiply and accumulate operations using floating point values, a dataset “when processed in an integrated circuit manufacturing system, causes the method of manufacturing hardware to be performed” (Martin: [0263]), and a dataset “stored thereon a computer readable description of hardware as described herein that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit embodying the hardware” (Martin: [0068]).
Allowable Subject Matter
Claim 18 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, and 35 U.S.C. 101 rejections set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
With regards to claim 18, the applicant claims A method of performing dot product of an array of '2k' floating point numbers, k ≥ 3, using a hardware implementation, the array comprising:
a first set of k floating-point numbers ao, ai..., ak-1, and a second set of k floating-point numbers bo, b1...,bk-1, wherein the method comprises: receiving both sets of 'k' floating point numbers; multiplying each floating point number ai with a floating point number bi, each multiplication generating a first intermediate product number (zi') and a second intermediate product numbers (zi"), thereby generating 2k product numbers comprising k first intermediate product numbers (zi') and k second intermediate product numbers (zi"), each having a mantissa bit length of 'r+1' bits; creating a set of '2k' numbers comprising k first numbers (yi') and k second numbers (yi"), based on the 2k product numbers, each having a bit-length of 'n' bits obtained by adding both extra most-significant bits and extra least-significant bits to the mantissa bit length of the product numbers (zi and zi"), wherein the 'n' bits comprises a number of magnitude bits, wherein 'n' is r + 1 + ⌈log2(k)⌉ + ⌈log2(k - 1)⌉ + x bits, where x is an integer, and x ≥ 1; identifying a maximum exponent sum (emax) among k exponent sums (eabi), each exponent sum is the sum of exponents of the floating point number ai and the floating point number bi; aligning the magnitude bits of the numbers (yi' and yi") based on the maximum exponent sum (emax); and adding the set of '2k' numbers concurrently.
The primary reason for indication of allowable subject matter is the above italicized claim limitations in combination with the remaining claim limitations including intervening claims.
Finch discloses a system and a method for performing a dot product on 2k floating point numbers, with two ‘k’ input vectors (Fig. 1A; [0070]-[0073] regarding performing dot product operations on two N sets of numbers; [0098] regarding N=16, and the inputs as floating point). Finch further discloses multiplying each element of the first vector with a corresponding input from the second vector, and each output result of the multiplication having a mantissa length of ‘r’ bits (Fig. 1A regarding reference numbers 101 (input), and 103 (coeff) processed by reference number 104 (mantissa processor) and output from 104, 109 (fraction output)as 16bXN (16bits); Fig. 3 regarding input and coefficient multiplied together; [0070]-[0073] regarding performing dot product operations on two N sets of numbers; [0070] regarding multiplying and accumulating the inputs by the coefficients, furthermore regarding [a1, a2, …, an]*[b1k, …, bnk] = [a1b1k + a2b2k + ... + anbnk]; [0098] regarding Fig. 1 as described as N pairs of floating point values comprised of the floating point input, and the floating point coefficient, are processed simultaneously by N first stages, N second stages, and adder stages). Finch further discloses creating a set of ‘k’ numbers (yi) based on the product results, by adding extra most-significant and extra least-significant bits to the mantissa bit length (Fig. 1A regarding reference numbers 109 (fraction outputs 16bXN), 122 (Pad, Complement, Shift (PCS) Processor); Fig. 5 regarding reference number 502 (0s padding), and the output as (yi); [0088] regarding the PCS processor adding leading extra leading 0s, and extra trailing 0s to the mantissa input, padding the mantissa to 32bits; [0098] regarding Fig. 1 as described as N pairs of floating point values comprised of the floating point input, and the floating point coefficient, are processed simultaneously by N first stages, N second stages, and adder stages). Finch further discloses identifying a maximum exponent sum among k exponent sums, with each exponent sum being the sum of exponents from each corresponding pair of elements from the input vectors (Fig. 1A regarding reference number 106 (exponent processors); [0098] regarding Fig. 1 as described as N pairs of floating point values comprised of the floating point input, and the floating point coefficient, are processed simultaneously by N first stages, N second stages, and adder stages; [0072] regarding a central find exponent processor (112) receiving inputs from all of the exponent processors to generate a maximum exponent sum (164); [0079] regarding Exponent processor (104) of the N exponent processors summing exponents from the input (101) and the coefficient (103), each Exponent processor of the N exponent processors are connected to a shared find max exponent finder (112) which receives exponent sums from all N first pipeline stages and outputs the largest exponent from among all first stage exponent sums; Fig 4 regarding reference numbers 101 (input exponent), 103 (coefficient exponent), 104 (exponent processor using an adder), 422 (other stages), 112 (central max exponent finder), 164 (max exponent)). Finch further discloses aligning the magnitude bits of the created set of ‘k’ numbers, (yi), based on the maximum exponent sum (Fig. 1A regarding reference numbers 114 (mantissa), 106 (exponent processor), 115 (Exp_diff/shift amount), 110 (control/exponent registers), 118 (Exp_diff/shift amount), 122 (PCS processor); Fig. 4 regarding reference numbers 164 (maximum exponent), 406 (exponent difference adjustment), 115 (exponent difference), and 110 (control/exponent registers) outputting 118 (exponent difference) based on 115(exponent difference); Fig. 5 regarding reference numbers 118 (exponent difference/shift amount), 114 (mantissa), 506 (shift processor); [0079] regarding initial difference 404 being the difference between the current exponent and the max exponent; [0080] regarding generating exp_diff output 115 based on initial difference 404; [0090] regarding shifting the mantissa based on the exponential difference (118)). Finch further discloses adding the created set of numbers (yi) concurrently, ([0098] regarding Fig. 1 as described as N pairs of floating point values comprised of the floating point input, and the floating point coefficient, are processed simultaneously by N first stages, N second stages, and adder stages; Fig. 1A regarding reference numbers 114 (fraction outputs 16bXN), 122 ((PCS) Processor), 156 (integer form fractions), 154 (adder stage); Fig. 5 regarding the output as (yi); [0072] regarding the common adder stage (154) receiving integer form fractions from all of the MAC processors and forms the single accumulated floating point output value (148); [0087] regarding adder (124) as operating on 8 pairs of 32 bit values (8 pairs, meaning 16, k, total numbers); Fig. 1B regarding the adder stage (154) operating on the 8 pairs of values, adding the values to generate an output value (148) the single accumulated floating point output value; [0102] regarding pipeline stages operating concurrently). However, Finch fails to teach or suggest the italicized claim limitations in combination with the remaining claim limitations as referenced above.
Boswell et al. (U.S. Patent Application Publication 2018/0321938 A1), hereinafter, “Boswell”, discloses a system/method for dot product calculations on floating point values, multiplying a set of elements with a corresponding set of elements (Fig. 13; [0137]). Boswell further discloses each multiplication generating a first intermediate product and a second intermediate product (Fig. 13 regarding two outputs from each of the multipliers; [0139]); Bozwell further discloses identifying a maximum exponent and shifting/aligning each partial product based on the maximum exponent. However, Boswell fails to teach or suggest the italicized claim limitations in combination with the remaining claim limitations as referenced above. Boswell does not teach/suggest the two intermediate products each having a mantissa bit length of ‘r+1’ bits, they are instead referred to as simply two integers ([0139]). Furthermore, Boswell does not teach/suggest adding both extra most-significant bits and extra least significant bits t the mantissa bit length of the intermediate product numbers.
Lies (U.S. Patent Application Publication 2023/0214176 A1), hereinafter “Lies”, discloses a system/method of performing a floating point multiplication operations (Fig. 1) with the output of the multiplication being two intermediate outputs (Fig. 1 Sum and Carry; [0023]). Lies further discloses a first exponent calculator which determines the larger exponent of the inputs (Fig. 1 reference number 108). However, Lies fails to teach or suggest the italicized claim limitations in combination with the remaining claim limitations as referenced above.
Conclusion
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/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
/J.A.K./Examiner, Art Unit 2182
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