DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: Figure 3 illustrates box 305 within 301. However, the specification fails to describe what 305 is. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). See the rejection under 35 U.S.C. 112(a) below.
Claim Objections
Claims 1-20 are objected to because of the following informalities:
Claims 1-3, 9-11, and 18 uses the term “floating point” and “floating-point” interchangeably. For purposes of clarification, Examiner suggests amending the claims to either recite “floating point” or “floating-point” to be consistent.
Claim 4 line 1 “the method of performing a dot product” should be “the method of performing the dot product” as antecedently recited in claim 1 line 1.
Claim 6 line 1 "wherein identifying a maximum exponent sum" should be " wherein identifying the maximum exponent sum" as antecedently recited in claim 1 line 14.
Claim 6 line 3; claim 17 line 3-4 recites “k exponent sums (eabi) is obtained by summing exponent (eai) and exponent (ebi)”. “k exponent sums” refers to plural. Thus, Examiner interprets such limitation as k exponent sums (eabi) are obtained by summing exponent (eai) and exponent (ebi).
Claim 7 line 1 “wherein adding extra most-significant bits” should be “wherein adding the at least extra most-significant bits” as antecedently recited in claim 1 line 10-11.
Claim 7 line 1-2 “the bit length ‘r + log(k-1)+1’ of the product numbers (zi)” should be “the mantissa bit length ‘r + log(k-1)+1’ of the product numbers (zi)” as antecedently recited in claim 1 line 7.
Claim 8 line 1 “wherein adding at least extra most-significant bits” should be “wherein adding the at least extra most-significant bits” as antecedently recited in claim 1 line 10-11.
Claim 10 line 1-2 "wherein aligning the magnitude bits of the numbers (yi) to be based on the maximum exponent (emax)" should be "wherein aligning the magnitude bits of the set of numbers (yi) based on the maximum exponent sum (emax)" as antecedently recited in claim 1 line 17.
claim 11 line 5 “a plurality of multiplier” should be “a plurality of multipliers” as it recites multiple multipliers.
Claim 11 line 19 “the magnitude bits of the numbers” should be “the magnitude bits of the numbers (yi)” to clearly identify the magnitude bits corresponds to the numbers (yi) since the claim recites different instants of numbers, such as yi and zi.
Claim 14 line 1-2 “wherein the multiplication unit comprises a plurality of multiplier units” should be “wherein the multiplication unit comprises the plurality of multipliers” as antecedently recited in claim 11 line 5.
Claim 15 line 1 “wherein the hardware implementation for performing a dot product operation” should be “wherein the hardware implementation for performing the dot product” as antecedently recited in claim 11 line 1.
claim 16 line 2 “generate k product number (zi)” should be “generate k product numbers (zi) as antecedently recited in claim 11 line 8.
Claim 17 line 2-3 “identify a maximum exponent sum (emax) among k exponent sums (eabi)” should be “identify the maximum exponent sum (emax) among k exponent sums (eabi)” as antecedently recited in claim 11 line 16-17.
Dependent claims are also objection for inheriting the same deficiencies in which claims they depend on.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f), is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f):
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f), is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f), is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f), except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f), except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f), because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“a format conversion unit" in claim 11. Figures 3 and 5 illustrate a format conversion unit 302 as a black box without sufficient structure to perform the claimed function. [0079-0080] describes what a format conversion unit does, but does not describe the sufficient structure that performs such function of conversion to create numbers.
“a maximum exponent detection unit” in claim 11, 17. Figures 3 and 5 illustrates a maximum exponent detection unit 304 as a black box without sufficient structure to perform the claimed function. [0095] describes the unit 304 detects using various methods or functions, such as a binary tree structure, [00110] describes the unit 304 may comprise two maximum function logics to identify the maximum exponent sum. However, the specification fails to describe sufficient structure within the maximum exponent detection unit to perform the claimed function.
“an alignment unit” in claim 11. Figure 5 illustrates implementation of alignment unit 306 having a plurality of subtractors 505 and shifters 506 to calculate the difference value and shift the magnitude bits based on the calculated difference value [00117-00118].
“a processing unit” in claim 11. Figures 3 and 5 illustrate the processing unit 308 as an adder 508 [00125].
“a renormalizing unit” in claim 12. Figures 3 and 5 illustrate renormalizing unit 310 comprises a shifter 510a to generate normalized output nk [00127]. However, the specification fails to provide sufficient structure to perform the function of rounding. Accordingly, the specification fails to provide sufficient structure to perform the entire claimed functions of renormalizing and rounding.
“the multiplication unit” in claim 16. Figure 5 illustrates the multiplication unit 301 having a plurality of multipliers 501 as black boxes without sufficient structure to perform the claimed function of generating k product numbers by rounding or padding.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f), it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f), applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f).
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 line 19; claim 11 line 21 recite “the set of ‘k’ numbers concurrently”. There is lack of antecedent basis and it is unclear whether the set of ‘k’ numbers is referring to the set of k number (yi) or another set of ‘k’ numbers. Specification, figure 5 illustrates a processing unit 508 configures to add a set of k numbers vi [00125], and also described in step 710 of [00141]. For examination purposes, Examiner interpret such limitation based on the specification as, “a set of ‘k’ numbers (vi) concurrently”.
Claim 1 line 11; claim 8 line 1-3; claim 11 line 13 recite “the bit length of the product numbers”. There is lack of antecedent basis for such limitation of the bit length and it is unclear whether the bit length is referring to a bit length or the mantissa bit length as antecedently recited in claim 1 line 7. For examination purposes, Examiner interprets as "the mantissa bit length of the k product numbers (zi)" as antecedently recited.
Claim 1 line 15; claim 11 line 17; claim 18 line 17 recite “the sum of exponents”. There is lack of antecedent basis for such limitation. For examination purposes, Examiner interprets such limitation as “a sum of exponents”
Claim 4 line 2; claim 15 line 2 recite "the precision". There is lack of antecedent basis for such limitation. For examination purposes, Examiner interprets as "a precision".
Claim 5 line 3; claim 16 line 4 recite “the bits of the intermediate mantissa product (mabi)”. There is lack of antecedent basis for such limitation. For examination purposes, Examiner interprets as “bits of the intermediate mantissa product (mabi)”.
Claim 5 line 5-6; claim 16 line 6 recite “the bit length of the intermediate mantissa product (mabi)”. There is lack of antecedent basis for such limitation. For examination purposes, Examiner interprets as “a bit length of the intermediate mantissa product (mabi)”.
Claim 6 line 2 recites "the maximum value". There is lack of antecedent basis for such limitation. For examination purposes, Examiner interprets as "a maximum value".
claim 7 line 3 recite “the most-significant bits”. there is lack of antecedent basis for such limitation. For examination purposes, Examiner interprets as “the at least extra most-significant bits”.
Claim 10 line 4 recites "the difference (ed)". There is lack of antecedent basis for such limitation. for examination purposes, Examiner interprets as "a difference (ed)"
Claim 10 line 6 "the LSB side". There is lack of antecedent basis for such limitation. For examination purposes, Examiner interprets such limitation as "a least significant bit (LSB) side".
Claim 16 line 4 recites “The hardware implementation as claimed in claim 11 … the intermediate mantissa product (mabi)”. There is lack of antecedent basis for such limitation as claim 11 does not antecedently recite intermediate mantissa product (mabi), but claim 14 first introduces an intermediate mantissa product. For examination purposes, Examiner interprets claim 16 as depends on claim 14.
Claim 18 line 8-10 recites “comprising k first intermediate product numbers (zi’) and k second intermediate product numbers (zi’’), each having a bit length of ‘r + log(k-1)+2 bits”. It is unclear whether the term “each” is referring to each of zi’ or each of zi’’ or each of zi’ and zi’’. For examination purposes, Examiner interprets such limitation as each of zi’ and zi’’.
Claim 18 line 11-12 recites “comprising k first number (yi’) and k second numbers (yi’’), based on the 2k product numbers, each having a bit-length of ‘n’ bits. It is unclear whether the term “each” is referring to each of yi’ or each of yi’’ or each of yi’ and yi’’. For examination purposes, Examiner interprets such limitation as each of yi’ and yi’’.
claim 18 line 13 recites “the bit length of the product numbers (zi and zi’’)”. There is lack of antecedent basis for such limitation of the bit length of the product numbers and zi. For examination purposes, examiner interprets such limitation as the mantissa bit length of the 2k product numbers (zi’ and zi’’).
Claim 18 line 14 recites “the ‘n’ bits”. it is unclear whether the ‘n’ bits is referring to the n bits of k first number (y’) or the n bits of k second number (y’’) or both. For examination purposes, Examiner interprets such limitation as referring to the n bits of y’ and y’’.
Claim 18 line 21 recites “adding the set of ‘2k’ numbers concurrently” There is lack of antecedent basis and it is unclear whether the set of ‘2k’ numbers is referring to the number (yi’ and yi’’) or another set of ‘2k’ numbers. Specification, figure 5 illustrates a processing unit 508 configures to add a set of k numbers vi [00125], and also described in step 710 of [00141]. For examination purposes, Examiner interpret such limitation based on the specification as, “add a set of ‘2k’ numbers concurrently”.
Claim 20 line 4-5 recites “the hardware implementation”. It is unclear whether such limitation is referring to the hardware implementation recited in claim 20 line 2 or the hardware implementation in claim 11 line 1. For examination purposes, examiner interprets such limitation as the hardware implementation recited in claim 20 line 2.
Claims 11-12, 16-17 recite limitation “a format conversion unit", "a maximum exponent detection unit”, “a renormalizing unit”, “the multiplication unit” invokes 35 U.S.C. 112(f). However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function. As explained above in the Claim Interpretation section, that claim recites hardware implementation comprises these units, which invoke 112(f), but the specification fails to provide sufficient structure to perform the entire claimed function. Specification Figures 3 and 5 a format conversion unit 302, a maximum exponent detection unit 304, renormalizing unit 310, the multiplication unit 301 having a plurality of multipliers 501 as black boxes without sufficient structure to perform the entire claimed function. [0079-0080] describes what a format conversion unit does, but does not describe the sufficient structure that performs such function of conversion to create numbers. [0095] describes the unit 304 detects using various methods or functions, such as a binary tree structure, [00110] describes the unit 304 may comprise two maximum function logics to identify the maximum exponent sum. However, the specification fails to describe sufficient structure within the maximum exponent detection unit to perform the claimed function. [00127] describes a shifter 510a to generate normalized output nk, but does not provide sufficient structure to perform the function of rounding. Moreover, claim 16 requires the multiplication unit to generating product numbers by rounding or padding, but the plurality of multipliers 501 in figure 5 are merely illustrated as black boxes without sufficient structure to perform the claimed function of generating k product numbers by rounding or padding. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b).
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f);
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Dependent claims are also rejected for inheriting the same deficiencies in which claims they depend on.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 11-17 and 19-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 11-12, 16-17 recite limitation “a format conversion unit", "a maximum exponent detection unit”, “a renormalizing unit”, “the multiplication unit” invokes 35 U.S.C. 112(f). However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function. See explanation above in 112(b).
Dependent claims are also rejected for inheriting the same deficiencies in which claims they depend on.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 19 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because the claim is directed to an integrated circuit definition dataset, which is merely information or data (e.g., data per se) being received as illustrated in figure 10. [00176] also describes that an integrated circuit definition dataset may be in form of computer code (e.g., software per se). Thus, it does not fall within a statutory category.
Claims 1-10, and 18 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Claim 1 recites a method of performing dot product
Under Prong One of Step 2A of the USPTO current eligibility guidance (MPEP 2106), the claim recites limitations cover mathematical calculations, relationship, and/or formula, such as a method of performing dot product of an array of '2k' floating point numbers, k
≥
3, the array comprising a first set of k floating-point numbers ao, a1..., ak-1, and a second set of k floating-point numbers bo, b1..., bk-i, wherein the method comprises: multiplying each floating point number al with a floating point number bi to generate k product numbers (zi), each product number (zi) having a mantissa bit length of 'r+ log (k- 1) +1' bits (see at least figure 7 step 702 performing multiplication of floating point numbers and see equation describes in [00100]); creating a set of 'k' numbers (yi) based on the k product numbers (zi), the numbers (yi) having a bit-length of 'n' bits obtained by adding at least extra most-significant bits to the bit length of the product numbers (zi), wherein the 'n' bits comprises a number of magnitude bits, wherein 'n' is r + [log2(k)] + [log2(k - 1)1 + x bits, where x is an integer, and x > 1 (see at least figure 7 step 704 describes converting data from one format to another format to create a set of numbers having n bits [0082]); identifying a maximum exponent sum (emax) among k exponent sums (eabi), each exponent sum is the sum of exponents of the floating point number al and the floating point number bi (see at least figure 7 step 706 describes finding a maximum exponent among the exponents, also see description in [00110]); aligning the magnitude bits of the numbers (yi) based on the maximum exponent sum (emax) (see at least figure 7 step 708 describes aligning bit by performing subtracting and shifting as mathematical equation described in [00123]); and adding the set of 'k' numbers (see at least equation described in [00125] that performs summation operation). Therefore, the claim includes limitations that fall within the “Mathematical Concepts” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Under Prong Two of Step 2A, this judicial exception is not integrated into a practical application. The claim additionally recites a hardware implementation. However, the additional element is recited at a high level of generality, i.e., as a generic system performing a computer function of processing data. Moreover, the claim recites the step of receiving both sets of ‘k’ floating point numbers and adding concurrently, which are considered as insignificant extra solution activity because the step of receiving data is mere data gathering and the concept of adding concurrently or parallel is well known. Such additional elements fail to provide a meaningful limitation on the judicial exception, and amount to no more than mere instructions to apply the exception using a computer component. Thus, the claim is directed to an abstract idea.
Under Step 2B, as discussed with respect to Prong Two of Step 2A, the additional elements in the claim amount no more than mere instructions to apply the exception using a computer component. The same conclusion is reached in step 2B, i.e., mere instructions to apply an exception on a computer component cannot integrate a judicial exception into a practical application at step 2A or provide an inventive concept that is furnished by an element or combination of elements that is recited in the claim in addition to (beyond) the judicial exception. The step of receiving both set ‘k’ floating point numbers (e.g., data) and adding concurrently are considered to be insignificant extra-solution activities in step 2A, and are determined to be well-understood, routine, conventional activities in the field. Court decisions cited in MPEP 2106.05(d)(II) section (i), indicate that mere receiving or transmitting data over a network, is well-understood, routing, conventional function when it is claimed in a merely generic manner and see at least Hennessy, John L., et al. Computer Architecture : A Quantitative Approach, Elsevier Science & Technology, page 108-110 describes add operations being performed in parallel using single instruction multiple data, wherein the data type is also floating point number. Thus, the additional element fails to ensure the claim as a whole amount to significantly more than the judicial exception itself. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 2 further recites wherein each number in the first set of k floating- point numbers ao, ai..., ak-i comprises a mantissa (mai) and an exponent (eal) and each number in the second set of k floating-point numbers bo, bi..., bk-i comprises a mantissa (mbi) and an exponent (ebi), where each mantissa (mai) is having a bit length of 'p' bits and each mantissa (mbi) is having a bit length of 'q' bits. Such limitations cover mathematical calculations, relationship, and/or formula (merely describes the floating point numbers being operated on having mantissa and exponent bits). The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 3 further recites wherein multiplying each floating point number al with the corresponding floating point number bi comprises multiplying mantissa (mai) and mantissa (mbi) to obtain an intermediate mantissa product (mabi). Such limitations cover mathematical calculations, relationship, and/or formula (performing multiplication operation on the mantissa of the floating point numbers). The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 4 further recites wherein the method of performing a dot product emulates the precision obtained using separate multiplication and addition units for performing dot product having an output mantissa bit length of P bits by setting the value of 'r' bits as 'r= P+1-log(k-1)'. Such limitation of performing dot product having an output mantissa bit length of P bits by setting the value of r bits as r = P+1-log(k-1)’ covers mathematical calculations, relationship, and/or formula (setting values for output mantissa bits), and the limitation of emulating the precision obtained using separate multiplication and addition units is merely recited as a result of performing the abstract idea (e.g., method for performing dot product) as recited in the claim. The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 5 further recites wherein generating k product numbers (zi) having the mantissa bit length of 'r+ log (k-1) +1' bits comprises: rounding, the bits of the intermediate mantissa product (mabi) to r+ log (k-1) +1 bits, if p+q+2>r+ log (k-1) +1 bits; or padding, extra least-significant bits to the bit length of the intermediate mantissa product (mabi) to generate r+ log (k-1) +1 bits, if p+q+2 < r+ log (k-1) +1 bits. Such limitations cover mathematical calculations, relationship, and/or formula (generating product numbers by performing rounding or padding, which are mathematical operations). The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 6 further recites wherein identifying a maximum exponent sum (emax) includes identifying the maximum value among k exponent sums (eabi) where k exponent sums (eabi) is obtained by summing exponent (eal) and exponent (ebi). Such limitations cover mathematical calculations, relationship, and/or formula (identifying maximum exponent). The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 7 further recites wherein adding extra most-significant bits to the bit length 'r+ log (k-1) +1' of the product numbers (zi) comprises adding at least [log2(k)] number of the most-significant bits. Such limitations cover mathematical calculations, relationship, and/or formula (performing adding bits to generate numbers yi having n bits). The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 8 further recites wherein adding at least extra most-significant bits to the bit length of the product numbers (zi) further comprises adding one or more least- significant bits to the bit length of the product numbers (zi). Such limitations cover mathematical calculations, relationship, and/or formula (performing adding bits to generate numbers yi having n bits). The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 9 further recites wherein the method further comprises: calculating an output value by processing 'k' numbers (yi); renormalizing the output value; and rounding the output value to represent the output value as a floating-point number. Such limitations cover mathematical calculations, relationship, and/or formula (see at least [00125]-[00127] describes the equations to calculate output o based on vi, which is generated based on processing yi, and performing renormalizing and rounding). The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 10 further recites wherein aligning the magnitude bits of the numbers (yi) to be based on the maximum exponent (emax) comprises the steps of, for each floating-point number (i): calculating the difference (ed) between the maximum exponent sum (emax) and each exponent sum (eabi); and shifting the magnitude bits of the corresponding number (yi), to the LSB side, based on the calculated difference (ed). Such limitations cover mathematical calculations, relationship, and/or formula (performing subtraction to find the difference and shifting to generate vi as described in [00123]). The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 18 recites a method claim having similar limitations as claim 1. Thus, it is rejected for the same reasons.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 6-14, and 17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Finch - US 20220405051.
Regarding claim 1, Finch teaches a method of performing dot product of an array of '2k' floating point numbers, k
≥
3, using a hardware implementation, the array comprising a first set of k floating-point numbers ao, a1..., ak-1, and a second set of k floating-point numbers bo, b1..., bk-I (Finch, figure 1A illustrates a unit element 100 [i.e., a hardware implementation] to perform dot product [0070] of an array of 2N floating point number, wherein N
≥
3, [0098] describe N pairs of floating point wherein N = 16, thus the array comprising 16 inputs [i.e., a first set of N floating point numbers] and 16 coefficients [i.e., a second set of N floating point numbers]), wherein the method comprises:
receiving both sets of 'k' floating point numbers (Finch figure 1A illustrates receiving of both set of N inputs and coefficients);
multiplying each floating point number al with a floating point number bi to generate k product numbers (zi) (Finch, figure 1A N mantissa processors to perform multiplication on each pair of input and coefficient to generate N fraction output [i.e., k product numbers (zi)), each product number (zi) having a mantissa bit length of 'r+ log (k- 1) +1' bits (Finch, figures 1 and 3 illustrate each fraction output having 16 bit mantissa length, which is r + log(16-1) +1, which is 11+4+1. Thus, r is 11);
creating a set of 'k' numbers (yi) based on the k product numbers (zi), the numbers (yi) having a bit-length of 'n' bits obtained by adding at least extra most-significant bits to the bit length of the product numbers (zi) (Finch figure 1A illustrates N fraction outputs 109 is fed into the PCS processor 122, and figure 5 further illustrates PCS processor having a 0s padding processor 502 [0088] describes mantissa 16 bits is padded to 32 bits by zero padding leading 0s, which is padding the most significant bits. Thus, creating a set of N padded numbers [i.e., a set of k numbers (yi)] based on the fraction output, wherein the padded mantissa having a bit length of 32 bit [i.e, n bits]), wherein the 'n' bits comprises a number of magnitude bits, wherein 'n' is r + [log2(k)] + [log2(k - 1)] + x bits, where x is an integer, and x
≥
1 (Finch [0088] describes padded mantissa having length of 32 bits, which is equivalent to r + [log2(k)] + [log2(k - 1)] + x bits, where r = 11, k =16 x = 13, which is 11 + 4 + 4 + 13 = 32 );
identifying a maximum exponent sum (emax) among k exponent sums (eabi), each exponent sum is the sum of exponents of the floating point number al and the floating point number bi (Finch, figures 1A and figure 4 illustrate implementation of N exponent processors, wherein a central max exponent finder [0072] identify a maximum exponent max_exp [i..e, emax] among N exponent sums, each exponent sum is calculated by adding exponent input and exponent coefficient as illustrated in 104);
aligning the magnitude bits of the numbers (yi) based on the maximum exponent sum (emax) (Finch, figure 1A and 5 [0091] illustrate implementation of N PCS processors that having a shift processor to align the magnitude bits of padded mantissa outputs [i.e., the numbers (yi)] based on a exp difference, which is calculated based on max_exp [i.e., emax]. Also see figure 7C illustrates padded mantissa output is shifted by EXP_DIFF when sign is not 1); and
adding the set of 'k' numbers concurrently (Finch figure 1A [0087] describes the N output of the PCS processor [i.e., the set of k numbers] are added using adder 124. [0102] also describes that N pipeline stages operating concurrently).
Regarding claim 2, Finch further teaches the method as claimed in claim 1, wherein each number in the first set of k floating- point numbers ao, ai..., ak-i comprises a mantissa (mai) and an exponent (eal) and each number in the second set of k floating-point numbers bo, bi..., bk-i comprises a mantissa (mbi) and an exponent (ebi), where each mantissa (mai) is having a bit length of 'p' bits and each mantissa (mbi) is having a bit length of 'q' bits (Finch figure 1A [0073] describes N = 16, thus, 16 floating point input 101 terms and 16 floating point coefficient 103 term, each having 1 sign bit, 8 exponent bits and 7 mantissa bits [i.e., p and q bits are equal]).
Regarding claim 3, Finch teaches the method as claimed in claim 2, wherein multiplying each floating point number al with the corresponding floating point number bi comprises multiplying mantissa (mai) and mantissa (mbi) to obtain an intermediate mantissa product (mabi) (Finch figures 1A and 3 illustrate implementation of mantissa processor having multiplier that multiply the mantissa of each input with a corresponding coefficient to obtain 16b fraction output [i.e., an intermediate mantissa product]).
Regarding claim 6, Finch teaches the method as claimed in claim 1, wherein identifying a maximum exponent sum (emax) includes identifying the maximum value among k exponent sums (eabi) where k exponent sums (eabi) is obtained by summing exponent (eal) and exponent (ebi) (Finch figure 4 illustrates implementation of exponent processor, wherein the central max exponent finder identifies the max_exp among N exponent sums [i.e., N=k] from N stage, where the N exponent sums are obtained by adding each summing exponent from input and coefficient as illustrated in 104).
Regarding claim 7, further teaches the method as claimed in claim 1, wherein adding extra most-significant bits to the bit length 'r+ log (k-1) +1' of the product numbers (zi) comprises adding at least [log2(k)] number of the most-significant bits (Finch figures 1A [0088] describes padding mantissa outputs from 16 to 32 bit by zero padding the most significant bits, [0090] describes that for N = 16, an optimal padding of four [i.e., log2(16)] prepended leading 0s is sufficient to prevent an overflow error.)
Regarding claim 8, Finch further teaches the method as claimed in claim 1, wherein adding at least extra most-significant bits to the bit length of the product numbers (zi) further comprises adding one or more least-significant bits to the bit length of the product numbers (zi) (Finch figures 1A [0088] describes padding mantissa outputs from 16 bit to 32 bit by adding trailing 0s [i.e., one or more least significant bits]).
Regarding claim 9, Finch further teaches the method as claimed in claim 1, wherein the method further comprises:
calculating an output value by processing 'k' numbers (yi) (Finch figures 1A and 1B illustrate the adder stage 154 that calculate an integer form fraction 168 by processing N numbers padded mantissa [i.e., yi]);
renormalizing the output value; and rounding the output value to represent the output value as a floating-point number (Finch figure 1B [0057] describes normalize and rounding block 146 to represent the output as 16b floating point).
Regarding claim 10, Finch further teaches the method as claimed in claim 1, wherein aligning the magnitude bits of the numbers (yi) to be based on the maximum exponent (emax) (Finch figures 5 and 7C illustrates the PCS processor having a shift processor 506 that aligns the padded number [i.e., yi] based on the EXP_DIFF calculated from the max _exp) comprises the steps of, for each floating-point number (i):
calculating the difference (ed) between the maximum exponent sum (emax) and each exponent sum (eabi) (Finch figure 4 illustrates exponent processor having diff adj component 406 to calculate exp_diff [i.e., ed] between exp_max and each exponent sum as described in figure 7A step 718); and shifting the magnitude bits of the corresponding number (yi), to the LSB side, based on the calculated difference (ed) (Finch [0091] describes the padded mantissa is shifted to the right [i..e, the LSB side] based on the exp_diff [i..e, ed]).
Regarding claim 11, Finch teaches a hardware implementation for performing dot product of an array of '2k' floating point numbers, k
≥
3, the array comprising a first set of k floating-point numbers ao, ai..., ak-1, and a second set of k floating-point numbers bo, b1..., bk-i, wherein the hardware implementation (Finch, figure 1A illustrates a unit element 100 [i.e., a hardware implementation] to perform dot product [0070] of an array of 2N floating point number, wherein N
≥
3, [0098] describe N pairs of floating point wherein N = 16, thus the array comprising 16 inputs [i.e., a first set of N floating point numbers] and 16 coefficients [i.e., a second set of N floating point numbers] comprises: a multiplication unit comprising a plurality of multiplier (Finch figure 1A illustrates N mantissa processors each having a multiplier as illustrated in figure 3. Thus, such N mantissa processors correspond to a multiplication unit comprising a plurality of multipliers) configured to:
receive both sets of 'k' floating point numbers (Finch figure 1A illustrates receiving of both set of N inputs and coefficients);
multiply each floating point number al with a floating point number bi to generate k product numbers (zi) (Finch, figure 1A N mantissa processors to perform multiplication on each pair of input and coefficient to generate N fraction output [i.e., k product numbers (zi)), each product number (zi) having a mantissa bit length of 'r+ log (k-1) +1' bits (Finch, figures 1 and 3 illustrate each fraction output having 16 bit mantissa length, which is r + log(16-1) +1, which is 11+4+1. Thus, r is 11);
a format conversion unit (Finch figures 1A and 5 illustrate implementation of N PCS processors, wherein each PCS processor includes a padding processor 502. Thus a plurality of padding processors 502 corresponds to a format conversion unit]) configured to: create a set of 'k' numbers (yi) based on the k product numbers (zi), the numbers (yi) having a bit-length of 'n' bits obtained by adding at least extra most- significant bits to the bit length of the product numbers (zi) (Finch figure 1A illustrates N fraction outputs 109 is fed into the PCS processor 122, and figure 5 further illustrates PCS processor having a 0s padding processor 502 [0088] describes mantissa 16 bits is padded to 32 bits by zero padding leading 0s, which is padding the most significant bits. Thus, creating a set of N padded numbers [i.e., a set of k numbers (yi)] based on the fraction output, wherein the padded mantissa having a bit length of 32 bit [i.e, n bits]), wherein the 'n' bits comprises a number of magnitude bits, wherein 'n' is r + [log2(k)] + [log2(k - 1)] + x bits, where x is an integer, and x
≥
2 (Finch [0088] describes padded mantissa having length of 32 bits, which is equivalent to r + [log2(k)] + [log2(k - 1)] + x bits, where r = 11, k =16 x = 13, which is 11 + 4 + 4 + 13 = 32 );
a maximum exponent detection unit (Finch figures 1A and figure 4 illustrates a central max exponent finder 112 [i.e., a maximum exponent detection unit]) configured to identify a maximum exponent sum (emax) among k exponent sums (eabi), each exponent sum is the sum of exponents of the floating point number al and the floating point number bi (Finch, figures 1A and figure 4 describes the central max exponent finder [0072] identifies a maximum exponent max_exp [i..e, emax] among N exponent sums, each exponent sum is calculated by adding exponent input and exponent coefficient as illustrated in 104);;
an alignment unit (Finch, figures 1A, 4, and 5 illustrates N PCS processors and N exponent processors, each having a different adj 406 and shift processor 506. Thus, the plurality of 406 and 506 correspond to an alignment unit) configured to align the magnitude bits of the numbers based on the maximum exponent sum (emax) (Finch, figure 1A and 5 [0091] illustrate implementation of each PCS processor includes a shift processor to align the magnitude bits of padded mantissa outputs [i.e., the numbers (yi)] based on a exp difference, which is calculated based on max_exp [i.e., emax]. Also see figure 7C illustrates padded mantissa output is shifted by EXP_DIFF when sign is not 1); and
a processing unit (Finch figure 1A adder stages 124 [i..e, a processing unit]) configured to add the set of 'k' numbers concurrently to generate an output value (Finch figure 1A [0087] describes the N output of the PCS processor [i.e., the set of k numbers] are added using adder 124. [0102] also describes that N pipeline stages operating concurrently to generate integer form fraction 168 [i.e., an output value] see figure 1B).
Regarding claim 12, Finch further teaches hardware implementation as claimed in claim 11, further comprising a renormalizing unit configured to: renormalize the output value; and round the output value to represent the output value as a floating-point number (Finch figure 1B [0057] describes normalize and rounding block 146 to represent the output integer form factions 168 as 16b floating point)).
Claims 13-14, and 17 recite apparatus claims that would practice the method claims 2-3, and 6. Thus, they are rejected for the same reasons.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Finch in view of Martin - US 20190147327
Regarding claim 19¸ Finch teaches a hardware implementation as set forth in claim 11, but Finch does not teach an integrated circuit definition dataset that, when processed in an integrated circuit manufacturing system, configures the integrated circuit manufacturing system to manufacture the hardware implementation as set forth in claim 11. However, Martin teaches an integrated circuit definition dataset that, when processed in an integrated circuit manufacturing system, configures the integrated circuit manufacturing system to manufacture a hardware implementation (Martin figure 9 illustrates an integrated circuit (IC) manufacturing system 1002 receives an IC definition dataset and configured to manufacture a hardware implementation)
It would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to represent the hardware implementation of Finch as the IC definition dataset taught by reference B to facilitate fabrication of the hardware implementation using the integrated circuit manufacturing system, thereby enabling the hardware implementation to be reliably reproduced as an integrated circuit. This modification would have been obvious because both reference discloses hardware implementation for performing floating point operation, such as multiply and accumulate operation.
Regarding claim 20, Finch teaches a hardware implementation of as set forth in claim 11, but Finch does not teach a non-transitory computer readable storage medium having stored thereon a computer readable dataset description of a hardware implementation, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit embodying the hardware implementation. However, Martin teaches a non-transitory computer readable storage medium having stored thereon a computer readable dataset description of a hardware implementation, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit embodying the hardware implementation (Martin figure 9 [0068] non-transitory computer readable storage medium having stored thereon a computer readable description of hardware as described herein that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit embodying the hardware)
It would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to store the hardware implementation of Finch on the non-transitory computer readable storage medium taught by Martin to facilitate automated manufacture of the integrated circuit and to permit the reuse of the hardware description throughout the integrated circuit design and fabrication process, thus reducing redesign effort. This modification would have been obvious because both reference discloses hardware implementation for performing floating point operation, such as multiply and accumulate operation.
Allowable Subject Matter
Claims 4-5 and 15-16 would be allowable if rewritten to overcome the rejection(s) under claim objections, rejections under 35 U.S.C. 112(b), 112(a), and 101, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claim 18 would be allowable if rewritten or amended to overcome the claim objections, rejections under 35 U.S.C. 112(b), and 101, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 4-5, 15-16, and 18, the prior art of records does not teach or suggest a combination of limitations, such as wherein the method of performing a dot product emulates the precision obtained using separate multiplication and addition units for performing dot product having an output mantissa bit length of P bits by setting the value of 'r' bits as 'r= P+1-log(k-1)' as required in claims 4 and 15, or generating k product numbers (zi) having the mantissa bit length of 'r+ log (k-1) +1' bits comprises: rounding, the bits of the intermediate mantissa product (mabi) to r+ log (k-1) +1 bits, if p+q+2>r+ log (k-1) +1 bits; or padding, extra least-significant bits to the bit length of the intermediate mantissa product (mabi) to generate r+ log (k-1) +1 bits, if p+q+2 < r+ log (k-1) +1 bits as required in claims 6 and 16; or a combination of limitations in claim 18, such as multiplying each floating point numbers a and b to generate first and second intermediate product numbers zi’ and zi’’, each having a bit length of r + log (k-1)+2 bits and create 2k numbers yi’ and yi’’ having n bits as r + 1 +[log2(k)] +log2(k-1)+x.
Finch - US 20220405051 teaches a system and method for performing floating point dot product using multiplier and accumulator. Figure 1 illustrates a system for processing pairs of plurality of operands, such as 16 input and 16 coefficient, each having 16 bit floating point precision, the N stages perform mantissa multiplication, then pad the results to 32 bits by prepending and appending 0s, and align the padded results based on determined maximum exponent, then add the padded result and normalize and round the added result to generate floating point value. However, Finch does not teach or suggest the combination of limitations as described above.
Brooks - US 20260161357 teaches a system and method for performing dot product on floating point numbers as illustrated in figure 7, wherein the method receives operands as floating point numbers and perform multiplication on the operands to generate product numbers 702, which are fed into product converter 514 to extend the mantissa bit of the products to 33b to preserve precision and prevent bits from being shifted out of the mantissa during alignment. The method further aligns the products and add the aligned converted products to generate a sum 516. However, Brooks does not suggest or teach the combination of limitations as described above.
Heddes - US 20190065146 teaches a system and method for performing floating point operations as illustrated in figure 3, wherein the method includes receiving floating point numbers, multiply using mantissa bits to generate 22 bit product, and convert the 22 bit product into 31 bit as illustrated in 312 by adding zeros bits to the most and least significant bit. The method further teaches a shift right operation to align extended product and perform an add operation. However, Heddes does not suggest or teach the combination of limitations as described above.
Lies - US 20230214176 teaches a method and system for performing fused multiply-accumulate operation on floating point numbers as illustrated in figure 1. The system includes a multiplier to generate product of AB, a shift calculator that determine the shift amount to align C and product AB, a compressor to add the shifted C and product AB, a normalizer and rounding to perform normalizing and rounding operation. However, Lies does not suggest or teach the combination of limitations as described above.
Conclusion
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