DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim s 1-8 , 12-15, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication No. 2019/0317196 ("Denham") in view of U.S. Patent Publication No. 2017/0069677 (" Saruwatari "). Regarding claim 1 , Denham discloses an apparatus comprising: a ground voltage node (304, Fig. 2); a detector voltage node (301, Fig. 2); a photodetector (302, Fig. 2) including a first detector terminal (203, Fig. 2) and a second detector terminal (306, Fig. 2), the photodetector configured to convert received light to an electrical signal (inherent function of a photodetector, see also Abstract); an isolation n-channel field effect transistor (201, Fig. 2, can be an n-channel transistor, see paragraph [0039], 201 can, for example, be a, “N transfer gate” which use NMOS transistors, further, under the broadest reasonable interpretation, the term “isolation” is given its plain meaning, i.e. all transistors are isolation transistors because they are switches that can connect/disconnected to a circuit, the term is merely a label that has no limiting effect as there is no structure/functional language that specifically differentiates an isolation transistor from any other transistor) including an isolation drain, an isolation source, and an isolation gate (see Fig. 2, transistor 201 has a source, drain, and gate electrodes, like all transistors do), the isolation drain electrically coupled to the detector voltage node (terminal connected to 301, Fig. 2), the isolation source electrically coupled to the first detector terminal (terminal connected to 203, Fig. 2); and a bias voltage (202, Fig. 2, paragraph [0029]) electrically coupled to the isolation gate (gate of 201, Fig. 2). Denham does not explicitly disclose that the bias voltage is selected such that the isolation nFET operates in a saturation region. However, Saruwatari discloses a bias voltage (BIAS, and 341, Fig. 42, see claim 17) is selected such that the isolation transistor (243, Fig. 42) operates in a saturation region (paragraphs [0159]-[0160]). It would have been obvious to one of ordinary skill in the art before the effective filing date to select a bias voltage such that the isolation transistor operates in a saturation region as disclosed by Saruwatari in the device of Denham in order to help filter out undesired signals in the circuit. Regarding claim 2 , Denham in view of Saruwatari discloses the apparatus of claim 1, and Denham further discloses a supply capacitor (204, Fig. 2) including a first supply capacitor terminal (+ terminal, Fig. 2) and a second supply capacitor terminal (other terminal, Fig. 2), the first supply capacitor terminal (+ terminal, Fig. 2) electrically coupled to the first detector terminal (203, Fig. 2) and the second supply capacitor terminal electrically coupled to the ground voltage node (304, Fig. 2, paragraph [0029]). Regarding claim 3 , Denham in view of Saruwatari discloses the apparatus of claim 1, and Saruwatari further discloses a gate capacitor (341, Fig. 42) including a first gate capacitor terminal and a second gate capacitor terminal (see Fig. 42, capacitor has two terminals), the first gate capacitor terminal electrically coupled to the isolation gate (gate of 243, Fig. 42) and the second gate capacitor terminal electrically coupled to the ground voltage node (ground, see Fig. 42, paragraph [0158]). It would have been obvious to one of ordinary skill in the art before the effective filing date to use a gate capacitor coupled to the gate of the isolation transistor as disclosed by Saruwatari in the device of Denham in order to suppress power consumption by disconnecting the bias power source and having the capacitor maintain the voltage applied to the gate of the isolation transistor at a level that maintains operation in the saturation region. Regarding claim 4 , Denham in view of Saruwatari discloses the apparatus of claim 3, and Saruwatari further discloses an enable switch (344, Fig. 42) including a first enable terminal and a second enable terminal (see Fig. 42, switch 344 has two terminals), the first enable terminal electrically coupled to a bias voltage node (BIAS, Fig. 42) and the second enable terminal electrically coupled to the isolation gate (gate of 243, Fig. 42, paragraph [0157]). It would have been obvious to one of ordinary skill in the art before the effective filing date to include a switch between the bias voltage node and the gate of the isolation transistor as disclosed by Saruwatari in the device of Denham in order to disconnect the bias power source and suppress power consumption in the circuit. Regarding claim 5 , Denham in view of Saruwatari discloses the apparatus of claim 4, and Saruwatari further discloses the enable switch (344, Fig. 42) is an enable FET (paragraph [0161]), the enable FET including an enable gate (control terminal, paragraph [0161]). Denham in view of Saruwatari does not explicitly disclose that the transistor is a field effect transistor. However, it would have been obvious to one of ordinary skill in the art before the effective filing date to use a field effect transistor as they are well-known to be used for digital and power switching because they have no moving parts and can switch at very fast rates. Regarding claim 6 , Denham in view of Saruwatari discloses the apparatus of claim 5, and Saruwatari further discloses a controller (implicit, see paragraph [0161]) electrically coupled to the enable gate (paragraph [0161]: “It should be noted that for the switch elements 343, 344 in the direct current removing section 351, the transistor and the like which can be repeatedly opened and closed by an electrical control can be used.”), the controller configured to place the enable FET (344, Fig. 42) in a non-cutoff region (element 344 is closed, paragraph [0159]) prior to an acquisition period (see Fig. 43) such that current passes from the bias voltage node (BIAS, Fig. 2) to the gate capacitor (341, Fig. 2, paragraph [0159]). It would have been obvious to one of ordinary skill in the art before the effective filing date to couple a controller to the enable switch as disclosed by Saruwatari in order to repeatedly open and close it as required based on specific application. Regarding claim 7 , Denham in view of Saruwatari discloses the apparatus of claim 6, and Saruwatari further discloses the controller is configured to place the enable FET in a cutoff region (344 is opened, paragraph [0160]) during the acquisition period (detection period, Fig. 43) such that the isolation gate (gate of 243, Fig. 42) is electrically isolated from the bias voltage node (paragraph [0160], see timing chart in Fig. 43). Regarding claim 8 , Denham in view of Saruwatari discloses the apparatus of claim 7, and Saruwatari further discloses the bias voltage node (BIAS, Fig. 42) is electrically coupled to the detector voltage node (anode of 130, Fig. 42). Regarding claim 13 , Denham discloses a method comprising: providing a detector voltage (301, Fig. 2) at a detector voltage node (203, Fig. 2, paragraph [0029]); biasing an isolation gate of an isolation n-channel field effect transistor (gate of 201, Fig. 2) to a bias voltage (202, Fig. 2), the isolation nFET including an isolation source and an isolation drain (see Fig. 2, transistor 201 has a source, drain, like all transistors do), the isolation drain electrically coupled to the detector voltage (terminal connected to 301, Fig. 2); charging a supply capacitor (204, Fig. 2) to a charge voltage (paragraphs [0029]-[0030]) via the detector voltage node (203, Fig. 2) and the isolation nFET (201, Fig. 2) prior to an acquisition period (paragraph [0030]), the supply capacitor (204, Fig. 2) electrically coupled to a photodetector (302, Fig. 2) and the isolation source at a detector node (203, Fig. 2); and converting a light signal into an electrical signal by the photodetector (302, Fig. 2) during the acquisition period (paragraph [0031], acquisition period/event). Denham does not explicitly disclose that the bias voltage is such that the isolation nFET operates in a saturation region. However, Saruwatari discloses a bias voltage (BIAS, and 341, Fig. 42, see claim 17) is selected such that the isolation transistor (243, Fig. 42) operates in a saturation region (paragraphs [0159]-[0160]). It would have been obvious to one of ordinary skill in the art before the effective filing date to select a bias voltage such that the isolation transistor operates in a saturation region as disclosed by Saruwatari in the device of Denham in order to help filter out undesired signals in the circuit. Regarding claim 14 , Denham in view of Saruwatari discloses the method of claim 13, and Saruwatari further discloses: charging a gate capacitor (341, Fig. 42) to the bias voltage (BIAS, Fig. 42) prior to the acquisition period (Fig. 43, charging period is before detection period, see also paragraph [0159]); and electrically isolating the gate capacitor from the bias voltage supply node during the acquisition period (detection period, Fig. 43, paragraphs [0160]-[0161]). It would have been obvious to one of ordinary skill in the art before the effective filing date to use a gate capacitor coupled to the gate of the isolation transistor as disclosed by Saruwatari in the device of Denham in order to suppress power consumption by disconnecting the bias power source and having the capacitor maintain the voltage applied to the gate of the isolation transistor at a level that maintains operation in the saturation region. Regarding claim 15 , Denham in view of Saruwatari discloses the method of claim 14, and Saruwatari further discloses: wherein charging the gate capacitor (341, Fig. 2) includes closing a bias switch (344, Fig. 42, paragraph [0159]) electrically coupled between the bias voltage supply node (BIAS, Fig. 42) and the gate capacitor (gate of 243, Fig. 42); and wherein electrically isolating the gate capacitor (341, Fig. 2) includes opening the bias switch (344, Fig. 42, paragraph [0160]). It would have been obvious to one of ordinary skill in the art before the effective filing date to include a switch between the bias voltage node and the gate of the isolation transistor as disclosed by Saruwatari in the device of Denham in order to disconnect the bias power source and suppress power consumption in the circuit. Regarding claim 18 , Denham in view of Saruwatari discloses the method of claim 13, and Denham further discloses a computer programmed (105, Fig. 1, paragraphs [0016], [0029], under the broadest reasonable interpretation a microprocessor is a type of computer) to carry out the method of claim 13. Allowable Subject Matter Claim s 9-12, and 16-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claims 9-10 and 16-17 , t he invention as claimed, specifically in combination with: a boost switch electrically coupled between the detector voltage node and the first detector terminal; and a comparator including a first comparator input, a second comparator input, and a comparator output, the first comparator input electrically coupled to the first detector terminal, the second comparator input electrically coupled to a threshold voltage reference, the comparator output configured to open the boost switch when a detector voltage at the first detector terminal is above the threshold voltage reference and to close the boost switch when the detector voltage is below the threshold voltage reference , is not taught or made obvious by the prior art of record . Regarding claims 11-12 , the invention as claimed, specifically in combination with: a bias load coupled to the first detector terminal and ground, is not taught or made obvious by the prior art of record. Claim s 19-20 are allowed. The following is an examiner’s statement of reasons for allowance: The invention as claimed, specifically in combination with: a boost switch electrically coupled between the detector voltage node and the first detector terminal; and a comparator including a first comparator input, a second comparator input, and a comparator output, the first comparator input electrically coupled to the first detector terminal, the second comparator input electrically coupled to a threshold voltage reference, the comparator output configured to open the boost switch when a detector voltage at the first detector terminal is above the threshold voltage reference and to close the boost switch when the detector voltage is below the threshold voltage reference , is not taught or made obvious by the prior art of record . Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT MONICA T. TABA whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-1583 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday - Friday 9 am - 6 pm . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Georgia Epps can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT 571-272-2328 . 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