DETAILED ACTION
This action is responsive to the communication filed on 1/15/2026. Claims 1-20 are pending and have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-13 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 9484098 B1) in view of Ioannou et al. (US 20200066361 A1).
As per claim 1,
A method, comprising: predicting a shift in a voltage threshold associated with a set of memory cells responsive to a determined quantity of bits that are decoded from the set of memory cells from performance of a first memory operation using a first voltage, [Hsu teaches determining that a large number of errors occurred in a read operation in memory cells of a given data unit in a memory array due to threshold voltage distribution shift and subsequently performing rereads using different parameters such as different read voltages (col. 1, line 66 – col. 2, line 25; col. 11, line 39-61; col. 12, lines 4-15, 46-55; col. 13, lines 24-33; also see col. 12, line 65 – col. 14, line 8 and figs. 14-15 and associated paragraphs showing read voltage selection as part of reread parameter determination), where the direction/adjustment of the reread voltages (higher or lower) may be determined based on whether the number of a bit (i.e. 0 or 1) obtained during an initial read using a default threshold voltage (first memory operation using a first voltage) is greater than an expected number of the bit by more than an error correctable amount or less than the expected number of the bit by more than the error correctable amount (col. 2, lines 16 – col. 3, line 22, col. 12, lines 33-35, col. 13, line 49 – col. 14, line 8; see col. 13, line 56 – col. 14, line 8 on read data being decoded to determine whether it can be corrected; see col. 11, lines 49-56 on threshold voltage shift causing bad bits by being read as inverse of the programmed logic state, and too many bad bits causing data to be uncorrectable; see col. 16, lines 30-35 providing shape of read data being determined, where data read is decoded)] performing a second memory operation involving the first portion of the set of memory cells using a second voltage that is greater than the first voltage in response to determining that the decoded quantity of bits exceeds a first threshold quantity of bits based on the predicted shift in the voltage associated with the set of memory cells, wherein the first threshold quantity of bits is a designated quantity of bits that is greater than a predicted quantity of bits for a read level of a read operation of the set of memory cells, and wherein the second voltage includes a set of positive offsets; or performing the second memory operation involving the second portion of the set of memory cells using a third voltage that is less than the first voltage in response to determining that the decoded quantity of bits is below a second threshold quantity of bits for the set of memory cells based on the predicted shift in the voltage associated with the set of memory cells, wherein the second threshold quantity of bits is a designated quantity of bits that is less than the predicted quantity of bits for the read level of the read operation of the set of memory cells. [Hsu as shown above teaches adjusting reread voltages (to be higher or lower) based on whether the number of a bit obtained, using the default threshold voltage (first voltage) of the first memory operation, is greater than or less than the expected number of the bit by more than the error correctable amount (col. 2, lines 16 – col. 3, line 22, col. 12, lines 33-35, col. 13, line 49 – col. 14, line 8; see col. 13, line 56 – col. 14, line 8, col. 11, lines 49-56, col. 16, lines 30-35 as cited above on decoding being performed on data read from the cells), where the first threshold quantity of bits may correspond the expected number of the bit plus the error correctable amount (threshold for the number of the bit being greater than the expected number of the bit by the error correctable amount), and the second threshold quantity of bits may correspond to the expected number of the bit minus the error correctable amount (threshold for the number of the bit being less than the expected number of the bit by the error correctable amount); Hsu teaches the reread may focus on using voltages that are either lower or higher than the original voltage based on the increase or decrease in the logic values (col. 12 line 65 – col. 13, line 23), where a reread performed on the cells using a higher voltage may correspond to a set of positive offsets, as a higher voltage is applied to each of the cells; Hsu teaches an example of decrease in threshold voltage signified by a decrease in 0’s, and that the reread would focus on lower voltages (using second voltage when the quantity is below the second threshold) (col. 13, lines 8-23), and where Hsu also gives an example of an increase in threshold voltage causing increasing in logic 0’s (col. 12, lines 3-35; fig. 11C), it would have been obvious for one of ordinary skill in the arts that reread would focus on higher voltages (first voltage) in response to the increase in threshold voltage as signified by increase in logic 0’s to provide for improved read calibration accounting for both increase and decrease in threshold voltages; where Hsu teaches focusing on the lower or higher voltages as shown above (col. 13, lines 8-23; fig 14), for the reread operation, Hsu also teaches applying, of possible voltages, a subset that corresponds to the determined threshold voltage shift direction (e.g. if the threshold voltages are shifted upwards, using increased voltage) to cut down in the search time (col. 14, line 65 – col. 15, line 18; col. 2, lines 35-40)]
Hsu does not explicitly disclose, but Ioannou discloses:
wherein the set of memory cells include a first portion with a target voltage greater than the voltage threshold and a second portion with a target voltage less than the voltage threshold;; involving the first portion of the set of memory cells; involving the second portion of the set of memory cells [Hsu as shown above discloses determining a threshold voltage shift direction and reread voltage associated with a data unit for performing a reread operation on the data unit (please see the rejection above; col. 1, line 66 – col. 2, line 25; col. 46-50), where the data unit may be any suitable unit such as a page or a block (col. 13, lines 24-34); however, Hsu’s disclosure is not explicit with respect to the reads involving first/second portions with target voltage greater than or less than the voltage threshold; Ioannou discloses, for a block comprising a plurality of page groups each comprising at least one memory page, iterating through the respective page groups to determine the direction of threshold voltage shift for each page group, where the threshold voltage may shift upwards or downwards for a page group (having target voltage greater than or less than voltage threshold) (abstract, para. 71, 58-63, 41; figs. 1, 4 and associated paragraphs), where page groups of a block may correspond to portions (page group) of a set of memory cells (block), and where a block, having page groups that may respective be determined to have shifted upwards or downwards, may necessarily comprise page groups with threshold voltage that has shifted upwards (first portion(s)) or downwards (second portion(s))]
Hsu and Ioannou are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Hsu and Ioannou, to modify the disclosures by Hsu to include disclosures by Ioannou since they both teach data storage, wherein Ioannou is directed towards improvement in endurance of memory cells (para. 31). Therefore, it would be applying a known technique (iterating through a plurality of page groups in a block for determining threshold voltage shift direction of the respective page groups) to a known device (system performing a read operation on a data unit for obtaining a change in the number of bits stored in the data unit, to determine the direction of threshold voltage shift and rereading the data unit using an adjusted voltage) ready for improvement to yield predictable results (system iterating through a plurality of page groups in a block, involving performing a read operation for obtaining a change in the number of bits stored in a page group to determine the direction of threshold voltage shift of the page group and rereading the data of the page group using adjusted voltage; doing so would provide for minimizing the maximum raw bit error rate for each block (Ioannou: para. 31)). MPEP 2143
As per claim 2, Hsu in view of Ioannou teaches all the limitations of claim 1 as shown above and further teaches:
further comprising performing the second memory operation on only the first portion of the set of memory cells using the second voltage that is greater than the first voltage in response to determining that the quantity of bits exceeds the first threshold quantity of bits. [Hsu in view of Ioannou as shown above teaches determining the shift direction of a page group’s threshold voltage based on the number of bits from a read operation with a default threshold voltage exceeding a first threshold or being below a second threshold (expected number of bits plus/minus error correctable amount), and performing a reread (second memory operation) using an increased or decreased voltage (see claim 1 above; Hsu: col. 1, line 66 – col. 3, line 22; col. 11, line 39-61; col. 12, lines 3-35; col. 13, lines 8-23; col. 13, line 49 – col. 14, line 8), wherein the process can be performed on respective page groups of a block (see claim 1 above; Ioannou: para. 71, 58-63, 41), where the reread (second memory operation) with increased (second) voltage will necessarily be performed only on the page groups with increased threshold voltage (first portion(s)), as determined by the obtained number of a bit from a page group exceeding the first threshold.]
Hsu and Ioannou are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Hsu and Ioannou, to modify the disclosures by Hsu to include disclosures by Ioannou since they both teach data storage, wherein Ioannou is directed towards improvement in endurance of memory cells (para. 31). Therefore, it would be applying a known technique (iterating through a plurality of page groups in a block for determining threshold voltage shift direction of the respective page groups) to a known device (system performing a read operation on a data unit for obtaining a change in the number of bits stored in the data unit, to determine the direction of threshold voltage shift and rereading the data unit using an adjusted voltage) ready for improvement to yield predictable results (system iterating through a plurality of page groups in a block, involving performing a read operation for obtaining a change in the number of bits stored in a page group to determine the direction of threshold voltage shift of the page group and rereading the data of the page group using adjusted voltage; doing so would provide for minimizing the maximum raw bit error rate for each block (Ioannou: para. 31)). MPEP 2143
As per claim 3, Hsu in view of Ioannou teaches all the limitations of claim 1 as shown above and further teaches:
further comprising performing the second memory operation on only the second portion of the set of memory cells using the third voltage that is less than the first voltage in response to determining that the quantity of bits is below the second threshold quantity of bits. [Hsu in view of Ioannou as shown above teaches determining the shift direction of a page group’s threshold voltage based on the number of bits from a read with a default threshold voltage exceeding a first threshold or being below a second threshold (expected number of bits plus/minus error correctable amount), and performing a reread (second memory operation) using an increased or decreased voltage (see claim 1 above; Hsu: col. 1, line 66 – col. 3, line 22; col. 11, line 39-61; col. 12, lines 3-35; col. 13, lines 8-23; col. 13, line 49 – col. 14, line 8), wherein the process can be performed on respective page groups of a block (see claim 1 above; Ioannou: para. 71, 58-63, 41), where the reread (second memory operation) with decreased (third) voltage will necessarily be performed only on the page groups (portion(s)) with decreased threshold voltage, as determined by the obtained number of a bit from a page group being below the second threshold.]
Hsu and Ioannou are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Hsu and Ioannou, to modify the disclosures by Hsu to include disclosures by Ioannou since they both teach data storage, wherein Ioannou is directed towards improvement in endurance of memory cells (para. 31). Therefore, it would be applying a known technique (iterating through a plurality of page groups in a block for determining threshold voltage shift direction of the respective page groups) to a known device (system performing a read operation on a data unit for obtaining a change in the number of bits stored in the data unit, to determine the direction of threshold voltage shift and rereading the data unit using an adjusted voltage) ready for improvement to yield predictable results (system iterating through a plurality of page groups in a block, involving performing a read operation for obtaining a change in the number of bits stored in a page group to determine the direction of threshold voltage shift of the page group and rereading the data of the page group using adjusted voltage; doing so would provide for minimizing the maximum raw bit error rate for each block (Ioannou: para. 31)). MPEP 2143
As per claim 4, Hsu in view of Ioannou teaches all the limitations of claim 1 as shown above and further teaches:
further comprising refraining from using the third voltage in response to determining that the quantity of bits is above the second threshold quantity of bits for the set of memory cells. [Hsu as shown above teaches respectively using voltages that are higher (second voltage) or lower (third voltage) in response to shift in voltage being determined to have increased or decreased pursuant to the number of relevant logical bits increasing or decreasing (see claim 1 above; col. 13, lines 8-23; col. 12, lines 3-35; fig. 14 and associated paragraphs); where Hsu teaches focusing on the lower or higher voltages as shown above (col. 13, lines 8-23; fig 14), for the reread operation, Hsu also teaches applying, of possible voltages, a subset that correspond to the determined threshold voltage shift direction (e.g. if the threshold voltages are shifted upwards, using increased voltage) to cut down in the search time (col. 14, line 65 – col. 15, line 18) and also teaches subsequent sets of read voltages (e.g. second and third set) each following the same trend of being higher or lower than the default voltage (col. 2, lines 26-40), where it would have been obvious for one of ordinary skill in the arts provided with Hsu’s disclosures as shown above to limit the voltages used in the reread operations to either the voltages that are higher than the original voltage or the voltages that are lower than the original voltage, among the possible voltages, pursuant to the determined direction of the voltage shift in order to provide for faster determination of possible usable adjusted read voltage]
As per claim 5, Hsu in view of Ioannou teaches all the limitations of claim 1 as shown above and further teaches:
wherein the set of memory cells comprise a word line of a NAND memory device. [Hsu in view of Ioannou as shown above teaches reading page groups (portions) of a block (set of cells) as shown above (see claim 1 above; Hsu: col. 1, line 66 – col. 2, line 25; Ioannou: para. 71, 58-63, 41, 5); Hsu teaches memory cells organized into NAND strings comprising a word line (col. 8, lines 2-28) and a page comprising to a word line, where a block may comprise a plurality of pages (col. 8, line 53 – col. 9, line 3; col. 9, lines 26-27; col. 13, lines 24-34), where a block (set of cells) would necessarily comprise a word line]
Hsu and Ioannou are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Hsu and Ioannou, to modify the disclosures by Hsu to include disclosures by Ioannou since they both teach data storage, wherein Ioannou is directed towards improvement in endurance of memory cells (para. 31). Therefore, it would be applying a known technique (iterating through a plurality of page groups in a block for determining threshold voltage shift direction of the respective page groups) to a known device (system performing a read operation on a data unit for obtaining a change in the number of bits stored in the data unit, to determine the direction of threshold voltage shift and rereading the data unit using an adjusted voltage) ready for improvement to yield predictable results (system iterating through a plurality of page groups in a block, involving performing a read operation for obtaining a change in the number of bits stored in a page group to determine the direction of threshold voltage shift of the page group and rereading the data of the page group using adjusted voltage; doing so would provide for minimizing the maximum raw bit error rate for each block (Ioannou: para. 31)). MPEP 2143
As per claim 6, Hsu in view of Ioannou teaches all the limitations of claim 1 as shown above and further teaches:
comprising determining the first threshold quantity of bits and the second threshold quantity of bits for the set of memory cells based on a particular memory cell or sub-set of memory cells that is in a particular physical location within the set of memory cells. [Hsu in view of Ioannou as shown above teaches determining the shift direction of a page group’s threshold voltage based on the number of bits, from a read operation with a default threshold voltage, exceeding a first threshold or being below a second threshold (expected number of bits plus/minus error correctable amount), and performing a reread (second memory operation) using an increased or decreased voltage (see claim 1 above; Hsu: col. 1, line 66 – col. 3, line 22; col. 11, line 39-61; col. 12, lines 3-35; col. 13, lines 8-23; col. 13, line 49 – col. 14, line 8), wherein the process can be performed on respective page groups of a block (see claim 1 above; Ioannou: para. 71, 58-63, 41); where the expected number of a bit of a particular page group comprises the initially programmed number of bits for the page group (unit of data) (Hsu: col. 2, lines 9-25), and where a page group (particular sub-set of memory cells) selected read may necessarily influence the first and second thresholds, as the thresholds are determined in part based on the page group’s expected number of bits as shown above.]
Hsu and Ioannou are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Hsu and Ioannou, to modify the disclosures by Hsu to include disclosures by Ioannou since they both teach data storage, wherein Ioannou is directed towards improvement in endurance of memory cells (para. 31). Therefore, it would be applying a known technique (iterating through a plurality of page groups in a block for determining threshold voltage shift direction of the respective page groups) to a known device (system performing a read operation on a data unit for obtaining a change in the number of bits stored in the data unit, to determine the direction of threshold voltage shift and rereading the data unit using an adjusted voltage) ready for improvement to yield predictable results (system iterating through a plurality of page groups in a block, involving performing a read operation for obtaining a change in the number of bits stored in a page group to determine the direction of threshold voltage shift of the page group and rereading the data of the page group using adjusted voltage; doing so would provide for minimizing the maximum raw bit error rate for each block (Ioannou: para. 31)). MPEP 2143
As per claim 7,
An apparatus, comprising: a processing device configured to: [Hsu teaches a memory system comprising a controller for controlling memory operations, where the controller comprises a processor (col. 6, line 40 – col. 7, line 10; fig. 1, 18 and associated paragraphs; see col. 16, lines 44-47 indicating firmware in the controller)] perform, using a first threshold voltage, a first read operation that targets at least one memory cell within a set of memory cells to: determine a first threshold quantity of bits for the set of memory cells, and determine a second threshold quantity of bits for the set of memory cells; [Hsu teaches reading memory cells of a data unit using a default set of read parameters (first read operation using first threshold voltage), comparing the number of memory cells determined to be in a first state that may represent, for example, logic 1 or 0, (i.e. number of bits) with the number of memory cells expected to be in the first state, and based on the resulting difference being positive or negative, selecting a respective modified set of read parameters and rereading the memory cells (second read operation) using the modified set of read parameters (col. 1, line 66 – col. 2, line 25; col. 2, line 55 – col. 3, line 3; col. 11, line 57 – col. 12, line 35; figs. 11A-E and associated paragraphs; see col. 13, lines 24-33 providing that the number of cells of a unit in a particular memory state such as logic 0 is recorded when the cells are programmed and used for the comparison when the cells are read; also see col. 12, line 65 – col. 14, line 8 and figs. 14-15 and associated paragraphs showing read voltage selection as part of reread parameter determination; see col. 13, line 56 – col. 14, line 8 on read data being decoded to determine whether it can be corrected; see col. 11, lines 49-56 on threshold voltage shift causing bad bits by being read as inverse of the programmed logic state, and too many bad bits causing data to be uncorrectable; see col. 16, lines 30-35 providing shape of read data being determined, where data read is decoded)); Hsu further teaches the difference in the bits must greater than a limit for the reread operation to occur, where the read data is normally sent to the memory controller otherwise (col. 2, line 55 – col. 3, line 3; col. 3, lines 20-22; col. 13, lines 56-59), where the first threshold quantity of bits may therefore correspond to the expected number of cells in the first state plus the limit (i.e. upper bound of bits read for not triggering a reread), and the second threshold quantity of bits may correspond to the expected number of cells in the first state minus the limit (i.e. lower bound number of bits read for not triggering a reread)] predict a shift in a voltage threshold associated with the set of memory cells based on performance of the first read operation using the first threshold voltage that targets at least the one memory cell within the set of memory cells, … wherein the performance includes a quantity of binary information from decoded bits compared to a predicted quantity of binary information from the decoded bits; and determine a second threshold voltage to be utilized for a second read operation based on a comparison between the determined first threshold quantity of bits and the second threshold quantity of bits and the predicted shift in the voltage associated with the set of memory cells,; wherein the second threshold voltage is greater than the first threshold voltage when the determined quantity of bits is greater than the first threshold quantity of bits and less than the first threshold voltage when the determined quantity of bits is less than the second threshold quantity of bits. [Hsu teaches, based on read performed using default/original read voltage, predicting reread conditions by identifying whether threshold voltages have shifted up or down, where the shifting direction of the threshold voltage may be determined based on whether the number of a certain logic value has decreased or increased (e.g. logic 0 or logic 1), and the reread may focus on using voltages (second threshold voltage) that are either lower or higher than the original voltage (first threshold voltage used by first read operation) based on the increase or decrease in the logic values (col. 12 line 65 – col. 13, line 23; also see col. 12, line 65 – col. 14, line 8 and figs. 14-15 and associated paragraphs showing read voltage selection as part of reread parameter determination; see col. 13, line 56 – col. 14, line 8, col. 11, lines 49-56, col. 16, lines 30-35 as cited above on decoding being performed on data read from the cells); for example, Hsu teaches that a decrease in threshold voltage can be signified by a decrease in logic 0’s, and that the reread would focus on lower voltages (col. 13, lines 8-23), and where Hsu further provides an example of an increase in threshold voltage increasing in logic 0’s (col. 12, lines 3-35), it would have been obvious for one of ordinary skill in the that reread would focus on higher voltages in response to the increase in threshold voltage as signified by increase in logic 0’s to provide for improved read calibration accounting for both increase and decrease in threshold voltages; where Hsu teaches focusing on the lower or higher voltages as shown above (col. 13, lines 8-23; fig 14), Hsu also teaches applying a subset of possible voltages based on the determined threshold voltage shift direction to cut down in the search time (col. 14, line 65 – col. 15, line 18), where it would have been obvious for one of ordinary skill in the arts provided with Hsu’s disclosure to limit the voltages used in the reread operations to either the voltages that are higher than the original voltage or the voltages that are lower than the original voltage, among the possible voltages, pursuant to the determined direction of the voltage shift in order to provide for faster determination of possible usable adjusted read voltage; where Hsu’s disclosure of comparing the expected number of a bit as written with the number of bits subsequently read for predicting the threshold voltage shift direction (col. 13, lines 8-33) while utilizing limits acting as the upper/lower bounds around the expected number of bits for triggering the reread operation (first/second threshold quantity of bits) (col. 2, line 55 – col. 3, line 3; col. 3, lines 20-22; col. 13, lines 56-59), may correspond to a comparison between the first threshold quantity of bits, second threshold quantity of bits, and the predicted shift in voltage.] wherein the first threshold quantity of bits is a designated quantity of bits that is greater than a predicted quantity of bits for a read level of a read operation of the set of memory cells and the second threshold quantity of bits is a designated quantity of bits that is less than the predicted quantity of bits for the read level of the read operation of the set of memory cells, [Hsu teaches the difference in the bits between the expected number of bits and the number of bits read by the default threshold voltage (read level) of the first memory operation must greater than a limit for the reread operation to occur, where the limit may be the correctable number of bits, where the read data is normally sent to the memory controller otherwise (col. 2, line 55 – col. 3, line 3; col. 3, lines 20-22; col. 13, lines 56-59), where the first threshold quantity of bits may therefore correspond to the expected number of cells in the first state plus the limit (i.e. upper bound of bits read for not triggering a reread), and the second threshold quantity of bits may correspond to the expected number of cells in the first state minus the limit (i.e. lower bound number of bits read for not triggering a reread)]
Hsu does not explicitly disclose, but Ioannou discloses:
wherein the set of memory cells include a first portion with a target voltage greater than the voltage threshold and a second portion with a target voltage less than the voltage threshold; [Hsu as shown above discloses determining a threshold voltage shift direction and reread voltage associated with a data unit for performing a reread operation on the data unit (please see the rejection above; col. 1, line 66 – col. 2, line 25; col. 46-50), where the data unit may be any suitable unit such as a page or a block (col. 13, lines 24-34); however, Hsu’s disclosure is not explicit with respect to the reads involving first/second portions with target voltage greater than or less than the voltage threshold; Ioannou discloses, for a block comprising a plurality of page groups each comprising at least one memory page, iterating through the respective page groups to determine the direction of threshold voltage shift for each page group, where the threshold voltage may shift upwards or downwards for a page group (having target voltage greater than or less than voltage threshold) (abstract, para. 71, 58-63, 41; figs. 1, 4 and associated paragraphs), where page groups of a block may correspond to portions (page group) of a set of memory cells (block), and where a block, having page groups that may respective be determined to have shifted upwards or downwards, may necessarily comprise page groups with threshold voltage that has shifted upwards (first portion(s)) or downwards (second portion(s))]
Hsu and Ioannou are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Hsu and Ioannou, to modify the disclosures by Hsu to include disclosures by Ioannou since they both teach data storage, wherein Ioannou is directed towards improvement in endurance of memory cells (para. 31). Therefore, it would be applying a known technique (iterating through a plurality of page groups in a block for determining threshold voltage shift direction of the respective page groups) to a known device (system performing a read operation on a data unit for obtaining a change in the number of bits stored in the data unit, to determine the direction of threshold voltage shift and rereading the data unit using an adjusted voltage) ready for improvement to yield predictable results (system iterating through a plurality of page groups in a block, involving performing a read operation for obtaining a change in the number of bits stored in a page group to determine the direction of threshold voltage shift of the page group and rereading the data of the page group using adjusted voltage; doing so would provide for minimizing the maximum raw bit error rate for each block (Ioannou: para. 31)). MPEP 2143
As per claim 8, Hsu in view of Ioannou teaches all the limitations of claim 7 as shown above and further teaches:
wherein the processing device is further configured to perform the second read operation using the second threshold voltage. [Hsu as shown above teaches, for a reread operation (second read operation), respectively using voltages that are higher or lower than the original voltage (second threshold voltage being higher or lower than the first threshold voltage) in response to shift in voltage being determined to have, respectively, increased or decreased pursuant to the number of relevant logical bits increasing or decreasing (see claim 7 above; col. 13, lines 8-23; col. 12, lines 3-35; fig. 14 and associated paragraphs)]
As per claim 9, Hsu in view of Ioannou teaches all the limitations of claim 8 as shown above and further teaches:
wherein the second read operation is performed on the first portion of memory cells when the determined quantity of bits is greater than the first threshold quantity of bits. [Hsu in view of Ioannou as shown above teaches determining the shift direction of a page group’s threshold voltage based on the number of bits from a read with a default/original threshold voltage exceeding a first threshold or being below a second threshold (expected number of bits plus/minus error correctable amount (or limit)), and performing a reread (second memory operation) using an increased or decreased voltage (see claim 7 above; Hsu: col. 1, line 66 – col. 3, line 22; col. 11, line 39-61; col. 12, lines 3-35; col. 13, lines 8-23; col. 13, line 49 – col. 14, line 8), wherein the process can be performed on respective page groups of a block (see claim 7 above; Ioannou: para. 71, 58-63, 41), where the reread (second memory operation) with increased voltage will necessarily be performed on the page groups with increased threshold voltage (first portion), as determined by the obtained number of a bit from a page group being above the first threshold.]
Hsu and Ioannou are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Hsu and Ioannou, to modify the disclosures by Hsu to include disclosures by Ioannou since they both teach data storage, wherein Ioannou is directed towards improvement in endurance of memory cells (para. 31). Therefore, it would be applying a known technique (iterating through a plurality of page groups in a block for determining threshold voltage shift direction of the respective page groups) to a known device (system performing a read operation on a data unit for obtaining a change in the number of bits stored in the data unit, to determine the direction of threshold voltage shift and rereading the data unit using an adjusted voltage) ready for improvement to yield predictable results (system iterating through a plurality of page groups in a block, involving performing a read operation for obtaining a change in the number of bits stored in a page group to determine the direction of threshold voltage shift of the page group and rereading the data of the page group using adjusted voltage; doing so would provide for minimizing the maximum raw bit error rate for each block (Ioannou: para. 31)). MPEP 2143
As per claim 10, Hsu in view of Ioannou teaches all the limitations of claim 8 as shown above and further teaches:
wherein the second read operation is performed on the second portion of memory cells when the determined quantity of bits is less than the second threshold quantity of bits. [Hsu in view of Ioannou as shown above teaches determining the shift direction of a page group’s threshold voltage based on the number of bits from a read with a default/original threshold voltage exceeding a first threshold or being below a second threshold (expected number of bits plus/minus error correctable amount (or limit)), and performing a reread (second memory operation) using an increased or decreased voltage (see claim 7 above; Hsu: col. 1, line 66 – col. 3, line 22; col. 11, line 39-61; col. 12, lines 3-35; col. 13, lines 8-23; col. 13, line 49 – col. 14, line 8), wherein the process can be performed on respective page groups of a block (see claim 7 above; Ioannou: para. 71, 58-63, 41), where the reread (second memory operation) with decreased voltage will necessarily be performed on the page groups with decreased threshold voltage (second portion), as determined by the obtained number of a bit from a page group being below the second threshold.]
Hsu and Ioannou are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Hsu and Ioannou, to modify the disclosures by Hsu to include disclosures by Ioannou since they both teach data storage, wherein Ioannou is directed towards improvement in endurance of memory cells (para. 31). Therefore, it would be applying a known technique (iterating through a plurality of page groups in a block for determining threshold voltage shift direction of the respective page groups) to a known device (system performing a read operation on a data unit for obtaining a change in the number of bits stored in the data unit, to determine the direction of threshold voltage shift and rereading the data unit using an adjusted voltage) ready for improvement to yield predictable results (system iterating through a plurality of page groups in a block, involving performing a read operation for obtaining a change in the number of bits stored in a page group to determine the direction of threshold voltage shift of the page group and rereading the data of the page group using adjusted voltage; doing so would provide for minimizing the maximum raw bit error rate for each block (Ioannou: para. 31)). MPEP 2143
As per claim 11, Hsu in view of Ioannou teaches all the limitations of claim 7 as shown above and further teaches:
wherein the processing device is configured to determine a plurality of subsequent threshold voltages to be greater than the first threshold voltage when the determined quantity of bits is greater than the first threshold quantity of bits. [Hsu as shown above teaches, for a reread operation (second memory operation), respectively using voltages that are higher or lower than the original voltage (second threshold voltage being higher or lower than the first threshold voltage) in response to shift in voltage being determined to have, respectively, increased or decreased pursuant to the number of relevant logical bits increasing or decreasing beyond a limit (see claim 7 above; col. 13, lines 8-23; col. 12, lines 3-35; fig. 14 and associated paragraphs), where the voltage of the reread operation (second threshold voltage) would be greater than the default voltage (first threshold voltage) if the read with the default voltage yielded a number of bits which is greater than the expected number of bits plus the limit (determined number of bits being greater than first threshold quantity of bits); Hsu also teaches applying a subset of possible voltages based on the threshold voltage shift direction to cut down in the search time (col. 14, line 65 – col. 15, line 18), where it would have been obvious for one of ordinary skill in the arts provided with Hsu’s disclosure to limit the reread operations to increased/decreased threshold voltages corresponding to the determined direction of the voltage shift in order to provide for faster determination of possible usable adjusted read voltage]
As per claim 12, Hsu in view of Ioannou teaches all the limitations of claim 7 as shown above and further teaches:
wherein the processing device is configured to determine a plurality of subsequent threshold voltages to be less than the first threshold voltage when the determined quantity of bits is less than the second threshold quantity of bits. [Hsu as shown above teaches, for a reread operation (second memory operation), respectively using voltages that are higher or lower than the original voltage (second threshold voltage being higher or lower than the first threshold voltage) in response to shift in voltage being determined to have, respectively, increased or decreased pursuant to the number of relevant logical bits increasing or decreasing beyond a limit (see claim 7 above; col. 13, lines 8-23; col. 12, lines 3-35; fig. 14 and associated paragraphs), where the voltage of the reread operation (second threshold voltage) would be lower than the default voltage (first threshold voltage) if the read with the default voltage yielded a number of bits which is lower than the expected number of bits minus the limit (determined number of bits being lower than the second threshold quantity of bits); Hsu also teaches applying a subset of possible voltages based on the threshold voltage shift direction to cut down in the search time (col. 14, line 65 – col. 15, line 18), where it would have been obvious for one of ordinary skill in the arts provided with Hsu’s disclosure to limit the reread operations to increased/decreased threshold voltages corresponding to the determined direction of the voltage shift in order to provide for faster determination of possible usable adjusted read voltage]
As per claim 13, Hsu in view of Ioannou teaches all the limitations of claim 7 as shown above and further teaches:
wherein the processing device is configured to: perform only positive read offsets when the determined quantity of bits is greater than the first threshold quantity of bits, and perform only negative read offsets when the determined quantity of bits is less than the second threshold quantity of bits. [Hsu as shown above teaches, for a reread operation (second memory operation), respectively using voltages that are higher or lower than the original voltage (second threshold voltage being higher or lower than the first threshold voltage) in response to shift in voltage being determined to have, respectively, increased or decreased pursuant to the number of relevant logical bits increasing or decreasing beyond a limit (see claim 7 above; col. 13, lines 8-23; col. 12, lines 3-35; fig. 14 and associated paragraphs), where the voltage of the reread operation (second threshold voltage) would be respectively lower or greater than the default voltage (first threshold voltage) if the read with the default voltage yielded a number of bits which is lower than the expected number of bits minus the limit (determined number of bits being lower than the second threshold quantity of bits) or greater than the expected number of bits plus the limit (determined number of bits being greater than the first threshold quantity of bits); Hsu also teaches applying a subset of possible voltages based on the threshold voltage shift direction to cut down in the search time (col. 14, line 65 – col. 15, line 18), where it would have been obvious for one of ordinary skill in the arts provided with Hsu’s disclosure to limit the reread operations to increased/decreased threshold voltages corresponding to the determined direction of the voltage shift in order to provide for faster determination of possible usable adjusted read voltage]
Allowable Subject Matter
Claims 14-20 are allowed.
With respect to claim 14, “… determine a quantity of bits of the set of memory cells based on the first read operation using the first threshold voltage, wherein the set of memory cells include a first portion with a target voltage greater than a first voltage threshold and a second portion with a target voltage less than the first voltage threshold; predict a shift in a voltage threshold associated with the set of memory cells based on performance of the first read operation involving the set of memory cells using the first threshold voltage, wherein the performance includes a quantity of decoded bits compared to a predicted quantity of bits for a read level of a read operation of the set of memory cells, and wherein the quantity of decoded bits is a quantity of binary information stored by the set of memory cells; and perform read operations involving the set of memory cells using a set of threshold voltages based on the predicted shift in the voltage threshold associated with the set of memory cells based on performance of the first read operation involving the set of memory cells using the first threshold voltage, wherein the set of threshold voltages includes a second threshold voltage that is greater than the first threshold voltage when the determined quantity of decoded bits is greater than an upper bit count threshold and a third threshold voltage that is less than the first threshold voltage when the determined quantity of decoded bits is less than a lower bit count threshold, wherein the set of threshold voltages includes a combination of positive and negative offsets when the determined quantity of decoded bits is between the upper bit count threshold and the lower bit count threshold.” in conjunction with the other limitations of the claim, are not disclosed by the prior art of record.
The closest prior arts of record are Hsu et al. (US 9484098 B1), Ioannou et al. (US 20200066361 A1), Sharon et al. (US 20220199156 A1), Kuribara et al. (US 20220093182 A1), and Sun et al. (US 9424944 B2).
Hsu teaches comparing bits read from memory cells and adjusting subsequent read voltages based on a comparison of the bits read against expected number of bits. Ioannou teaches iteratively adjusting read voltages for page groups in a block. Sharon teaches performing read threshold calibration based on expected number of bits in lower, middle, and upper pages read. Kuribara teaches repeating re-reads and error correction based on the number of bits read in a read operation differing from expected number of bits. Sun teaches adjusting re-read voltage in a direction respectively corresponding to an increase or decrease in the number of binary 1’s read in comparison to the number of binary 1’s expected.
However, the prior arts of record, neither individually nor in combination, teaches performing first read operation on a set of memory cells using a first threshold voltage to determine a quantity of decoded bits, the memory cells comprising a first portion with a target voltage greater than a first voltage threshold and a second portion with a target voltage less than the first voltage threshold, where further read operations are performed on the set of memory cells using a set of threshold voltages based on a predicted shift in the voltage threshold of the set of memory cells, the set of threshold voltages including a second threshold voltage that is greater than the first threshold voltage when the quantity of decoded bits is greater than an upper bit count threshold and a third threshold voltage that is less than the first threshold voltage when the determined quantity of decoded bits is less than a lower bit count threshold, and where the set of threshold voltages includes a combination of positive and negative offsets when the determined quantity of decoded bits is between the upper bit count threshold and the lower bit count threshold.
Therefore, the prior arts of record, neither individually nor in combination disclose, in conjunction with the other limitations of the claim, the claim as a whole.
Claims 15-20 are allowed based at least on the virtues of their dependency from claim 14.
Response to Arguments
The rejection pursuant to 35 U.S.C. 112(b) previously included in the most recent previous office action has been withdrawn in view of the amendments by the applicant.
With respect to arguments as recited in pages 9-11 of the remarks, stating that the combination of references fail to teach or suggest a claimed subject matter relating to performing a read operation with an increased voltage in response to predicting a shift in a voltage threshold associated with a set of memory cells responsive to a determined quantity of bits that are decoded from the set of memory cells from performance of a first memory operation using a first voltage… wherein the determined quantity of bits is a quantity of binary information stored by the set of memory cells, the examiner respectfully disagrees.
The examiner respectfully submits that Hsu in view of Ioannou as relied upon for the rejections of claims 1 and 7 provide for performing a read operation (first memory operation) in a given unit of data (set of memory cells) using a default voltage (first voltage), using information regarding change in the total number of memory cells read having a given bit, where the information may indicate a direction of threshold voltage shift, and a read parameter may be adjusted in the appropriate direction, such as by increasing read voltage, for a second read operation (‘a read operation’) (please see rejections 1, 7 above; Hsu: col. 1, line 66 – col. 3, line 22; col. 11, line 39-61; col. 12, lines 4-55; col. 13, lines 24-33), where Hsu further teaches performing a decoding, or ECC, process on the data as read in determining (Hsu: col. 13, line 56 – col. 14, line 8, col. 11, lines 49-56, col. 16, lines 30-35).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/E.Y.K./Examiner, Art Unit 2135
/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135
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