Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Remarks
Applicant’s arguments, see §112(a) - Claim 13 and Objection to the drawings, filed April 1, 2026, have been fully considered and are persuasive. The §112(a) rejection and drawing objection of December 1, 2025 has been withdrawn.
Applicant’s arguments, see §112(b) - Claims 2-3, 5-6, and 11, filed April 1, 2026, with respect to Section II.A./C./D./E. have been fully considered and are persuasive. The §112(b) rejections of December 1, 2025 have been withdrawn.
Applicant’s arguments, see §112(b) - Claims 2-3, 5-6, and 11, filed April 1, 2026, with respect to Section II.B., the rejection of claim 2 (line 6) under §112(b), has been fully considered and is not persuasive. Therefore, the rejection stands. See Claim Rejections - 35 USC § 112 section below.
Applicant’s arguments, see §112(b) - Claims 2-3, 5-6, and 11, filed April 1, 2026, with respect to Section II.F. has been fully considered and is partially persuasive. The §112(b) rejection, of inheriting the defects of claim 3, of December 1, 2025 for claim 4 has been withdrawn. The §112(b) rejections, of inheriting the defects of claim 2, of December 1, 2025 for claims 7-10 and 12 stands.
Response to Arguments
Applicant's arguments filed April 1, 2026 have been fully considered but they are not persuasive. Applicant argues that the prior art does not teach each and.
Applicant’s arguments with respect to claim 1 has been considered but are moot because the new ground of rejection.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 1 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The maintenance of a non-zero phase difference between an output of the phase locked loop circuit and a reference clock in a steady state has not been sufficiently described.
Claims 2-12 inherit the defects of independent claim 1.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2 and 5-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 (lines 3-4) recites "a reference clock". It is unclear if this "reference clock" is the same "reference clock" introduced in claim 1, or is this a new "reference clock".
Claim 2 (line 6) recites "a loop current". Applicant's remarks, filed April 1, 2026, state that this "loop current" of line 6 is "the same loop current referenced in claim 1", but the phrase "a loop current" is still shown in line 6 as being introduced in claim 2. A suggestion could be to revise the phrase from "to output a loop current" to "to a loop current output".
Claims 5-12 inherit the defects of the dependent claim 2.
Claim Rejections - 35 USC § 103
Applicant is reminded that claim mapping is provided as a courtesy to the
applicant, but applicant should consider a reference as a whole, as the entire reference
gives context to mapped sections.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 20110012683 A1), in view of Xu et al. (US 7545188 B1); hereinafter Lin, in view of Xu.
Regarding Claim 1, as best understood, Lin discloses a phase shift circuit [Fig. 1] comprising: a phase locked loop circuit [100] including a feedback divider [160] in a feedback loop [output node of 150 thru 160 to CLK2 signal]; and an adder circuit [130] configured to add a phase adjustment current [I2, which is injecting a phase current from secondary phase detector 120 to the adder 130, where I2 offsets (adjusts) the component (paragraph 0012)] to a loop current [I1] of the phase locked loop circuit. Lin does not explicitly disclose a circuit that maintains a non-zero phase difference between an output of the phase locked loop circuit and a reference clock in a steady state.
However, Xu discloses a circuit [Fig. 1] that maintains a non-zero phase difference between an output of the phase locked loop circuit [145] and a reference clock [105] in a steady state [Column 3, line 60 - Column 6, line 5]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the invention of Lin, in view of Xu, by adding a phase shift unit, for the benefit of generating phase shifting accuracy.
Regarding Claim 2, as best understood, Lin, in view of Xu, discloses the phase shift circuit of claim 1, wherein the phase locked loop circuit further includes: a first phase frequency detector (PFD) [within 110, paragraph 0003 discloses the phase detector comprises a PFD] configured to compare a phase between a reference clock [CLK1] and a feedback signal [CLK2] to output a first comparison signal [I1]; a first charge pump [within 110, paragraph 0003 discloses the phase detector comprises a charge pump circuit] configured to perform charging and discharging according to the first comparison signal to output the loop current; a loop filter [140] configured to filter the loop current; and a voltage-controlled oscillator [150] configured to oscillate according to a loop filter output voltage [Vc], wherein the feedback divider is configured to divide an output frequency of the voltage-controlled oscillator [CLK3] to supply the divided output frequency as the feedback signal to the first PFD.
Regarding Claim 3, as best understood, Lin, in view of Xu, discloses the phase shift circuit of claim 1, further comprising an adjustment current generation unit [120/300, paragraphs 0012-0014, Fig. 1-3] configured to output the phase adjustment current signal from a control word output [D] from a controller [320].
Regarding Claim 4, as best understood, Lin, in view of Xu, discloses the phase shift circuit of claim 3, wherein the adjustment current generation unit is a digital-to-analog converter [330] configured to convert the control word output from the controller to an analog signal [I2] and output the analog signal as the phase adjustment current signal.
Regarding Claim 5, as best understood, Lin, in view of Xu, discloses the phase shift circuit of claim 2, further comprising an adjustment current generation unit [120/300, paragraphs 0012-0014, Fig. 1-3] configured to generate the phase adjustment current signal and output the phase adjustment current signal to the adder circuit.
Regarding Claim 11, as best understood, Lin, in view of Xu, discloses the phase shift circuit of claim 5, wherein the adjustment current generation unit includes: a flip-flop [220] configured to receive an output of the feedback divider and synchronize the output with an output of the voltage-controlled oscillator to output the synchronized output; a second phase frequency detector (PFD) [within 120, paragraph 0003 discloses the phase detector comprises a PFD] configured to compare a phase between the reference clock and the output of the flip-flop to output a second comparison signal [I2]; and a second charge pump [within 120, paragraph 0003 discloses the phase detector comprises a charge pump circuit] configured to perform charging and discharging according to the second comparison signal to output the phase adjustment current.
Regarding Claim 12, as best understood, Lin, in view of Xu, discloses the phase shift circuit of claim 11, further comprising a digital-to-analog converter [330] configured to convert a control word output [D] from a controller [320] to an analog signal [I2], and supply the analog signal as an additional phase adjustment current signal to the adder circuit.
Claims 6 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Lin, in view of Xu, further in view of Yun (US 20120146692 A1); hereinafter Lin, in view of Xu, further in view of Yun.
Regarding Claim 6, as best understood, Lin, in view of Xu, does not explicitly disclose the phase shift circuit of claim 5, wherein the adjustment current generation unit includes: a divider configured to receive an output of the feedback divider and synchronize the output with an output of the voltage-controlled oscillator to output the synchronized output; a second phase frequency detector (PFD) configured to compare a phase between the reference clock and the output of the divider to output a second comparison signal; and a second charge pump configured to perform charging and discharging according to the second comparison signal to output the phase adjustment current.
However, Yun discloses a phase shift circuit [Fig. 1], wherein the adjustment current generation unit includes: a divider configured to receive an output of the feedback divider and synchronize the output with an output of the voltage-controlled oscillator to output the synchronized output [paragraphs 0013-0014]; a second phase frequency detector (PFD) [104] configured to compare a phase between the reference clock [FREF] and the output of the divider to output a second comparison signal [UP2/DN2]; and a second charge pump [108] configured to perform charging and discharging according to the second comparison signal to output the phase adjustment current. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the invention of Lin, in view of Xu, further in view of Yun, for the purpose of phase shifting accuracy.
Regarding Claim 8, as best understood, Lin, in view of Xu, further in view of Yun, discloses the phase shift circuit of claim 6, further comprising a delay locked loop [Yun, 118] configured to delay the output of the voltage-controlled oscillator to supply the output as a synchronization input of the divider [FOUT].
Regarding Claim 9, as best understood, Lin, in view of Xu, further in view of Yun, discloses the phase shift circuit of claim 8, wherein the delay locked loop is a digital delay locked loop configured to delay the output of the voltage-controlled oscillator according to a delay control word to supply the output as the synchronization input of is the divider [Yun, paragraph 0045].
Claims 7 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Lin, in view of Xu and Yun, further in view of Kim et al. (US 20210013888 A1); hereinafter Lin, in view of Xu and Yun, further in view of Kim.
Regarding Claim 7, as best understood, Lin, in view of Xu, further in view of Yun, does not explicitly disclose the phase shift circuit of claim 6, further comprising: a first random charge/discharge switching unit configured to connect a plurality of first current sources and one arbitrarily selected among the plurality of first current sources according to the first comparison signal to a charge/discharge input of the first charge pump; and a second random charge/discharge switching unit configured to connect a plurality of second current sources and one arbitrarily selected among the plurality of second current sources according to the second comparison signal to a charge/discharge input of the second charge pump.
However, Kim discloses wherein a phase shift circuit [Fig. 1/2/8/9; paragraphs 0026, 0082], further comprising: a first random charge/discharge switching unit [TB1] configured to connect a plurality of first current sources [paragraphs 0093, 0099] and one arbitrarily selected among the plurality of first current sources according to the first comparison signal to a charge/discharge input of the first charge pump [ICP1]; and a second random charge/discharge switching unit [TB2] configured to connect a plurality of second current sources [paragraphs 0093, 0099] and one arbitrarily selected among the plurality of second current sources according to the second comparison signal to a charge/discharge input of the second charge pump [ICP2]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the invention of Lin, in view of Xu and Yun, further in view of Kim, for the purpose of stabilizing the charge pump.
Regarding Claim 10, as best understood, Lin, in view of Xu and Yun, further in view of Kim, discloses the phase shift circuit of claim 7, further comprising a digital-to-analog converter [Lin, 330] configured to convert a control word output [Lin, D] from a controller [Lin, 320] to an analog signal [Lin, I2], and supply the analog signal as an additional phase adjustment signal to the adder circuit.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Amit Bhatia whose telephone number is (571)272-4410. The examiner can normally be reached Monday-Friday 8:30am-4:30pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch can be reached at (571) 270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Amit R Bhatia/Examiner, Art Unit 2836
/REGIS J BETSCH/SPE, Art Unit 2836
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