DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/27/2025 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Modi et al. (US 10924096, hereinafter “Modi”) and further in view of Meswani et al. (US 20170168546, hereinafter “Meswani”).
Regarding claim 1, Modi discloses,
A multilane transmitter (FIG. 2A depicts a block diagram of an exemplary transmitter having multiple lanes. In this depicted example, a transmitter 200A includes N lanes (or also referred to as channels) for data transmission. N may be any positive integer, Col. 7; lines 37-40), comprising:
a plurality of transmitter lane circuits (a transmitter 200A includes N lanes (or also referred to as channels) for data transmission. N may be any positive integer, Col. 7; lines 37-40 and Fig. 2A-2C); and
a phase lock circuit (Fig. 2A; PLL), comprising an oscillating circuit (A phase-locked loop (PLL) is a frequency control circuit that generates an output signal whose phase is related to the phase of an input signal. A frequency oscillator and a phase detector in a feedback loop are often used to form a PLL, Col. 1; lines 29-34), wherein a oscillating circuit is configured to provide one clock signal corresponding to the transmitter lane circuits (The transmitter 200A receives an initial clock signal INICLK (e.g., provided by a phase-locked-loop PLL) and distributes the initial clock signal INICLK to each of its lanes. Because of the natural characteristics of a transmitter 200A, the initial clock signal INICLK may travel different distances before the respective PCS of the lanes L1-LN receive the clock signal, Col. 7; lines 60; Col. 8; lines 6).”
However, Modi does not disclose, the oscillating circuit comprises a plurality of logic units,, a clock receiving terminal of each of the transmitter lane circuits is coupled to an output terminal of each of the logic units, wherein the oscillating circuit is a ring oscillator.
In the same field of endeavor, Meswani discloses the oscillating circuit (ring oscillator 220) comprises a plurality of logic units (A ring oscillator is a circuit composed of a cascaded chain of inverters), a clock receiving terminal of each of the transmitter lane circuits is coupled to an output terminal of each of the logic units, wherein the oscillating circuit is a ring oscillator, wherein the oscillating circuit is a ring oscillator (The apparatus 200 includes an encoder 210, frequency control unit 220, one or more execution lanes 230, (designated L.sub.0, L.sub.1, . . . , L.sub.N), and one or more power steering supplies 240, (designated S.sub.0, S.sub.1, . . . , S.sub.N). The encoder 210 is in communication with the ring oscillator 220 and the power steering supplies 240. The ring oscillator is connected across the rail voltage (V.sub.DD) and the reference voltage (V.sub.SS), and to each of the execution lanes 230, [0016]-[0018]).
Therefore, it would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify Modi by specifically providing the oscillating circuit comprises a plurality of logic units,, a clock receiving terminal of each of the transmitter lane circuits is coupled to an output terminal of each of the logic units, wherein the oscillating circuit is a ring oscillator, as taught by Meswani for the purpose of performing inter-lane power management includes deactivating execution lanes that are not computing useful results and redistributing power to active execution lanes [0011].
Regarding claim 2, the combination of Modi and Meswani everything claimed as applied above (see claim 1), further Modi discloses,
wherein the logic units are differential delay units (the initial clock signal INICLK may travel different distances before the respective PCS of the lanes L1-LN receive the clock signal. The different distances may result in different time delays between the clock signal received at the lanes. In this depicted example, the corresponding clock signal received by each lane L1-LN is expressed as USERCLK_1, USERCLK_N, respectively, Col. 7; lines 60-Col. 8; lines 56 and Fig. 2B-2C).
Regarding claim 3, the combination of Modi and Meswani everything claimed as applied above (see claim 1), in addition Meswani discloses,
wherein the logic units are inverters (A ring oscillator is a circuit composed of a cascaded chain of inverters).
Regarding claim 4, the combination of Modi and Meswani everything claimed as applied above (see claim 2), in addition Meswani discloses,
wherein output terminals of the logic units are coupled to the clock receiving terminal of one of the transmitter lane circuits (The apparatus 200 includes an encoder 210, frequency control unit 220, one or more execution lanes 230, (designated L.sub.0, L.sub.1, . . . , L.sub.N), and one or more power steering supplies 240, (designated S.sub.0, S.sub.1, . . . , S.sub.N). The encoder 210 is in communication with the ring oscillator 220 and the power steering supplies 240. The ring oscillator is connected across the rail voltage (V.sub.DD) and the reference voltage (V.sub.SS), and to each of the execution lanes 230, [0016]-[0018]).
Regarding claim 5, the combination of Modi and Meswani everything claimed as applied above (see claim 4), further Modi discloses,
wherein the clock signals corresponding to the transmitter lane circuits have a fixed phase (FIGS. 3B-3Fdepicts exemplary circuit blocks used to form the first exemplary skew compensation circuit and exemplary timing diagrams of phase detector output signals, Col. 12; lines 13-Col. 13; lines 30).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Modi, in view of Meswani and further in view of Hwang (US 2018010762, hereinafter “Hwang”).
Regarding claim 6, the combination of Modi and Meswani discloses everything claimed as applied above (see claim 5), however the combination of Modi and Meswani does not explicitly disclose, wherein a quantity of logic units is the same as a quantity of the transmitter lane circuits.
In the same field of endeavor, Hwang discloses, wherein a quantity of logic units is the same as a quantity of the transmitter lane circuits (The first data transmitter 140-1 may include an N-to-1 serializer 241-1, a buffer 242-1, an output signal storage circuit 243-1, and a D-flip flop (DFF) 244-1. Similarly, the M.sup.th data transmitter 140-M may include an N-to-1 serializer 241-M, a buffer 242-M, an output signal storage circuit 243-M, and a D-flip flop (DFF) 244-M, [0027]).
Therefore, it would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify Modi by specifically providing wherein a quantity of logic units is the same as a quantity of the transmitter lane circuits, as taught by Hwang for the purpose of providing a method of testing a data transmission system transmitting a plurality of data through a plurality of data transmitters included in a plurality of transmission lanes [0006].
Allowable Subject Matter
Claims 7-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 7, the following is a statement of reasons for the indication of allowable subject matter: the closest prior art, Modi, Meswani and Hwang, whether taken alone or combination, do not teach or suggest the following novel features:
“the transmitter comprises wherein distances from the clock receiving terminals of the transmitter lane circuits the output terminals of the logic units to which the clock receiving terminals are coupled are the same”, in combination with the other limitations in claims 1, 2 and 4-6.
Claims 8-11 are allowed as those inherit the allowable subject matter from
claim 7.
Prior Art of the Record:
The prior art made of record not relied upon and considered pertinent to
Applicant’s disclosure:
US 10804904: A multi-lane transmitter and method of detecting a sync loss are provided. The method includes generating a high-speed clock signal and a sync reset signal synchronized to the high-speed clock signal. A sync loss pulse is generated based on the high-speed clock signal, and the sync loss pulse is provided to each of plural serializer circuits.
US 20190138488: An integrated circuit includes a first multi-lane interface having a plurality of first lanes, a second multi-lane interface having a plurality of second lanes; a first layer of clock lane selection units arranged to select one or two of the first and second lanes and output signals on the one or two selected lanes.
US 9419786: A multi-lane serial link signal receiving system includes a clock generating circuit and a plurality of data receiving channels. The clock generating circuit provides a fundamental clock signal. Each of the data receiving channels receives an input signal and the fundamental clock signal, and includes a phase detecting circuit, a multi-order digital clock data recovery circuit and a phase adjusting circuit.
Conclusion
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/GOLAM SOROWAR/ Primary Examiner, Art Unit 2641