DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 10/30/2025 have been fully considered but they are not persuasive because of the following reason:
Applicant’s argues that:
Claims 1-5 stand rejected under 35 U.S.C. § 103 as being unpatentable over Modi, US 10924096 in view of Meswani, US 20170168546. Claim 6 stands rejected under 35 U.S.C. § 103 as being unpatentable over Modi in view of Meswani, and further in view of Hwang, US 2018/010762. These rejections are respectfully traversed.
A complete discussion of the Examiner's rejections is set forth in the Office Action, and is not being repeated here. Without conceding to the propriety of the Examiner's rejections, but merely to timely advance the prosecution of the application, as the Examiner will note, independent claim 1 has been amended to more clearly clarify the present invention. In particular, independent claim 1 now recites a combination of elements including "a plurality of transmitter lane circuits; and a phase lock circuit, comprising an oscillating circuit, wherein the oscillating circuit is configured to provide one clock signal corresponding to the transmitter lane circuits, the oscillating circuit comprises a plurality of logic units, a clock receiving terminal of each of the transmitter lane circuits is coupled to an output terminal of each of the logic units; wherein the oscillating circuit is a ring oscillator, and wherein the logic units are differential delay units" (emphasis added).
The Office Action asserts that Modi discloses "a plurality of transmitter lane circuits" and "a phase lock circuit comprising an oscillating circuit, wherein the oscillating circuit is configured to provide one clock signal corresponding to the transmitter lane circuits". The Office Action further asserts that Meswani discloses "the oscillating circuit comprising a plurality of logic units,"a clock receiving terminal of each of the transmitter lane circuits is coupled to an output terminal of each of the logic units" and "the oscillating circuit being a ring oscillator."
Applicant respectfully disagrees and submits that neither Modi nor Meswani discloses "a clock receiving terminal of each of the transmitter lane circuits is coupled to an output terminal of each of the logic units" and "wherein the logic units are differential delay units". Therefore, Applicant respectfully submits that the combined teachings of Modi and Meswani fail to disclose every element of the claimed invention and does not render the claimed invention obvious……..In view of the above, Meswani discloses an inter-lane power management apparatus including an encoder 210, a frequency control unit 220 (i.e., a ring oscillator 220), a plurality of execution lanes 230, and power steering supplies 240. In this structure, the ring oscillator 220 is connected across the rail voltage VDD and the reference voltage VSS, and is connected to the execution lanes 230. Each execution lane 230 is further connected to its corresponding power steering supply 240 to VDD and also to VSS. In other words, Meswani merely discloses that the ring oscillator 220, as an integrated module, is connected to all of the execution lanes 230 collectively, and the execution lanes 230 are not coupled to the output terminals of the individual inverters within the ring oscillator 220. In contrast, in claim 1, the clock receiving terminal of each of the transmitter lane circuits is coupled to the output terminal of each of the logic units, that is, the clock receiving terminals of the transmitter lane circuits are respectively coupled to different positions (i.e., output terminals of different logic units).Accordingly, Meswani does not disclose "a clock receiving terminal of each of the transmitter lane circuits is coupled to an output terminal of each of the logic units" as recited in claim 1.
Examiner respectfully disagrees for the following reason:
Applicant argues that the applied combination of Modi in view of Meswani fails to disclose (i) “a clock receiving terminal of each of the transmitter lane circuits is coupled to an output terminal of each of the logic units,” and (ii) “wherein the logic units are differential delay units.” Applicant's arguments are not persuasive because they rely on an unduly narrow interpretation of the claim language and fail to properly consider the express disclosures, inherent characteristics, and functional equivalence of the cited references.
With respect to the limitation “wherein the logic units are differential delay units,” Applicant asserts that Modi does not describe the internal logic units of the PLL and therefore cannot teach differential delay units. This argument is unpersuasive. The claim does not require that the differential delay units be expressly identified as internal oscillator stages of the PLL, nor does it require that such logic units be physically located within the PLL block itself. Rather, the claim broadly recites logic units that provide differential delay in the generation of transmitter lane clocks. As shown in FIGS. 2A-2C and described in Col. 7; lines 37-Col. 10; lines 3, Modi discloses a multi-lane transmitter in which an initial clock signal (INICLK) is distributed to multiple transmitter lanes (L1-LN), and in which different propagation delays are intentionally introduced along the clock paths via routing traces (220a-220c, 220b', 220c'). Modi further discloses active skew compensation circuits (225a-225c) that receive multiple delayed versions of the clock signal, compare those signals, and calculate and apply a differential amount of delay to one clock signal relative to another in order to generate aligned user clocks (USERCLK_1', USERCLK_2', USERCLK_3'). By their disclosed operation, these skew compensation circuits apply differential delay between clock signals so that the resulting outputs show controlled phase alignment across lanes.
Accordingly, even though Modi does not explicitly use the phrase “differential delay unit,” the disclosed skew compensation circuits and associated delay paths perform the same function, in the same manner, to achieve the same result as differential delay units, namely, differentially delaying clock signals to achieve phase alignment. Examiner respectfully submits that it is well established that a claim limitation is satisfied when the prior art discloses the same structure or function, even if different terminology is used. Therefore, Modi discloses logic units that are differential delay units within the meaning of the claim.
Moreover, Modi's disclosure is not limited to passive routing delays. Modi expressly teaches active skew compensation circuits that receive multiple clock inputs and calculate and apply differential delays based on differences between those inputs (see Col. 7; lines 37-Col. 10; lines 3). Such circuits necessarily include controllable delay elements operating on the relative timing of multiple clock paths, which is the defining characteristic of differential delay logic. The fact that these delay logic units are implemented downstream of the PLL output does not remove them from being logic units involved in generating the transmitter lane clocks, particularly where the claim does not require any restriction on the physical location of the differential delay units. Accordingly, Modi alone teaches the use of differential delay units for generating and aligning transmitter lane clocks.
With respect to the limitation “the oscillating circuit comprising a plurality of logic units, a clock receiving terminal of each of the transmitter lane circuits is coupled to an output terminal of each of the logic units, wherein the oscillating circuit is a ring oscillator”, Applicant argues that Meswani merely discloses a ring oscillator connected to execution lanes as an integrated block and does not disclose coupling to output terminals of individual logic units. This argument is also unpersuasive. Meswani expressly discloses a frequency control unit implemented as a ring oscillator (220) and further discloses that the ring oscillator is connected to each of the execution lanes (230) (see paragraphs [0016]-[0017]). A ring oscillator, by its very nature, comprises a plurality of logic units (delay stages), the outputs of which collectively form the oscillating signal. When such a ring oscillator supplies clock signals to multiple lane circuits, the clock receiving terminals of those lane circuits are necessarily coupled, either directly or indirectly, to output terminals of the internal logic units that form the oscillator. The claim does not require that each inverter or delay stage output be separately exposed, explicitly labeled, or directly connected without intervening circuitry.
Coupling through conventional buffering, routing, or clock distribution circuitry is sufficient to meet the claim language. Accordingly, the claimed coupling is satisfied when the lane clock receiving terminals receive clock signals derived from the outputs of the oscillator's internal logic units, which is exactly what Meswani discloses.
When Modi and Meswani are considered together, the combination clearly teaches or renders obvious the claimed subject matter. Meswani provides the oscillating circuit implemented as a ring oscillator comprising a plurality of logic units, while Modi provides a detailed multi-lane transmitter environment in which lane-specific clocks are generated, subjected to different delays, compared, and aligned using differential delay logic. One of ordinary skill in the art would have readily understood how to implement Meswani's ring oscillator as the clock source in Modi's multi-lane transmitter and how to employ differential delay logic, as taught by Modi, to distribute and align oscillator-derived clocks across the transmitter lanes. Such integration represents the predictable application of known clock generation and skew alignment techniques to address lane-to-lane timing differences in a multi-lane transmitter and would not require inventive skill.
Accordingly, Applicant's arguments do not overcome the rejection. Modi discloses logic units that function as differential delay units through its skew compensation and delay logic, Meswani discloses a ring oscillator comprising multiple logic units coupled to execution lanes, and the combination teaches or renders obvious the claimed limitations, including that each transmitter lane clock receiving terminal is coupled to an output terminal of logic units of an oscillating ring oscillator. Therefore, the rejection of claim 1 under 35 U.S.C. § 103 is maintained. Claims 3-6, which depend therefrom, fall with claim 1 absent additional limitations that patentably distinguish over the applied prior art.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Modi et al. (US 10924096, hereinafter “Modi”) and further in view of Meswani et al. (US 20170168546, hereinafter “Meswani”).
Regarding claim 1, Modi discloses,
A multilane transmitter (FIG. 2A depicts a block diagram of an exemplary transmitter having multiple lanes. In this depicted example, a transmitter 200A includes N lanes (or also referred to as channels) for data transmission. N may be any positive integer, Col. 7; lines 37-40), comprising:
a plurality of transmitter lane circuits (a transmitter 200A includes N lanes (or also referred to as channels) for data transmission. N may be any positive integer, Col. 7; lines 37-40 and Fig. 2A-2C); and
a phase lock circuit (Fig. 2A; PLL), comprising an oscillating circuit (A phase-locked loop (PLL) is a frequency control circuit that generates an output signal whose phase is related to the phase of an input signal. A frequency oscillator and a phase detector in a feedback loop are often used to form a PLL, Col. 1; lines 29-34), wherein a oscillating circuit is configured to provide one clock signal corresponding to the transmitter lane circuits (The transmitter 200A receives an initial clock signal INICLK (e.g., provided by a phase-locked-loop PLL) and distributes the initial clock signal INICLK to each of its lanes. Because of the natural characteristics of a transmitter 200A, the initial clock signal INICLK may travel different distances before the respective PCS of the lanes L1-LN receive the clock signal, Col. 7; lines 60; Col. 8; lines 6), and
wherein the logic units are differential delay units (the initial clock signal INICLK may travel different distances before the respective PCS of the lanes L1-LN receive the clock signal. The different distances may result in different time delays between the clock signal received at the lanes. In this depicted example, the corresponding clock signal received by each lane L1-LN is expressed as USERCLK_1, USERCLK_N, respectively, Col. 7; lines 60-Col. 8; lines 56 and Fig. 2B-2C).
However, Modi does not disclose, the oscillating circuit comprises a plurality of logic units,, a clock receiving terminal of each of the transmitter lane circuits is coupled to an output terminal of each of the logic units, wherein the oscillating circuit is a ring oscillator.
In the same field of endeavor, Meswani discloses the oscillating circuit (ring oscillator 220) comprises a plurality of logic units (A ring oscillator is a circuit composed of a cascaded chain of inverters), a clock receiving terminal of each of the transmitter lane circuits is coupled to an output terminal of each of the logic units, wherein the oscillating circuit is a ring oscillator, wherein the oscillating circuit is a ring oscillator (The apparatus 200 includes an encoder 210, frequency control unit 220, one or more execution lanes 230, (designated L.sub.0, L.sub.1, . . . , L.sub.N), and one or more power steering supplies 240, (designated S.sub.0, S.sub.1, . . . , S.sub.N). The encoder 210 is in communication with the ring oscillator 220 and the power steering supplies 240. The ring oscillator is connected across the rail voltage (V.sub.DD) and the reference voltage (V.sub.SS), and to each of the execution lanes 230, [0016]-[0018]).
Therefore, it would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify Modi by specifically providing the oscillating circuit comprises a plurality of logic units,, a clock receiving terminal of each of the transmitter lane circuits is coupled to an output terminal of each of the logic units, wherein the oscillating circuit is a ring oscillator, as taught by Meswani for the purpose of performing inter-lane power management includes deactivating execution lanes that are not computing useful results and redistributing power to active execution lanes [0011].
Regarding claim 3, the combination of Modi and Meswani everything claimed as applied above (see claim 1), in addition Meswani discloses,
wherein the logic units are inverters (A ring oscillator is a circuit composed of a cascaded chain of inverters).
Regarding claim 4, the combination of Modi and Meswani everything claimed as applied above (see claim 1), in addition Meswani discloses,
wherein output terminals of the logic units are coupled to the clock receiving terminal of one of the transmitter lane circuits (The apparatus 200 includes an encoder 210, frequency control unit 220, one or more execution lanes 230, (designated L.sub.0, L.sub.1, . . . , L.sub.N), and one or more power steering supplies 240, (designated S.sub.0, S.sub.1, . . . , S.sub.N). The encoder 210 is in communication with the ring oscillator 220 and the power steering supplies 240. The ring oscillator is connected across the rail voltage (V.sub.DD) and the reference voltage (V.sub.SS), and to each of the execution lanes 230, [0016]-[0018]).
Regarding claim 5, the combination of Modi and Meswani everything claimed as applied above (see claim 4), further Modi discloses,
wherein the clock signals corresponding to the transmitter lane circuits have a fixed phase (FIGS. 3B-3Fdepicts exemplary circuit blocks used to form the first exemplary skew compensation circuit and exemplary timing diagrams of phase detector output signals, Col. 12; lines 13-Col. 13; lines 30).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Modi, in view of Meswani and further in view of Hwang (US 2018010762, hereinafter “Hwang”).
Regarding claim 6, the combination of Modi and Meswani discloses everything claimed as applied above (see claim 5), however the combination of Modi and Meswani does not explicitly disclose, wherein a quantity of logic units is the same as a quantity of the transmitter lane circuits.
In the same field of endeavor, Hwang discloses, wherein a quantity of logic units is the same as a quantity of the transmitter lane circuits (The first data transmitter 140-1 may include an N-to-1 serializer 241-1, a buffer 242-1, an output signal storage circuit 243-1, and a D-flip flop (DFF) 244-1. Similarly, the M.sup.th data transmitter 140-M may include an N-to-1 serializer 241-M, a buffer 242-M, an output signal storage circuit 243-M, and a D-flip flop (DFF) 244-M, [0027]).
Therefore, it would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify Modi by specifically providing wherein a quantity of logic units is the same as a quantity of the transmitter lane circuits, as taught by Hwang for the purpose of providing a method of testing a data transmission system transmitting a plurality of data through a plurality of data transmitters included in a plurality of transmission lanes [0006].
Allowable Subject Matter
Claims 7-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 7, the following is a statement of reasons for the indication of allowable subject matter: the closest prior art, Modi, Meswani and Hwang, whether taken alone or combination, do not teach or suggest the following novel features:
“the transmitter comprises wherein distances from the clock receiving terminals of the transmitter lane circuits the output terminals of the logic units to which the clock receiving terminals are coupled are the same”, in combination with the other limitations in claims 1, 2 and 4-6.
Claims 8-11 are allowed as those inherit the allowable subject matter from
claim 7.
Prior Art of the Record:
The prior art made of record not relied upon and considered pertinent to
Applicant’s disclosure:
US 10804904: A multi-lane transmitter and method of detecting a sync loss are provided. The method includes generating a high-speed clock signal and a sync reset signal synchronized to the high-speed clock signal. A sync loss pulse is generated based on the high-speed clock signal, and the sync loss pulse is provided to each of plural serializer circuits.
US 20190138488: An integrated circuit includes a first multi-lane interface having a plurality of first lanes, a second multi-lane interface having a plurality of second lanes; a first layer of clock lane selection units arranged to select one or two of the first and second lanes and output signals on the one or two selected lanes.
US 9419786: A multi-lane serial link signal receiving system includes a clock generating circuit and a plurality of data receiving channels. The clock generating circuit provides a fundamental clock signal. Each of the data receiving channels receives an input signal and the fundamental clock signal, and includes a phase detecting circuit, a multi-order digital clock data recovery circuit and a phase adjusting circuit.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GOLAM SOROWAR whose telephone number is (571)270-3761. The examiner can normally be reached Mon-Fri: 8:30AM-5PM.
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/GOLAM SOROWAR/ Primary Examiner, Art Unit 2641
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