Office Action Predictor
Last updated: April 15, 2026
Application No. 18/113,264

DATABASE SYNCHRONIZATION BASED ON MEMORY TRANSFER

Non-Final OA §103
Filed
Feb 23, 2023
Examiner
HALE, BROOKS T
Art Unit
2166
Tech Center
2100 — Computer Architecture & Software
Assignee
Hewlett Packard Enterprise Development LP
OA Round
4 (Non-Final)
49%
Grant Probability
Moderate
4-5
OA Rounds
3y 0m
To Grant
64%
With Interview

Examiner Intelligence

Grants 49% of resolved cases
49%
Career Allow Rate
36 granted / 74 resolved
-6.4% vs TC avg
Strong +16% interview lift
Without
With
+15.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 0m
Avg Prosecution
37 currently pending
Career history
111
Total Applications
across all art units

Statute-Specific Performance

§101
22.3%
-17.7% vs TC avg
§103
61.3%
+21.3% vs TC avg
§102
10.1%
-29.9% vs TC avg
§112
3.0%
-37.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 74 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Status Claims 1-20 are pending. Claims 1-5, 7-9, 11-20 are rejected. Claims 6 and 10 are objected. Response to Arguments Applicant’s arguments with respect to claims 1-20 have been fully considered and are persuasive. Upon further consideration, and in view of applicant’s amendments, a new grounds of rejection is made in view of newly cited references Lin and Voigt. Allowable Subject Matter Claims 6 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 6: The prior arts of the record lack disclosure or inference of the limitation “wherein a respective of the first and second databases is an in-memory key-value-store (memkvs)”. The closest prior art of the record, Lee, teaches “a memory for storing various elements” but does not teach “an in-memory key-value-store”. Regarding claim 10: The prior arts of the record lack disclosure or inference of the steps “wherein the direct memory-transfer operation further comprises transferring a cyclic redundancy check (CRC) value from a first data structure associated with the first database of the active unit to a second data structure associated with the second database of the standby unit, and wherein the CRC value is computed based on the content of the first memory block”. The closest prior art of the record, Voigt, teaches a direct memory-transfer operation but doesn’t teach a direct memory-transfer operation further comprises transferring a cyclic redundancy check (CRC) value. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-5, 7-9, 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 6721735 B1) hereafter Lee in view of Lin et al (US 20220179812 A1) hereafter Lin further in view of Voigt (US 20170052723 A1) hereafter Voigt Regarding claim 1, Lee teaches a method comprising: receiving, by an appliance from a database management application on an active unit of the appliance, a notification indicating that a first memory block has been updated due to an update to a first entry in a first database of the active unit, wherein the first memory block stores the first entry in a first memory segment of a first memory device of the active unit (Para 9, detecting a change to at least one database record in any of a first plurality of databases based on a first set of parameters, and notifying a controller of the change, “database record” is analogous to “first memory block”); identifying, by the appliance, a second memory block that stores a corresponding second entry in a second database of a standby unit of the appliance, wherein the second memory block is in a second memory segment of a second memory device of the standby unit (Para 30, the DSS 112 communicates with the first plurality of databases 124 and the second plurality of databases 125 via a communications link 130); and replacing, by the appliance, content of the second memory block with content of the first memory block using a memory-transfer operation to synchronize the first and second entries (Para 9, updating, according to the detected change, each of a second plurality of databases containing the respective database record in response to a determination that the change falls within a second parameter). Lee does not appear to explicitly teach wherein the first memory segment is outside of an accessible memory range of a first operating system of the active unit; and wherein the second memory segment is outside of an accessible memory range of a second operating system of the standby unit. In analogous art, Lin teaches wherein the first memory segment is outside of an accessible memory range of a first operating system of the active unit; and wherein the second memory segment is outside of an accessible memory range of a second operating system of the standby unit (Para 0028, These communication primitives may include operating system bypass send and receive operations as well as remote direct memory access operations. RDMA is a set of technologies that enable the movement of data from the memory of one device directly, or at least substantially directly, into the memory of another device without involving the operating system of either device). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Lee to include the teaching of Lin. One of ordinary skill in the art would be motivated to implement this modification in order improve system performance, as taught by Lin (Para 0050, Because the operating system is bypassed, the RDMA quickly moves data from a system to the memory of the remote host through a network. Therefore, a large quantity of CPU resources may be saved, a system throughput is improved, overheads of external memory replication and context switching are eliminated, and memory bandwidth can be released to improve application system performance). Lee in view of Lin does not appear to explicitly teach using a direct memory-transfer operation managed by a direct memory access (DMA) controller of the appliance independent of the first operating system and the second operating system to synchronize the first and second entries. In analogous art, Voight teaches using a direct memory-transfer operation managed by a direct memory access (DMA) controller of the appliance independent of the first operating system and the second operating system to synchronize the first and second entries (Para 0012, Data may be transferred from the application server to the remote server using a remote direct memory access (RDMA)). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Lee in view of Lin to include the teaching of Voight. One of ordinary skill in the art would be motivated to implement this modification in order to reduce CPU overhead, as taught by Voight (Para 0012, RDMAs may reduce CPU overhead in a data transfer). Regarding claim 2, Lee in view of Lin further in view of Voight teaches the method of claim 1, further comprising presenting, to the DMA controller of the appliance, the first and second memory segments as a unified flat memory space (Lee, Para 30, The processor 112-C4 cooperates with conventional support circuitry 112-C6 such as power supplies, clock circuits, cache memory and the like as well as circuits that assist in executing the software routines stored in the memory 112-C8). Regarding claim 3, Lee in view of Lin further in view of Voight teaches the method of claim 2, wherein the active and standby units are housed in a chassis of the appliance, and wherein the DMA controller comprises a processor of the chassis outside of the active and standby units (Lee, Para 4, the communications system 100 of FIG. 1 comprises a software manager 102, a fault manager 104, an inventory manager 106, a provisioning manager 108, a tree manager 110, a Database Synchronization Server (DSS) 112, a DSS controller 112-C, a Digital Cross Connect Network Manager (DCS-NM) 114, a DCS element management system 116, a Synchronous Optical Network Manager (SONET-NM) 118, a SONET element management system 120, a domain manager 122, a first plurality of independent databases 124-1 through 124-N). Regarding claim 4, Lee in view of Lin further in view of Voight teaches the method of claim 1, wherein the notification is triggered in response to completion of a transaction that updates the first entry, and wherein the database management application determines that the first memory block is updated by the transaction (Lee, Para 33, The last update.sub.1, field 320 is transparent and indicates the date and time records RA31 through RA33 were updated for DCS identifier field 310). Regarding claim 5, Lee in view of Lin further in view of Voight teaches the method of claim 1, wherein the first and second entries store same state information for the active and secondary units, respectively, and wherein the state information facilitates a failover from the active unit to the standby unit (Lee, Para 29, the scheduled bulk updates are still completed to protect against occurrences such as failure to notify DSS 112 of a change in a database, communication failure and DSS 112 failure). Regarding claim 7, Lee in view of Lin further in view of Voight teaches the method of claim 1, wherein the direct memory-transfer operation further comprises data replication from the first memory block to the second memory block using DMA (Voight, Para 0012, Data may be transferred from the application server to the remote server using a remote direct memory access). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Lee in view of Lin to include the teaching of Voight. One of ordinary skill in the art would be motivated to implement this modification in order to reduce CPU overhead, as taught by Voight (Para 0012, RDMAs may reduce CPU overhead in a data transfer). Regarding claim 8, Lee in view of Lin further in view of Voight teaches the method of claim 7, wherein the active and standby units are coupled via an interconnect fabric within the appliance, and wherein the interconnect fabric supports DMA-based data replication (Lee, Para 4, a Digital Cross Connect Network Manager). Regarding claim 9, Lee in view of Lin further in view of Voight teaches the method of claim 8, wherein the direct memory-transfer operation further comprises storing the content of the first memory block in a buffer of the interconnect fabric (Lin, Para 0049, Direct memory access (DMA) is a working manner in which input/output (I/O) switching is performed by hardware). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Lee to include the teaching of Lin. One of ordinary skill in the art would be motivated to implement this modification in order improve system performance, as taught by Lin (Para 0050, Because the operating system is bypassed, the RDMA quickly moves data from a system to the memory of the remote host through a network. Therefore, a large quantity of CPU resources may be saved, a system throughput is improved, overheads of external memory replication and context switching are eliminated, and memory bandwidth can be released to improve application system performance). Claim 11 is the apparatus claim corresponding to the method claim 1, and is analyzed and rejected accordingly. Claim 12 is the apparatus claim corresponding to the method claim 2, and is analyzed and rejected accordingly. Claim 13 is the apparatus claim corresponding to the method claim 3, and is analyzed and rejected accordingly. Claim 14 is the apparatus claim corresponding to the method claim 4, and is analyzed and rejected accordingly. Claim 15 is the apparatus claim corresponding to the method claim 5, and is analyzed and rejected accordingly. Claim 16 is the apparatus claim corresponding to the method claim 6, and is analyzed and rejected accordingly. Claim 17 is the apparatus claim corresponding to the method claim 7, and is analyzed and rejected accordingly. Claim 18 is the apparatus claim corresponding to the method claim 8, and is analyzed and rejected accordingly. Claim 19 is the apparatus claim corresponding to the method claim 9, and is analyzed and rejected accordingly. Claim 20 is the medium claim corresponding to the method claim 1, and is analyzed and rejected accordingly. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Brooks Hale whose telephone number is 571-272-0160. The examiner can normally be reached 9am to 5pm est. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sanjiv Shah can be reached on (571) 272-4098. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /B.T.H./Examiner, Art Unit 2166 /SANJIV SHAH/Supervisory Patent Examiner, Art Unit 2166
Read full office action

Prosecution Timeline

Feb 23, 2023
Application Filed
Apr 22, 2024
Non-Final Rejection — §103
May 16, 2024
Interview Requested
Jun 14, 2024
Examiner Interview Summary
Jul 29, 2024
Response Filed
Oct 08, 2024
Final Rejection — §103
Dec 17, 2024
Response after Non-Final Action
Feb 28, 2025
Request for Continued Examination
Mar 07, 2025
Response after Non-Final Action
Jun 14, 2025
Non-Final Rejection — §103
Sep 17, 2025
Response Filed
Dec 17, 2025
Non-Final Rejection — §103
Jan 15, 2026
Response after Non-Final Action
Jan 15, 2026
Response Filed
Mar 30, 2026
Response Filed

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12572584
DATA STORAGE METHOD AND APPARATUS BASED ON BLOCKCHAIN NETWORK
2y 5m to grant Granted Mar 10, 2026
Patent 12561344
CLASSIFICATION INCLUDING CORRELATION
2y 5m to grant Granted Feb 24, 2026
Patent 12561309
CORRELATION OF HETEROGENOUS MODELS FOR CAUSAL INFERENCE
2y 5m to grant Granted Feb 24, 2026
Patent 12561375
ENHANCED SEARCH RESULT GENERATION USING MULTI-DOCUMENT SUMMARIZATION
2y 5m to grant Granted Feb 24, 2026
Patent 12555669
SYSTEMS AND METHODS FOR GENERATING AN INTEGUMENTARY DYSFUNCTION NOURISHMENT PROGRAM
2y 5m to grant Granted Feb 17, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

4-5
Expected OA Rounds
49%
Grant Probability
64%
With Interview (+15.7%)
3y 0m
Median Time to Grant
High
PTA Risk
Based on 74 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in for Full Analysis

Enter your email to receive a magic link. No password needed.

Free tier: 3 strategy analyses per month