DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to applicant’s communication filed 21 May 2026, in response to the Office Action mailed 19 March 2026. The applicant’s remarks and any amendments to the claims or specification have been considered, with the results that follow.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-7, 11-15, and 18-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-7 of U.S. Patent No. 12,688,342 in view of Keller (US 2016/0098561).
As per claim 1, the claim is compared with claim 4 (which depends upon claim 1) of U.S. Patent No. 12,688,342—where any differences between them have been highlighted (in bold)—as follows:
Instant Application
U.S. Patent No. 12,688,342
An operating method of an electronic device which includes a processor performing simulation of target row refresh logic of a dynamic random access memory, the method comprising:
A device comprising: … initiate a simulator, trained to output a simulator parameter for a design of a semiconductor device [claim 1]
generating a first input tensor by the processor by using a generator network
generate an input tensor from the trained generator network, [claim 1]
obtaining a first score by the processor by inputting the input tensor to a target row refresh logic module
initiate a simulator, trained to output a simulator parameter for a design of a semiconductor device, to perform a black box operation on the input tensor and to output an output score as a result of the black box operation, [claim 1]
storing a pair of the generator network and the first score in an evolution pool by the processor when the first score is greater than a first threshold value
and to store the input tensor and the output score in the memory as the input tensor-score pair, store information used in the black box operation in the evolution pool when the output score is greater than a minimum score stored in the memory, [claim 1]
training a critic network based on the first input tensor and the first score by the processor when a number of times of iteration is smaller than a maximum number of times of iteration
initiate a critic network to train the sampled generator network in a back- propagation manner, [claim 1] … wherein the processor is configured to train the critic network and update the evolution pool until a number of iterations thereof reaches a preset maximum number [claim 4]
training the generator network based on a training result of the critic network by the processor when the number of times of iteration is smaller than the maximum number of times of iteration
initiate a critic network to train the sampled generator network in a back- propagation manner, [claim 1] … wherein the processor is configured to train the critic network and update the evolution pool until a number of iterations thereof reaches a preset maximum number [claim 4]
again performing the generating of the first input tensor, the obtaining of the first score, and the storing the pair of the generator network and the first score in the evolution pool by the processor when the number of times of iteration is smaller than the maximum number of times of iteration
initiate a critic network to train the sampled generator network in a back- propagation manner, [claim 1] … wherein the processor is configured to train the critic network and update the evolution pool until a number of iterations thereof reaches a preset maximum number [claim 4]
wherein the first input tensor includes patterns of row addresses
As illustrated above, claim 4 of U.S. Patent No. 12,688,342 claims all of the limitations set forth in the instant application, except for the simulation being performed being simulation of target row refresh logic of a dynamic random access memory, [and] wherein the first input tensor includes patterns of row addresses.
Keller teaches simulation of target row refresh logic of a dynamic random access memory as [various simulators may be used to simulate the computer assets (para. 0103, etc.) including refresh logic of rows of a DRAM memory (para. 0119, etc.), which can be used by the pattern modeling to produce a score for the hardware (paras. 0130, 0143, 0202, etc.)], [and] wherein the first input tensor includes patterns of row addresses [address lines associated with memory reads/writes can be exploited for detection of software contaminants (para. 0118, etc.) and for the row refresh only the row address is needed (para. 0119, etc.) creating hardware address and data bit patterns from data or address lines (paras. 0121-122, etc.)].
Patent ‘342 and Keller are analogous art, as they are within the same field of endeavor, namely simulating and malicious/attack/risk scoring computer hardware components.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to simulate row refresh logic of the DRAM memory as part of the modeling/scoring of the hardware components, utilizing row address patterns, as taught by Keller, as the simulator producing a simulator parameter for a design of a semiconductor device, in the claimed invention of Patent ‘342.
Keller provides motivation as [The read process in DRAM is destructive and removes the charge on the memory cells in an entire row, so there is a row of specialized latches on the chip called sense amplifiers, one for each column of memory cells, to temporarily hold the data. During a normal read operation the sense amplifiers, after reading and latching the data, rewrite the data in the accessed row before sending the bit from a single column to output. The normal read electronics on the chip has the ability to refresh an entire row of memory in parallel, significantly speeding up the refresh process. The refresh circuitry must perform a refresh cycle on each of the rows on the chip within the refresh time interval, to make sure that each cell gets refreshed (para. 0119, etc.) and particular exemplary embodiments analyze these characteristics which conceptually provide a fingerprint or fingerprints of what is anticipated and hence form a pattern or patterns. These patterns can be tracked, monitored and verified to be certain to a degree of probability or alternatively a quantified score that the hardware, firmware or software is not substantially different or modified and is only doing what was originally intended to be accomplished and that added, disabled or modified circuitry, code or algorithms have not been implemented and are not doing something unwanted behind the scenes (para. 0130) where address lines associated with memory reads/writes can be exploited for detection of software contaminants (para. 0118, etc.)].
As per claim 2, Patent ‘342/Keller teaches wherein the training of the critic network, the training of the generator network, the generating of the first input tensor, the obtaining of the first score, and the storing the pair of the generator network and the first score in the evolution pool are iteratively performed until the number of times of iteration reaches the maximum number of times of iteration [wherein the processor is configured to train the critic network and update the evolution pool until a number of iterations thereof reaches a preset maximum number (Patent ‘342: claim 4)].
As per claim 3, Patent ‘342/Keller teaches initializing a generator pool including a plurality of generator networks [a memory configured to store an evolution pool and an input tensor-score pair; and a processor configured to sample a generator network in the evolution pool (Patent ‘342: claim 1)],
wherein the generating of the first input tensor, the obtaining of the first score, and the storing the pair of the generator network and the first score in the evolution pool, the training of the critic network, and the training of the generator network are performed on each of the plurality of generator networks [wherein the processor is configured to train the critic network and update the evolution pool until a number of iterations thereof reaches a preset maximum number (Patent ‘342: claim 4), which includes sampling a generator from the evolution pool (Patent ‘342: claim 1), thereby performing the training on each of the plurality of generator networks (of the pool)].
As per claim 4, Patent ‘342/Keller teaches wherein the training of the critic network includes:
training the critic network such that the first score is generated from the first input tensor [wherein the processor is configured to train the critic network by updating the critic network such that a predicted score calculated by the black box operation on the input tensor is closer to the output score, based on the input tensor-score pair stored in the memory (Patent ‘342: claim 3)].
As per claim 5, Patent ‘342/Keller teaches wherein the training of the generator network includes:
inferring a second score from the first input tensor by using the critic network; and
training the generator network by using a difference between the first score and the second score as a loss function [wherein the processor is configured to train the critic network by updating the critic network such that a predicted score calculated by the black box operation on the input tensor is closer to the output score, based on the input tensor-score pair stored in the memory (Patent ‘342: claim 3); where training to bring the scores closer together is using the difference between the scores as a loss function].
As per claim 6, Patent ‘342/Keller teaches sorting generator network-first score pairs of the evolution pool based on the first score [wherein the updating of the evolution pool includes: sorting the stored information based on a level of the output score (Patent ‘342: claim 5)]; and
when the number of the generator network-first score pairs of the evolution pool reaches a second threshold value, removing a generator network-first score pair including the first score having the smallest value from among the generator network-first score pairs of the evolution pool from the evolution pool such that the number of the generator network-first score pairs of the evolution pool is maintained below the second threshold value [wherein the updating of the evolution pool includes: sorting the stored information based on a level of the output score, leaving only the preset number of information in a descending order from a maximum score, and deleting a remaining portion of the information (Patent ‘342: claim 5)].
As per claim 7, Patent ‘342/Keller teaches selecting one of the generator networks of the evolution pool [sample a generator network in the evolution pool (Patent ‘342: claim 1); and wherein the processor is configured to train the critic network and update the evolution pool until a number of iterations thereof reaches a preset maximum number (Patent ‘342: claim 4), such that the sampling will occur again and again until the iteration number/threshold is met];
generating a second input tensor by using the selected generator network [generate an input tensor from the trained generator network (Patent ‘342: claim 1); repeating as described above (to generate a second input tensor)];
obtaining a third score by inputting the second input tensor to the target row refresh logic module [perform a black box operation on the input tensor and to output an output score as a result of the black box operation (Patent ‘342: claim 1); where various simulators may be used to simulate the computer assets (Keller: para. 0103, etc.) including refresh logic of rows of a DRAM memory (para. 0119, etc.), which can be used by the pattern modeling to produce a score for the hardware (Keller: paras. 0130, 0143, 0202, etc.)];
when the third score is greater than the first threshold value, storing a pair of the selected generator network and the third score in the evolution pool [and to store the input tensor and the output score in the memory as the input tensor-score pair, store information used in the black box operation in the evolution pool when the output score is greater than a minimum score stored in the memory (Patent ‘342: claim 1)];
when a second number of times of iteration is smaller than a second maximum number of times of iteration, training the critic network based on the second input tensor and the third score [wherein the processor is configured to train the critic network and update the evolution pool until a number of iterations thereof reaches a preset maximum number (Patent ‘342: claim 4)];
when the second number of times of iteration is smaller than the second maximum number of times of iteration, training the selected generator network based on a training result of the critic network [wherein the processor is configured to train the critic network and update the evolution pool until a number of iterations thereof reaches a preset maximum number (Patent ‘342: claim 4); where updating the evolution pool includes training the generator network (see Patent ‘342: claim 1)]; and
when the second number of times of iteration is smaller than the second maximum number of times of iteration, again performing the generating the second input tensor, the obtaining of the third score, and the storing the pair of the selected generator network and the third score in the evolution pool [wherein the processor is configured to train the critic network and update the evolution pool until a number of iterations thereof reaches a preset maximum number (Patent ‘342: claim 4), such that the sampling and producing tensor/scores will occur again and again until the iteration number/threshold is met].
As per claim 11, Patent ‘342/Keller teaches wherein the first input tensor does not have a boundary condition [generate an input tensor from the trained generator network (Patent ‘342: claim 1), which does not include a boundary condition].
As per claim 12, the claim is compared with claim 4 (which depends upon claim 1) of U.S. Patent No. 12,688,342—where any differences between them have been highlighted (in bold)—as follows:
Instant Application
U.S. Patent No. 12,688,342
An electronic device comprising:
a processor; and
a memory
A device comprising: a memory configured to store an evolution pool and an input tensor-score pair; and a processor [claim 1]
wherein the processor is configured to execute a simulator performing simulation of target row refresh logic of a dynamic random access memory by using the memory
initiate a simulator, trained to output a simulator parameter for a design of a semiconductor device, to perform a black box operation on the input tensor and to output an output score as a result of the black box operation, [claim 1]
wherein the simulator includes:
a first module configured to execute an algorithm of the target row refresh logic and to output a risk level as a first score
initiate a simulator, trained to output a simulator parameter for a design of a semiconductor device, to perform a black box operation on the input tensor and to output an output score as a result of the black box operation, [claim 1]
and a second module configured to perform the simulation by using the first module
and to store the input tensor and the output score in the memory as the input tensor-score pair, store information used in the black box operation in the evolution pool when the output score is greater than a minimum score stored in the memory, [claim 1]
wherein the second module includes: a generator pool including a plurality of generator networks each configured to generate an input tensor of the first module
a processor configured to sample a generator network in the evolution pool … generate an input tensor from the trained generator network [claim 1] … wherein the processor is configured to train the critic network and update the evolution pool until a number of iterations thereof reaches a preset maximum number [claim 4]
and a critic network configured to be trained to replicate the first module and to infer a second score from the input tensor
initiate a critic network to train the sampled generator network in a back- propagation manner, [claim 1] … wherein the processor is configured to train the critic network and update the evolution pool until a number of iterations thereof reaches a preset maximum number [claim 4]
wherein each of the plurality of generator networks is repeatedly trained together with the critic network
initiate a critic network to train the sampled generator network in a back- propagation manner, [claim 1] … wherein the processor is configured to train the critic network and update the evolution pool until a number of iterations thereof reaches a preset maximum number [claim 4]
wherein, in each iteration where the training is repeated, when the first score is greater than a first threshold value, a generator network corresponding to the first score is stored in an evolution pool together with the first score
and to store the input tensor and the output score in the memory as the input tensor-score pair, store information used in the black box operation in the evolution pool when the output score is greater than a minimum score stored in the memory [claim 1]
and wherein the input tensor includes patterns of row addresses
As illustrated above, claim 4 of U.S. Patent No. 12,688,342 claims all of the limitations set forth in the instant application, except for the simulation being performed being simulation of target row refresh logic of a dynamic random access memory, and wherein the input tensor includes patterns of row addresses.
Keller teaches simulation of target row refresh logic of a dynamic random access memory as [various simulators may be used to simulate the computer assets (para. 0103, etc.) including refresh logic of rows of a DRAM memory (para. 0119, etc.), which can be used by the pattern modeling to produce a score for the hardware (paras. 0130, 0143, 0202, etc.)] and wherein the input tensor includes patterns of row addresses [address lines associated with memory reads/writes can be exploited for detection of software contaminants (para. 0118, etc.) and for the row refresh only the row address is needed (para. 0119, etc.) creating hardware address and data bit patterns from data or address lines (paras. 0121-122, etc.)].
Patent ‘342 and Keller are analogous art, as they are within the same field of endeavor, namely simulating and malicious/attack/risk scoring computer hardware components.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to simulate row refresh logic of the DRAM memory as part of the modeling/scoring of the hardware components, utilizing row address patterns, as taught by Keller, as the simulator producing a simulator parameter for a design of a semiconductor device, in the claimed invention of Patent ‘342.
Keller provides motivation as [The read process in DRAM is destructive and removes the charge on the memory cells in an entire row, so there is a row of specialized latches on the chip called sense amplifiers, one for each column of memory cells, to temporarily hold the data. During a normal read operation the sense amplifiers, after reading and latching the data, rewrite the data in the accessed row before sending the bit from a single column to output. The normal read electronics on the chip has the ability to refresh an entire row of memory in parallel, significantly speeding up the refresh process. The refresh circuitry must perform a refresh cycle on each of the rows on the chip within the refresh time interval, to make sure that each cell gets refreshed (para. 0119, etc.) and particular exemplary embodiments analyze these characteristics which conceptually provide a fingerprint or fingerprints of what is anticipated and hence form a pattern or patterns. These patterns can be tracked, monitored and verified to be certain to a degree of probability or alternatively a quantified score that the hardware, firmware or software is not substantially different or modified and is only doing what was originally intended to be accomplished and that added, disabled or modified circuitry, code or algorithms have not been implemented and are not doing something unwanted behind the scenes (para. 0130) where address lines associated with memory reads/writes can be exploited for detection of software contaminants (para. 0118, etc.)].
As per claim 13, see the rejection of claim 6, above.
As per claim 14, see claim 4 of U.S. Patent No. 12,688,342.
As per claim 15, see claim 4 of U.S. Patent No. 12,688,342.
As per claim 18, see claim 3 of U.S. Patent No. 12,688,342.
As per claim 19, see claim 3 of U.S. Patent No. 12,688,342.
As per claim 20, see the rejections of claims 1 and 12, above.
Claim 8-10, 16, and 17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-7 of U.S. Patent No. 12,688,342 in view of Keller (US 2016/0098561), further in view of Esmaeilzadeh (US 2022/0269928).
As per claim 8, Patent ‘342/Keller teaches periodically regenerating the third score of a generator network from among the generator networks of the evolution pool [wherein the updating of the evolution pool includes: recalculating and rearranging scores of the stored information every set period, and leaving only information satisfying a preset condition and deleting a remaining portion of the information (Patent ‘342: claim 6)].
While Patent ‘342/Keller teaches periodically regenerating the third score of generator networks in the evolution pool, it has not been relied upon for teaching the generator network being stochastic.
Esmaeilzadeh teaches a generator network being stochastic [the generative models can include both stochastic and non-stochastic versions and/or layers (para. 0034, fig. 1; etc.)].
Patent ‘342/Keller and Esmaeilzadeh are analogous art, as they are within the same field of endeavor, namely training generator models.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include stochastic and non-stochastic generator models, as taught by Esmaeilzadeh, in the evolution pool of generator networks of Patent ‘342/Keller.
Esmaeilzadeh provides motivation as [the stochastic and non-stochastic layers/models allow each model parameter to have a unique respective learned distribution (para. 0024, etc.) and repeated inputs of the same record may product variation in corresponding outputs of those stochastic noise layers, as different values are expected to be sampled from the probability distributions in each iteration (para. 0025, etc.)].
As per claim 9, Patent ‘342/Keller teaches removing an oldest generator network from generator networks among the generator networks of the evolution pool from the evolution pool [wherein the updating of the evolution pool includes: sorting the stored information in an oldest order based on a time at which the information is stored, leaving only information having a storing time thereof after a preset timing, and deleting a remaining portion of the information (Patent ‘342: claim 7)].
While Patent ‘342/Keller teaches removing an oldest generator from the evolution pool of generator networks, it has not been relied upon for teaching (some of) the networks being non-stochastic.
Esmaeilzadeh teaches a generator network being non-stochastic [the generative models can include both stochastic and non-stochastic versions and/or layers (para. 0034, fig. 1; etc.)].
Patent ‘342/Keller and Esmaeilzadeh are analogous art, as they are within the same field of endeavor, namely training generator models.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include stochastic and non-stochastic generator models, as taught by Esmaeilzadeh, in the evolution pool of generator networks of Patent ‘342/Keller.
Esmaeilzadeh provides motivation as [the stochastic and non-stochastic layers/models allow each model parameter to have a unique respective learned distribution (para. 0024, etc.) and repeated inputs of the same record may product variation in corresponding outputs of those stochastic noise layers, as different values are expected to be sampled from the probability distributions in each iteration (para. 0025, etc.)].
As per claim 10, Patent ‘342/Keller/Esmaeilzadeh teaches training the selected generator network based on a random number [Some embodiments augment otherwise deterministic neural networks with one or more stochastic layers in which parameters of the layers (e.g., some or all of the weights of a subset of layers in a neural network) are randomly (e.g., pseudo-randomly) sampled from probability distributions (also called noise distributions, or just distributions) learned during training (Esmaeilzadeh: para. 0024, etc.) and training can include random sampling of outputs (Esmaeilzadeh: paras. 0042-47; etc.); which uses a random number in training of the generator model].
As per claim 16, see the rejection of claim 8, above.
As per claim 17, see the rejection of claim 9, above.
Allowable Subject Matter
Examiner’s Note: The cited art teaches various systems including multiple generator models, critic models, and simulation of components. However, besides the double patenting rejections described above, none of the cited art, either alone or in combination, appears to include motivation for combining the claimed elements in the manner claimed, including generating an input tensor by a generator network, inputting the input tensor to target row refresh logic module(s) to obtain a score, storing the generator and score in an evolution pool if the score is greater than a threshold, training a critic network based on the generated input tensor and score, etc., repeatedly until a threshold/max number of iteration is reached (see, e.g., claim 1).
Response to Arguments
The rejections under 35 U.S.C. 112 have been withdrawn due to the amendments filed.
Applicant's arguments filed 21 May 2026 have been fully considered but they are not persuasive.
Applicant argues that the cited art does not teach inputting a first tensor including patterns of row address to a target row refresh logic module.
However, Patent ‘342 claims initiating a simulator, trained to output a simulator parameter for a design of a semiconductor device, to perform a black box operation on the input tensor and to output an output score as a result of the black box operation (claim 1, etc.) while Keller teaches the refresh circuitry must perform a refresh cycle on each of the rows on the chip within the refresh time interval, to make sure that each cell gets refreshed. A normal read or write cycle refreshes a row of memory, but normal memory accesses cannot be relied on to hit all the rows within the necessary time, necessitating a separate refresh process. Rather than use the normal read cycle in the refresh process, to save time an abbreviated cycle called a refresh cycle is used. The refresh cycle is similar to the read cycle, but executes faster for two reasons; for a refresh, only the row address is needed, so a column address doesn't have to be applied to the chip address circuits, and data read from the cells does not need to be fed into the output buffers or the data bus to send to the CPU (para. 0119, etc.) which includes inputting row address patterns to row refresh logic.
Additionally, in response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Conclusion
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i): claims 1-20 are rejected.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hong (US 2023/0196759), Dorium (US 2023/0196760), and Hong (US 2023/0194298) – disclose systems/methods including updating an image map database with generated data based upon a discriminator score being above a specified threshold.
Lee (US 2020/0381039) – discloses a memory architecture including row refresh logic of DRAM cells, used for layers of a neural network.
Pierre (US 2023/0342454) – discloses row-hammer attack simulations including generating system degradation scores for simulated components.
Hoang et al. (MGAN: Training Generative Adversarial Nets with Multiple Generators, Oct 2017, pgs. 1-23) – discloses a system/method of training a GAN that includes training multiple generators with a single discriminator network.
Olsson et al. (Skill Rating for Generative Models, Aug 2018, pgs. 1-28) – discloses a system/method for training and evaluating generative models of GANs, including utilizing a tournament system for the generators/discriminators and assigning skill ratings.
Ohsawa et al. (Optimizing the DRAM Refresh Count for Merged DRAM/Logic LSIs, 1998, pgs. 82-87) – discloses several architectures for DRAM refresh logic to eliminate unnecessary refreshes.
Mathew et al. (Using Run-Time Reverse-Engineering to Optimize DRAM Refresh, Oct 2017, pgs. 1-11) – discloses a system/method for optimizing DRAM refresh timing parameters.
Joo (US 2021/0257019 – cited in an IDS) – discloses row control circuits for refreshing word lines at target addresses.
Lai (US 10,916,293 – cited in an IDS) – discloses row refresh logic including storing target row addresses.
Rajan (US 8,280,714) and Schakel (US 8,077,535) – disclose memory circuit simulation systems including mapping row/bank address bits to row address and bank address inputs.
The examiner requests, in response to this Office action, that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application.
When responding to this office action, Applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of the art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 CFR 1.111(c).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
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