DETAILED ACTION
The instant application having Application No. 18/114,140 filed on 2/24/2023 is presented for examination by the examiner. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. Applicant has not complied with one or more conditions for receiving the benefit of an earlier filing date under 35 U.S.C. 119(e) and 35 U.S.C. 120 as follows:
The later-filed application must be an application for a patent for an invention which is also disclosed in the prior application (the parent or original nonprovisional application or provisional application). The disclosure of the invention in the parent application and in the later-filed application must be sufficient to comply with the requirements of 35 U.S.C. 112(a) or the first paragraph of pre-AIA 35 U.S.C. 112, except for the best mode requirement. See Transco Products, Inc. v. Performance Contracting, Inc., 38 F.3d 551, 32 USPQ2d 1077 (Fed. Cir. 1994).
The disclosure(s) of the prior-filed applications, Application No. 62/958226, 62/959604, 17/027276, and 17/146101, fail to provide adequate support or enablement in the manner provided by 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph for one or more claims of this application. The Examiner does not find support for “a normalizer” comprising/including “a "0" search circuit configured to search for a position of a most significant "0" bit of first mantissa data included in input data to output first search data; a "1" search circuit configured to search for a position of a most significant "1" bit of the first mantissa data included in the input data to output second search data; a selector configured to output one selected by a bit value of first sign data of the input data between the first search data and the second search data, as selected data; an exponent adder configured to add first exponent data included in the input data and the selected data to output second exponent data included in output data; and a mantissa shifter configured to perform a shifting operation on the first mantissa data, based on the selected data to output second mantissa data included in the output data”, as is claimed in independent Claims 1 and 13. For example, the disclosures of the prior-filed applications at least fail to include Figures 79-94, which illustrates the structure and function of a normalizer comprising a “0” search circuit, a “1” search circuit, and a selector, as well as a MAC operator embodiment comprising an accumulating adder and the normalizer. Therefore, the effective filing date for all Claims 1-35 is the instant application’s actual filing date of 2/24/2023.
Similarly, the Examiner does not find support for the above described limitations in the foreign priority application KR 10-2020-0006903. Upon examination of an English language translation of the application, the Examiner does not find description of a normalizer comprising a “0” search circuit, a “1” search circuit, and a selector, nor does the foreign application include Figures 79-94 from the instant application. See § MPEP 2152.01, “If the application properly claims foreign priority under 35 U.S.C. 119(a)-(d), 365(a) or (b), or 386(a) or (b), the effective filing date of a claimed invention is the filing date of the foreign priority document if the claim is adequately supported in the foreign priority document.” See also § MPEP 216. Therefore, the effective filing date for all Claims 1-35 is the instant application’s actual filing date of 2/24/2023.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-6, 8-9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Fossum et al. (US 4,994,996) in view of Ezer et al. (US 6,256,655).
As per Claim 1, Fossum discloses a normalizer (Figure 2, a floating-point adder comprises normalization unit 18);
comprising: a “0” search circuit configured to search for a position of a most significant “0” bit of first mantissa data included in input data to output first search data; a “1” search circuit configured to search for a position of a most significant “1” bit of the first mantissa data included in the input data to output second search data (Figures 2-3 and Column 5, lines 52-66, leading-zeros detector 32 and leading-ones detector 33 output a number of shifts required to place the most significant “1” bit and most significant “0” bit, respectively, into the most significant bit position);
a selector configured to output one selected by a bit value of first sign data of the input data between the first search data and the second search data, as selected data (Figure 2 and Column 5, lines 47-51 and Column 6, lines 3-23, multiplexer 34 selects either the leading-zeros count or the leading-ones count according to the sign of the input number on bus 31);
an exponent adder configured to subtract the selected data from first exponent data included in the input data to output second exponent data included in output data (Figures 2-3 and Column 5, lines 11-21 and Column 6, lines 10-23 and Column 8, lines 1-8, exponent adjusting adder 60 decrements the result exponent EXPS by the leading-zeros or leading-ones count as selected by MUX 34);
and a mantissa shifter configured to perform a shifting operation on the first mantissa data, based on the selected data to output second mantissa data included in the output data (Figures 2-3 and Column 5, lines 11-14 and Column 6, lines 10-18, normalization shifter 35 shifts the result mantissa FRACS based on the selected leading-zeros or leading-ones count).
Fossum does not disclose a normalizer comprising an exponent adder configured to add first exponent data included in the input data and the selected data to output second exponent data included in output data.
However, Ezer teaches a floating-point normalizer comprising a leading zero/one counter (Figure 3, LZCNT 42); configured to search for a position of a most significant “0” bit and/or a most significant “1” bit of first mantissa data included in input data, wherein either the leading zero count or the leading one count is selected by a bit value of first sign data of the input data (Figure 6 and Column 11, line 65 through Column 12, line 28, a shift count and shift direction are generated by counting leading 1’s or leading 0’s based on the sign of the result/accumulator mantissa); further comprising an exponent adder configured to add first exponent data included in the input data and the selected data to output second exponent data included in output data (Figures 3, 6 and Column 12, lines 20-28 and 56-67, the shift count and shift direction generated by LSCNT 42 is provided to exponent adder 59, wherein the shift count is added to the result/accumulator exponent value based on the normalizer shift direction).
It would have been obvious to one of ordinary skill in the art prior to the effective filing of the claimed invention to combine the floating-point architecture taught by Ezer with the floating-point adder of Fossum because Ezer provides significant improvements in both time and space efficiency over prior art floating-point implementations, e.g. by eliminating the normalization step from numerous iterations of floating-point computations until the final iteration (Ezer, Abstract and Column 1, lines 45-67 and Column 2, lines 35-45 and 52-64 and Column 4, lines 15-23).
As per Claim 2, Fossum does not explicitly disclose the normalizer of claim 1, wherein the first search data output from the “0” search circuit includes: a first sign bit corresponding to a most significant bit of the first search data; and first shift bits corresponding to remaining bits except for the most significant bit among the bits of the first search data.
However, Ezer discloses the first search data output from the “0” search circuit includes: a first sign bit corresponding to a most significant bit of the first search data; and first shift bits corresponding to remaining bits except for the most significant bit among the bits of the first search data (Figure 3 and Column 11, line 65 through Column 12, line 23, LZCNT 42 generates a leading ones count comprising a shift count that can be positive or negative, wherein the sign of the shift count is output as the shift direction and the remaining bits are output as the shift count).
It would have been obvious to one of ordinary skill in the art prior to the effective filing of the claimed invention to combine the floating-point architecture taught by Ezer with the floating-point adder of Fossum because Ezer provides significant improvements in both time and space efficiency over prior art floating-point implementations, e.g. by eliminating the normalization step from numerous iterations of floating-point computations until the final iteration (Ezer, Abstract and Column 1, lines 45-67 and Column 2, lines 35-45 and 52-64 and Column 4, lines 15-23).
As per Claim 3, Fossum does not explicitly disclose the normalizer of claim 2, wherein the “0” search circuit is configured to generate a value corresponding to the number of bits by which the most significant “0” bit is to be shifted so that the most significant “0” bit is positioned immediately before the binary decimal point, based on the binary decimal point of the first mantissa data, as the first shift bits.
However, Ezer discloses the “0” search circuit is configured to generate a value corresponding to the number of bits by which the most significant “0” bit is to be shifted so that the most significant “0” bit is positioned immediately before the binary decimal point, based on the binary decimal point of the first mantissa data, as the first shift bits (Column 12, lines 13-23, a leading ones count outputs a number of bits to shift the mantissa in order to place a most significant “0” immediately before the decimal point (i.e. binary point)).
It would have been obvious to one of ordinary skill in the art prior to the effective filing of the claimed invention to combine the floating-point architecture taught by Ezer with the floating-point adder of Fossum because Ezer provides significant improvements in both time and space efficiency over prior art floating-point implementations, e.g. by eliminating the normalization step from numerous iterations of floating-point computations until the final iteration (Ezer, Abstract and Column 1, lines 45-67 and Column 2, lines 35-45 and 52-64 and Column 4, lines 15-23).
As per Claim 5, Fossum does not explicitly disclose the normalizer of claim 2, wherein the second search data output from the “1” search circuit includes: a second sign bit corresponding to a most significant bit of the second search data; and second shift bits corresponding to remaining bits except for the most significant bit among the bits of the second search data.
However, Ezer discloses the second search data output from the “1” search circuit includes: a second sign bit corresponding to a most significant bit of the second search data; and second shift bits corresponding to remaining bits except for the most significant bit among the bits of the second search data (Figure 3 and Column 11, line 65 through Column 12, line 23, LZCNT 42 generates a leading zeroes count comprising a shift count that can be positive or negative, wherein the sign of the shift count is output as the shift direction and the remaining bits are output as the shift count).
It would have been obvious to one of ordinary skill in the art prior to the effective filing of the claimed invention to combine the floating-point architecture taught by Ezer with the floating-point adder of Fossum because Ezer provides significant improvements in both time and space efficiency over prior art floating-point implementations, e.g. by eliminating the normalization step from numerous iterations of floating-point computations until the final iteration (Ezer, Abstract and Column 1, lines 45-67 and Column 2, lines 35-45 and 52-64 and Column 4, lines 15-23).
As per Claim 6, Fossum does not explicitly disclose the normalizer of claim 5, wherein the “1” search circuit is configured to generate a value corresponding to the number of bits by which the most significant “1” bit is to be shifted so that the most significant “1” bit is positioned immediately before the binary decimal point, based on the binary decimal point of the first mantissa data, as the second shift bits.
However, Ezer discloses the “1” search circuit is configured to generate a value corresponding to the number of bits by which the most significant “1” bit is to be shifted so that the most significant “1” bit is positioned immediately before the binary decimal point, based on the binary decimal point of the first mantissa data, as the second shift bits (Column 12, lines 13-23, a leading zeroes count outputs a number of bits to shift the mantissa in order to place a most significant “1” immediately before the decimal point (i.e. binary point)).
It would have been obvious to one of ordinary skill in the art prior to the effective filing of the claimed invention to combine the floating-point architecture taught by Ezer with the floating-point adder of Fossum because Ezer provides significant improvements in both time and space efficiency over prior art floating-point implementations, e.g. by eliminating the normalization step from numerous iterations of floating-point computations until the final iteration (Ezer, Abstract and Column 1, lines 45-67 and Column 2, lines 35-45 and 52-64 and Column 4, lines 15-23).
As per Claim 8, Fossum discloses the normalizer of claim 5, wherein the selector is configured to: output the first search data as the selected data when a bit value of the first sign data is “1”, and output the second search data as the selected data when the bit value of the first sign data is “0” (Figure 2 and Column 6, lines 3-8, the output of the leading-ones detector 33 is selected if the signal -/+ is “1”, indicating that the number on the bus 31 is negative).
As per Claim 9, Fossum does not explicitly disclose the normalizer of claim 8, wherein the exponent adder is configured to perform an addition operation on the first exponent data and the remaining data except for a most significant bit among bits of the selected data.
However, Ezer discloses the exponent adder is configured to perform an addition operation on the first exponent data and the remaining data except for a most significant bit among bits of the selected data (Column 11, line 65 through Column 12, line 23 and lines 56-64, LZCNT 42 generates a leading zeroes count comprising a shift count that can be positive or negative, wherein the sign of the shift count is output as the shift direction and the remaining bits are output as the shift count, wherein add/subtract unit 59 sums the shift count and accumulator exponent).
It would have been obvious to one of ordinary skill in the art prior to the effective filing of the claimed invention to combine the floating-point architecture taught by Ezer with the floating-point adder of Fossum because Ezer provides significant improvements in both time and space efficiency over prior art floating-point implementations, e.g. by eliminating the normalization step from numerous iterations of floating-point computations until the final iteration (Ezer, Abstract and Column 1, lines 45-67 and Column 2, lines 35-45 and 52-64 and Column 4, lines 15-23).
As per Claim 11, Fossum does not explicitly disclose the normalizer of claim 5, wherein the mantissa shifter is configured to shift the first mantissa data by the number of bits corresponding to a value of the remaining data of the selected data to generate the second mantissa data.
However, Ezer discloses the mantissa shifter is configured to shift the first mantissa data by the number of bits corresponding to a value of the remaining data of the selected data to generate the second mantissa data (Column 11, line 65 through Column 12, line 41, LZCNT 42 generates a leading zeroes count comprising a shift count that can be positive or negative, wherein the sign of the shift count is output as the shift direction and the remaining bits are output as the shift count, wherein shifter 46 shifts the accumulator mantissa by the number of bits corresponding to the shift count).
It would have been obvious to one of ordinary skill in the art prior to the effective filing of the claimed invention to combine the floating-point architecture taught by Ezer with the floating-point adder of Fossum because Ezer provides significant improvements in both time and space efficiency over prior art floating-point implementations, e.g. by eliminating the normalization step from numerous iterations of floating-point computations until the final iteration (Ezer, Abstract and Column 1, lines 45-67 and Column 2, lines 35-45 and 52-64 and Column 4, lines 15-23).
Claims 13, 25-26, 28-29, 31-32 and 34 are rejected under 35 U.S.C. 103 as being unpatentable over Urbanski et al. (US 2021/0263993) in view of Fossum and in view of Ezer.
As per Claim 13, Urbanski discloses a multiplication-and-accumulation (MAC) operator comprising: a multiplication circuit and adder tree configured to perform multiplication and addition operations, respectively, on weight data and vector data to generate and output multiplication addition data (Abstract and Figures 10-12, a floating-point and fixed-point dot-product circuit comprises multiplier(s) 1034/1234 and an adder tree 1046/1246 for performing multiplication and addition operations on input vectors);
and an accumulator comprising: an accumulating adder configured to perform an accumulative addition operation on the multiplication addition data and latch data to generate accumulation data (Figure 12, accumulator adder 1256 performs accumulative addition on the adder tree output 1247 and accumulator latch data 1258);
a normalizer configured to perform normalization on the accumulation data to generate normalized data, and a latch circuit configured to latch the normalized data to provide the normalized data as the latch data (Figure 12, normalization circuit 1250 normalizes the accumulation data output from accumulative adder 1256 and provides the normalized result to accumulator latch circuit 1258).
Urbanski does not explicitly disclose that the normalizer includes: a “0” search circuit configured to search for a position of a most significant “0” bit of first mantissa data included in the accumulation data to output first search data; a “1” search circuit configured to search for a position of a most significant “1” bit of the first mantissa data included in the accumulation data to output second search data; a selector configured to output one selected by a bit value of first sign data of the accumulation data between the first search data and the second search data, as selected data; an exponent adder configured to add first exponent data included in input data and the selected data to output second exponent data included in the normalized data; and a mantissa shifter configured to perform a shifting operation on the first mantissa data, based on the selected data to output second mantissa data included in the normalized data.
However, Fossum discloses a normalizer (Figure 2, a floating-point adder comprises normalization unit 18); comprising: a “0” search circuit configured to search for a position of a most significant “0” bit of first mantissa data included in input data to output first search data; a “1” search circuit configured to search for a position of a most significant “1” bit of the first mantissa data included in the input data to output second search data (Figures 2-3 and Column 5, lines 52-66, leading-zeros detector 32 and leading-ones detector 33 output a number of shifts required to place the most significant “1” bit and most significant “0” bit, respectively, into the most significant bit position); a selector configured to output one selected by a bit value of first sign data of the input data between the first search data and the second search data, as selected data (Figure 2 and Column 5, lines 47-51 and Column 6, lines 3-23, multiplexer 34 selects either the leading-zeros count or the leading-ones count according to the sign of the input number on bus 31); an exponent adder configured to subtract the selected data from first exponent data included in the input data to output second exponent data included in output data (Figures 2-3 and Column 5, lines 11-21 and Column 6, lines 10-23 and Column 8, lines 1-8, exponent adjusting adder 60 decrements the result exponent EXPS by the leading-zeros or leading-ones count as selected by MUX 34); and a mantissa shifter configured to perform a shifting operation on the first mantissa data, based on the selected data to output second mantissa data included in the output data (Figures 2-3 and Column 5, lines 11-14 and Column 6, lines 10-18, normalization shifter 35 shifts the result mantissa FRACS based on the selected leading-zeros or leading-ones count).
Moreover, Ezer teaches performing multiplication and accumulation operations on input data and weight data (Column 1, lines 35-48, filter weights); including a floating-point normalizer comprising a leading zero/one counter (Figure 3, LZCNT 42); configured to search for a position of a most significant “0” bit and/or a most significant “1” bit of first mantissa data included in input data, wherein either the leading zero count or the leading one count is selected by a bit value of first sign data of the input data (Figure 6 and Column 11, line 65 through Column 12, line 28, a shift count and shift direction are generated by counting leading 1’s or leading 0’s based on the sign of the result/accumulator mantissa); further comprising an exponent adder configured to add first exponent data included in the input data and the selected data to output second exponent data included in output data (Figures 3, 6 and Column 12, lines 20-28 and 56-67, the shift count and shift direction generated by LSCNT 42 is provided to exponent adder 59, wherein the shift count is added to the result/accumulator exponent value based on the normalizer shift direction).
It would have been obvious to one of ordinary skill in the art prior to the effective filing of the claimed invention to combine the floating-point adder architecture taught by Fossum with the accumulator and normalizer of Urbanski because it advantageously provides support for addition and subtraction while reducing computation time and reducing circuit area, as well as providing increased accuracy during normalization and rounding (Fossum, Column 3, lines 4-25). It also would have been obvious to combine the floating-point architecture taught by Ezer with the accumulator and normalizer of Urbanski as well as with the floating-point adder of Fossum because Ezer provides significant improvements in both time and space efficiency over prior art floating-point implementations, e.g. by eliminating the normalization step from numerous iterations of floating-point computations until the final iteration (Ezer, Abstract and Column 1, lines 45-67 and Column 2, lines 35-45 and 52-64 and Column 4, lines 15-23).
As per Claims 25-26, 28-29, 31-32 and 34, they recite the same limitations as claimed in Claims 2-3, 5-6, 8-9 and 11, respectively. Thus, Claims 25-26, 28-29, 31-32 and 34 are rejected under the same rationale(s) as presented in the above rejection(s) of Claims 2-3, 5-6, 8-9 and 11.
Allowable Subject Matter
Claims 4, 7, 10, 12, 14-24, 27, 30, 33 and 35 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Jiang et al. (US 5,993,051) – discloses a floating point unit (FPU) that processes normalized numbers and performs A*B±C. The FPU comprises a combined leading zero anticipator (LZA) and leading ones anticipator (LOA), wherein the output of either the LZA or the LOA is selected by a multiplexer according to the most significant bit of the result mantissa, i.e. the sign bit indicating whether the result is a positive or negative number. A post normalizer count logic converts the selected LZA or LOA output into a shift signal for a post normalizer, which shifts the result accordingly.
Brashears et al. (US 5,633,819) – discloses a floating-point adder comprising a leading-one/leading-zero predictor to predict an initial first normalization shift amount, wherein the predictor includes a first priority encoder to search for a first “1” bit in the result number, a second priority encoder to search for a first “0” bit in the result number, and a multiplexer to select one of the priority encoder outputs as the predicted shift amount according to whether the result is a negative number or positive number.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW SANDIFER whose telephone number is (571)270-5175. The examiner can normally be reached Mon-Fri 9:30am-6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Trujillo can be reached at (571) 272-3677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MATTHEW D SANDIFER/Primary Examiner, Art Unit 2151
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