Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1 and 14 have been amended. Claims 6 and 16-17 have been cancelled. Claims 1-5, 7-15, and 18-20 are currently pending and have been considered by the Examiner.
Claim Objections
Claim 14 is objected to because of the following informalities: Based on the previous claim set filed on 11/18/2024, it appears that the limitations in pending claim 14, from line 6 up to page 4, line 7 should be indented to the right.
In claim 14 on page 4, line 3, Examiner suggests changing “comprises” to “comprising” since it modifies the “identifying” limitation starting in claim 14, line 6. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 7-15, and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Henry et al. (US 20170103304 A1, cited in PTO-892 issued 02/01/2024).
Regarding claim 1, Henry teaches: A method for energy-efficient data processing, the method comprising: in response to a read operation being enabled, identifying, in a content addressable memory cell of a plurality of content addressable memory cells contained within and that control a memory device, a set of input locations from which to read input data, each of the input locations being associated with an address value for a neuron, ([0052], [0055], and Fig. 1. A neural network unit (NNU) 121 comprises data RAM 122 which is arranged as D rows of N data words, each data word is a plurality of bits, and each data word functions as the output/activation value of a neuron of the previous layer in the network. A memory address 123 is used to provision the data RAM to select one of the D rows of N data words for provision to the N neural processing units 126. The NNU is a “memory device” because it is a computing device comprising memory. A “read operation being enabled” corresponds to a read command for reading memory address 123. The “plurality of content addressable memory cells” are the individual bits storing each word in data RAM 122, which are contained within the NNU and control the NNU via multiply-accumulate operations in the NPU 126. A “set of input locations from which to read input data” is a row in the data RAM, representing an activation value to be applied as an input to a next layer’s neuron, which corresponds to “a neuron” as claimed.)
the memory device comprises summing nodes and multipliers that are embedded in the memory device; ([0052], [0060], lines 11-13, [0062], and Figs. 1 and 2. The NNU 121 includes a number of different NPUs 126. Each of these NPUs, such as NPU J shown in Fig. 2, comprises an arithmetic logic unit 204 comprising adders 224 (i.e., summing nodes) and multipliers 242. Thus, the NNU 121 (i.e., the memory device) comprises summing nodes and multipliers.)
accessing the input data in the set of input locations; ([0055] and Fig. 1. The selected row of N data words is provided (i.e., accessed) from the data RAM.)
using the input data to generate a result; and ([0064]. The selected data words are provided to NPUs 126 that generate a result 133.)
writing the result back into the memory device. ([0064]. The result 133 is written to data RAM 122.)
Regarding claim 2, Henry teaches: The method according to claim 1, further comprising associating a set of input data items with the address value for the neuron. ([0055]. The row of N data words (i.e., set of input data items) is associated with the memory address 123 for the input value to the neuron.)
Regarding claim 3, Henry teaches: The method according to claim 1, wherein two or more locations of the set of input locations are concurrently accessed. ([0055]-[0056]. The row of N data words (i.e., set of input data items) is provided/accessed at the same cycle (i.e., concurrently).)
Regarding claim 4, Henry teaches: The method according to claim 1, wherein the result is associated with the neuron. ([0064] and Figs. 1 and 2. The result 133 is an activation function result associated with a neuron implemented by a neural processing unit 126-J.)
Regarding claim 5, Henry teaches: The method according to claim 1, wherein the neuron represents a node in a fully connected network. ([0086]. The neuron is in a network having fully connected layers.)
Regarding claim 7, Henry teaches: The method according to claim 1, wherein the set of input locations are accessed in a single clock cycle. ([0056]. The row of N data words is provided/accessed in a single cycle.)
Regarding claim 8, Henry teaches: The method according to claim 2, further comprising a read source that comprises the address value for the neuron, the read source outputs a first enable signal that enables a data item among the set of input data items. ([0055], [0126]-[0128] and Figs. 1 and 16. A read port of data RAM 122 (i.e., read source) receives a memory address for a read command for an input to a neuron and activates banks of data words for a row of data words (i.e., set of input data items).)
Regarding claim 9, Henry teaches: The method according to claim 8, further comprising applying the address value to one or more write target inputs that, in response to containing the value, output a second enable signal that causes the result to be written to the data item. ([0055], [0126]-[0128] and Figs. 1 and 16. A memory address is provided to write port of data RAM 122 (i.e., a write target input) that writes the result to the corresponding location (i.e., inherently using an enable signal to activate the writing). A calculation result is written to the data RAM in response to containing the address row of the address input 123.)
Regarding claim 10, Henry teaches: The method according to claim 8, further comprising enabling at least one weight item, and multiplying the enabled data item with enabled weight items to obtain a sum of products. ([0059] and [0062]. Sequencer 128 applies a memory address to data RAM 122 and a memory address to weight RAM 124 thereby enabling at least one data item and at least one weight. Multiplier 242 multiplies a selected/enabled data word and weight to generate a product that is added/summed to other products.)
Regarding claim 11, Henry teaches: The method according to claim 10, wherein the result is associated with the sum of products that is associated with the neuron. ([0059] and [0064]. The result 133 is obtained using the accumulator output (i.e., sum of products) to generate the output of the neuron.)
Regarding claim 12, Henry teaches: The method according to claim 10, wherein generating the result further comprises applying the sum of products to an adder to obtain an output. ([0062]. The adder adds the product to an accumulated value (i.e., the sum of products) to generate output 217.)
Regarding claim 13, Henry teaches: The method according to claim 11, further comprising applying the output to an activation function to obtain the result. ([0064]. The activation function unit (AFU) applies an activation function to the accumulator output 217.)
Regarding claim 14, Henry teaches: A system for energy-efficient data processing, the system comprising: a processor; and ([0043] teaches a processor)
a non-transitory computer-readable medium comprising instructions that, when executed by the processor, cause steps to be performed, the steps comprising: ([0043] teaches a memory)
in response to a read operation being enabled, identifying, in a content addressable memory cell of a plurality of content addressable memory cells contained within and that control a memory device, a set of input locations from which to read a set of input data items, each of the input locations being associated with an address value for a neuron, ([0052], [0055], and Fig. 1. A neural network unit (NNU) 121 comprises data RAM 122 which is arranged as D rows of N data words, each data word is a plurality of bits, and each data word functions as the output/activation value of a neuron of the previous layer in the network. A memory address 123 is used to provision the data RAM to select one of the D rows of N data words for provision to the N neural processing units 126. The NNU is a “memory device” because it is a computing device comprising memory. A “read operation being enabled” corresponds to a read command for reading memory address 123. The “plurality of content addressable memory cells” are the individual bits storing each word in data RAM 122, which are contained within the NNU and control the NNU via multiply-accumulate operations in the NPU 126. A “set of input locations from which to read input data” is a row in the data RAM, representing an activation value to be applied as an input to a next layer’s neuron, which corresponds to “a neuron” as claimed.)
the memory device comprises summing nodes and multipliers that are embedded in the memory device; ([0052], [0060], lines 11-13, [0062], and Figs. 1 and 2. The NNU 121 includes a number of different NPUs 126. Each of these NPUs, such as NPU J shown in Fig. 2, comprises an arithmetic logic unit 204 comprising adders 224 (i.e., summing nodes) and multipliers 242. Thus, the NNU 121 (i.e., the memory device) comprises summing nodes and multipliers.)
accessing the set of input data items in the set of input locations; ([0055] and Fig. 1. The selected row of N data words is provided (i.e., accessed) from the data RAM.)
using the set of input data items to generate a result; and ([0064]. The selected data words are provided to NPUs 126 that generate a result 133.)
writing the result back into the memory device; ([0064]. The result 133 is written to data RAM 122.)
a read source that comprises the address value for the neuron, the read source outputs a first enable signal that enables a data item among the set of input data items. ([0052], [0055], [0126]-[0128] and Figs. 1 and 16. A read port (i.e., read source) of data RAM 122 receives a memory address for a read command for an input to a neuron and activates banks of data words for a row of data words (i.e., set of input data items).)
Claim 15 recites a system which implements the same features as the method of claim 3 and is therefore rejected for at least the same reasons.
Regarding claim 18, Henry teaches: The system according to claim 14, wherein the steps further comprise applying the address value to one or more write target inputs that, in response to containing the value, output a second enable signal that causes the result to be written to the data item. ([0055], [0126]-[0128] and Figs. 1 and 16. A memory address is provided to a write port of data RAM 122 (i.e., a write target input) that writes the result to the corresponding location (i.e., inherently using an enable signal to activate the writing). A calculation result is written to the data RAM in response to containing the address row of the address input 123.)
Regarding claim 19, Henry teaches: The system according to claim 14, wherein the steps further comprise enabling at least one weight item, and multiplying the enabled data item with enabled weight items to obtain a sum of products. ([0059] and [0062]. Sequencer 128 applies a memory address to data RAM 122 and a memory address to weight RAM 124 thereby enabling at least one data item and at least one weight. Multiplier 242 multiplies a selected/enabled data word and weight to generate a product that is added/summed to other products.)
Regarding claim 20, Henry teaches: The system according to claim 19, wherein the result is associated with the sum of products that is associated with the neuron. ([0059] and [0064]. The result 133 is obtained using the accumulator output (i.e., sum of products) to generate the output of the neuron.)
Response to Arguments
The following is the Examiner’s response to the Applicant’s arguments filed on 08/12/2025.
Applicant’s Arguments Under 35 U.S.C. 102 (pages 5-6): Without conceding to the propriety of the rejection, Applicant respectfully submits that the neural processing unit of Henry cannot teach or suggest the claimed memory device because the claimed memory device further contains “a content addressable memory cell of a plurality of content addressable memory cells.” Moreover, the memory device is controlled by such plurality of content addressable memory cells. On the other hand, the neural processing unit of Henry operates as a neuron or node in an artificial neural network. Henry at ¶ 59. The neural processing unit is not a memory device controlled by various content addressable memory cells.
Accordingly, Henry fails to teach or suggest “a set of input locations” being identified within “a content addressable memory cell of a plurality of content addressable memory cells contained within and that control a memory device,” as recited in claim 1.
Examiner’s Response: Applicant's arguments have been fully considered but they are not persuasive. The arguments appear to mischaracterize the prior art rejection of claim 1 over Henry. In the previous and current prior art rejections, the limitation “a memory device” corresponds to neural network unit 121 as disclosed in paragraphs 52 and Fig. 1. The neural network unit comprises both a data RAM 122 and neural processing units 126. A memory device is any computing device with memory. The memory device corresponds to a combination of at least the data RAM and the neural processing units.
Henry teaches the limitation “identifying, in a content addressable memory cell of a plurality of content addressable memory cells contained within and that control a memory device, a set of input locations from which to read input data” at [0052], [0055], and Fig. 1. As explained above, a neural network unit (NNU) 121 comprises data RAM 122 which is arranged as D rows of N data words, each data word is a plurality of bits, and each data word functions as the output/activation value of a neuron of the previous layer in the network. A memory address 123 is used to provision the data RAM to select one of the D rows of N data words for provision to the N neural processing units 126. Each “content addressable memory cell” is an individual bit within each word in data RAM 122, which are contained within the NNU and control the NNU via multiply-accumulate operations in the NPU 126. A “set of input locations from which to read input data” is a row in the data RAM, representing an activation value to be applied as an input to a next layer’s neuron, which corresponds to “a neuron” as claimed. Regarding the limitation “writing the result back into the memory device”, Henry at [0064] on page 7, col. 1, lines 14-16 teaches the result 133 is written to data RAM 122.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Asher H. Jablon whose telephone number is (571)270-7648. The examiner can normally be reached Monday - Friday, 9:00 am - 6:00 pm.
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/A.H.J./Examiner, Art Unit 2127
/ABDULLAH AL KAWSAR/Supervisory Patent Examiner, Art Unit 2127
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